rob.hh

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/*
 * Copyright (c) 2012 ARM Limited
 * All rights reserved
 *
 * The license below extends only to copyright in the software and shall
 * not be construed as granting a license to any other intellectual
 * property including but not limited to intellectual property relating
 * to a hardware implementation of the functionality of the software
 * licensed hereunder.  You may use the software subject to the license
 * terms below provided that you ensure that this notice is replicated
 * unmodified and in its entirety in all distributions of the software,
 * modified or unmodified, in source code or in binary form.
 *
 * Copyright (c) 2004-2006 The Regents of The University of Michigan
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions are
 * met: redistributions of source code must retain the above copyright
 * notice, this list of conditions and the following disclaimer;
 * redistributions in binary form must reproduce the above copyright
 * notice, this list of conditions and the following disclaimer in the
 * documentation and/or other materials provided with the distribution;
 * neither the name of the copyright holders nor the names of its
 * contributors may be used to endorse or promote products derived from
 * this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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 *
 * Authors: Kevin Lim
 *          Korey Sewell
 */

#ifndef __CPU_O3_ROB_HH__
#define __CPU_O3_ROB_HH__

#include <string>
#include <utility>
#include <vector>

#include "arch/registers.hh"
#include "base/types.hh"
#include "config/the_isa.hh"
#include "enums/SMTQueuePolicy.hh"

struct DerivO3CPUParams;

template <class Impl>
class ROB
{
  public:
    //Typedefs from the Impl.
    typedef typename Impl::O3CPU O3CPU;
    typedef typename Impl::DynInstPtr DynInstPtr;

    typedef std::pair<RegIndex, PhysRegIndex> UnmapInfo;
    typedef typename std::list<DynInstPtr>::iterator InstIt;

    enum Status {
        Running,
        Idle,
        ROBSquashing
    };

  private:
    Status robStatus[Impl::MaxThreads];

    SMTQueuePolicy robPolicy;

  public:
    ROB(O3CPU *_cpu, DerivO3CPUParams *params);

    std::string name() const;

    void setActiveThreads(std::list<ThreadID> *at_ptr);

    void drainSanityCheck() const;

    void takeOverFrom();

    void insertInst(const DynInstPtr &inst);

//    DynInstPtr readHeadInst();

    const DynInstPtr &readHeadInst(ThreadID tid);

    DynInstPtr findInst(ThreadID tid, InstSeqNum squash_inst);

//    DynInstPtr readTailInst();

    DynInstPtr readTailInst(ThreadID tid);

//    void retireHead();

    void retireHead(ThreadID tid);

//    bool isHeadReady();

    bool isHeadReady(ThreadID tid);

    bool canCommit();

    void resetEntries();

    int entryAmount(ThreadID num_threads);

    unsigned numFreeEntries();

    unsigned numFreeEntries(ThreadID tid);

    unsigned getMaxEntries(ThreadID tid)
    { return maxEntries[tid]; }

    unsigned getThreadEntries(ThreadID tid)
    { return threadEntries[tid]; }

    bool isFull()
    { return numInstsInROB == numEntries; }

    bool isFull(ThreadID tid)
    { return threadEntries[tid] == numEntries; }

    bool isEmpty() const
    { return numInstsInROB == 0; }

    bool isEmpty(ThreadID tid) const
    { return threadEntries[tid] == 0; }

    void doSquash(ThreadID tid);

    void squash(InstSeqNum squash_num, ThreadID tid);

    void updateHead();

    void updateTail();

//    uint64_t readHeadPC();

//    uint64_t readHeadPC(ThreadID tid);

//    uint64_t readHeadNextPC();

//    uint64_t readHeadNextPC(ThreadID tid);

//    InstSeqNum readHeadSeqNum();

//    InstSeqNum readHeadSeqNum(ThreadID tid);

//    uint64_t readTailPC();

//    uint64_t readTailPC(ThreadID tid);

//    InstSeqNum readTailSeqNum();

//    InstSeqNum readTailSeqNum(ThreadID tid);

    bool isDoneSquashing(ThreadID tid) const
    { return doneSquashing[tid]; }

    bool isDoneSquashing();

    int countInsts();

    size_t countInsts(ThreadID tid);

    void regStats();

  private:
    void resetState();

    O3CPU *cpu;

    std::list<ThreadID> *activeThreads;

    unsigned numEntries;

    unsigned threadEntries[Impl::MaxThreads];

    unsigned maxEntries[Impl::MaxThreads];

    std::list<DynInstPtr> instList[Impl::MaxThreads];

    unsigned squashWidth;

  public:
    InstIt tail;

    InstIt head;

  private:
    InstIt squashIt[Impl::MaxThreads];

  public:
    int numInstsInROB;

    DynInstPtr dummyInst;

  private:
    InstSeqNum squashedSeqNum[Impl::MaxThreads];

    bool doneSquashing[Impl::MaxThreads];

    ThreadID numThreads;

    // The number of rob_reads
    Stats::Scalar robReads;
    // The number of rob_writes
    Stats::Scalar robWrites;
};

#endif //__CPU_O3_ROB_HH__