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mmapped_ipr.hh
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1 /*
2  * Copyright (c) 2006 The Regents of The University of Michigan
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28  * Authors: Ali Saidi
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30 
31 #ifndef __ARCH_SPARC_MMAPPED_IPR_HH__
32 #define __ARCH_SPARC_MMAPPED_IPR_HH__
33 
40 #include "arch/sparc/tlb.hh"
41 #include "cpu/thread_context.hh"
42 #include "mem/packet.hh"
43 
44 namespace SparcISA
45 {
46 
47 inline Cycles
48 handleIprRead(ThreadContext *xc, Packet *pkt)
49 {
50  return dynamic_cast<TLB *>(xc->getDTBPtr())->doMmuRegRead(xc, pkt);
51 }
52 
53 inline Cycles
54 handleIprWrite(ThreadContext *xc, Packet *pkt)
55 {
56  return dynamic_cast<TLB *>(xc->getDTBPtr())->doMmuRegWrite(xc, pkt);
57 }
58 
59 
60 } // namespace SparcISA
61 
62 #endif
Cycles
Cycles is a wrapper class for representing cycle counts, i.e.
Definition: types.hh:83
ThreadContext::getDTBPtr
virtual BaseTLB * getDTBPtr()=0
ThreadContext
ThreadContext is the external interface to all thread state for anything outside of the CPU...
Definition: thread_context.hh:93
SparcISA::handleIprRead
Cycles handleIprRead(ThreadContext *xc, Packet *pkt)
Definition: mmapped_ipr.hh:48
Packet
A Packet is used to encapsulate a transfer between two objects in the memory system (e...
Definition: packet.hh:255
SparcISA::handleIprWrite
Cycles handleIprWrite(ThreadContext *xc, Packet *pkt)
Definition: mmapped_ipr.hh:54
thread_context.hh
packet.hh
Declaration of the Packet class.
SparcISA
Definition: asi.cc:34
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