gem5  v20.1.0.0
armv8_cpu.cc
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37 
39 
40 #include <linux/kvm.h>
41 
42 #include "debug/KvmContext.hh"
43 #include "params/ArmV8KvmCPU.hh"
44 
45 using namespace ArmISA;
46 
47 // Unlike gem5, kvm doesn't count the SP as a normal integer register,
48 // which means we only have 31 normal integer registers.
49 constexpr static unsigned NUM_XREGS = NUM_ARCH_INTREGS - 1;
50 static_assert(NUM_XREGS == 31, "Unexpected number of aarch64 int. regs.");
51 
52 // The KVM interface accesses vector registers of 4 single precision
53 // floats instead of individual registers.
54 constexpr static unsigned NUM_QREGS = NumVecV8ArchRegs;
55 static_assert(NUM_QREGS == 32, "Unexpected number of aarch64 vector regs.");
56 
57 #define EXTRACT_FIELD(v, name) \
58  (((v) & name ## _MASK) >> name ## _SHIFT)
59 
60 #define CORE_REG(name, size) \
61  (KVM_REG_ARM64 | KVM_REG_ARM_CORE | \
62  KVM_REG_SIZE_ ## size | \
63  KVM_REG_ARM_CORE_REG(name))
64 
65 #define INT_REG(name) CORE_REG(name, U64)
66 #define SIMD_REG(name) CORE_REG(name, U128)
67 
68 #define SYS_MPIDR_EL1 ARM64_SYS_REG(0b11, 0b000, 0b0000, 0b0000, 0b101)
69 
70 constexpr uint64_t
71 kvmXReg(const int num)
72 {
73  return INT_REG(regs.regs[0]) +
74  (INT_REG(regs.regs[1]) - INT_REG(regs.regs[0])) * num;
75 }
76 
77 constexpr uint64_t
78 kvmFPReg(const int num)
79 {
80  return SIMD_REG(fp_regs.vregs[0]) +
81  (SIMD_REG(fp_regs.vregs[1]) - SIMD_REG(fp_regs.vregs[0])) * num;
82 }
83 
84 union KvmFPReg {
85  union {
86  uint32_t i;
87  float f;
88  } s[4];
89 
90  union {
91  uint64_t i;
92  double f;
93  } d[2];
94 
95  uint8_t data[32];
96 };
97 
98 #define FP_REGS_PER_VFP_REG 4
99 
101  { INT_REG(regs.sp), INTREG_SP0, "SP(EL0)" },
102  { INT_REG(sp_el1), INTREG_SP1, "SP(EL1)" },
103 };
104 
106  MiscRegInfo(INT_REG(elr_el1), MISCREG_ELR_EL1, "ELR(EL1)"),
107  MiscRegInfo(INT_REG(spsr[KVM_SPSR_EL1]), MISCREG_SPSR_EL1, "SPSR(EL1)"),
108  MiscRegInfo(INT_REG(spsr[KVM_SPSR_ABT]), MISCREG_SPSR_ABT, "SPSR(ABT)"),
109  MiscRegInfo(INT_REG(spsr[KVM_SPSR_UND]), MISCREG_SPSR_UND, "SPSR(UND)"),
110  MiscRegInfo(INT_REG(spsr[KVM_SPSR_IRQ]), MISCREG_SPSR_IRQ, "SPSR(IRQ)"),
111  MiscRegInfo(INT_REG(spsr[KVM_SPSR_FIQ]), MISCREG_SPSR_FIQ, "SPSR(FIQ)"),
112  MiscRegInfo(CORE_REG(fp_regs.fpsr, U32), MISCREG_FPSR, "FPSR"),
113  MiscRegInfo(CORE_REG(fp_regs.fpcr, U32), MISCREG_FPCR, "FPCR"),
114 };
115 
116 const std::set<MiscRegIndex> ArmV8KvmCPU::deviceRegSet = {
120 };
121 
124 };
125 
126 ArmV8KvmCPU::ArmV8KvmCPU(ArmV8KvmCPUParams *params)
127  : BaseArmKvmCPU(params)
128 {
129 }
130 
132 {
133 }
134 
135 void
137 {
139 
140  // Override ID registers that KVM should "inherit" from gem5.
141  for (const auto &ri : miscRegIdMap) {
142  const uint64_t value(tc->readMiscReg(ri.idx));
143  DPRINTF(KvmContext, " %s := 0x%x\n", ri.name, value);
144  setOneReg(ri.kvm, value);
145  }
146 }
147 
148 void
150 {
151  inform("Integer registers:\n");
152  inform(" PC: %s\n", getAndFormatOneReg(INT_REG(regs.pc)));
153  for (int i = 0; i < NUM_XREGS; ++i)
154  inform(" X%i: %s\n", i, getAndFormatOneReg(kvmXReg(i)));
155 
156  for (int i = 0; i < NUM_QREGS; ++i)
157  inform(" Q%i: %s\n", i, getAndFormatOneReg(kvmFPReg(i)));
158 
159  for (const auto &ri : intRegMap)
160  inform(" %s: %s\n", ri.name, getAndFormatOneReg(ri.kvm));
161 
162  inform(" %s: %s\n", "PSTATE", getAndFormatOneReg(INT_REG(regs.pstate)));
163 
164  for (const auto &ri : miscRegMap)
165  inform(" %s: %s\n", ri.name, getAndFormatOneReg(ri.kvm));
166 
167  for (const auto &ri : miscRegIdMap)
168  inform(" %s: %s\n", ri.name, getAndFormatOneReg(ri.kvm));
169 
170  for (const auto &reg : getRegList()) {
171  const uint64_t arch(reg & KVM_REG_ARCH_MASK);
172  if (arch != KVM_REG_ARM64) {
173  inform("0x%x: %s\n", reg, getAndFormatOneReg(reg));
174  continue;
175  }
176 
177  const uint64_t type(reg & KVM_REG_ARM_COPROC_MASK);
178  switch (type) {
179  case KVM_REG_ARM_CORE:
180  // These have already been printed
181  break;
182 
183  case KVM_REG_ARM64_SYSREG: {
184  const uint64_t op0(EXTRACT_FIELD(reg, KVM_REG_ARM64_SYSREG_OP0));
185  const uint64_t op1(EXTRACT_FIELD(reg, KVM_REG_ARM64_SYSREG_OP1));
186  const uint64_t crn(EXTRACT_FIELD(reg, KVM_REG_ARM64_SYSREG_CRN));
187  const uint64_t crm(EXTRACT_FIELD(reg, KVM_REG_ARM64_SYSREG_CRM));
188  const uint64_t op2(EXTRACT_FIELD(reg, KVM_REG_ARM64_SYSREG_OP2));
189  const MiscRegIndex idx(
190  decodeAArch64SysReg(op0, op1, crn, crm, op2));
191 
192  inform(" %s (op0: %i, op1: %i, crn: %i, crm: %i, op2: %i): %s",
193  miscRegName[idx], op0, op1, crn, crm, op2,
195  } break;
196 
197  case KVM_REG_ARM_DEMUX: {
198  const uint64_t id(EXTRACT_FIELD(reg, KVM_REG_ARM_DEMUX_ID));
199  const uint64_t val(EXTRACT_FIELD(reg, KVM_REG_ARM_DEMUX_VAL));
200  if (id == KVM_REG_ARM_DEMUX_ID_CCSIDR) {
201  inform(" CSSIDR[%i]: %s\n", val,
203  } else {
204  inform(" UNKNOWN[%i:%i]: %s\n", id, val,
206  }
207  } break;
208 
209  default:
210  inform("0x%x: %s\n", reg, getAndFormatOneReg(reg));
211  }
212  }
213 }
214 
215 void
217 {
218  DPRINTF(KvmContext, "In updateKvmState():\n");
219 
220  // update pstate register state
221  CPSR cpsr(tc->readMiscReg(MISCREG_CPSR));
222  cpsr.nz = tc->readCCReg(CCREG_NZ);
223  cpsr.c = tc->readCCReg(CCREG_C);
224  cpsr.v = tc->readCCReg(CCREG_V);
225  if (cpsr.width) {
226  cpsr.ge = tc->readCCReg(CCREG_GE);
227  } else {
228  cpsr.ge = 0;
229  }
230  DPRINTF(KvmContext, " %s := 0x%x\n", "PSTATE", cpsr);
231  setOneReg(INT_REG(regs.pstate), static_cast<uint64_t>(cpsr));
232 
233  for (const auto &ri : miscRegMap) {
234  const uint64_t value(tc->readMiscReg(ri.idx));
235  DPRINTF(KvmContext, " %s := 0x%x\n", ri.name, value);
236  setOneReg(ri.kvm, value);
237  }
238 
239  for (int i = 0; i < NUM_XREGS; ++i) {
240  const uint64_t value(tc->readIntReg(INTREG_X0 + i));
241  DPRINTF(KvmContext, " X%i := 0x%x\n", i, value);
242  setOneReg(kvmXReg(i), value);
243  }
244 
245  for (const auto &ri : intRegMap) {
246  const uint64_t value(tc->readIntReg(ri.idx));
247  DPRINTF(KvmContext, " %s := 0x%x\n", ri.name, value);
248  setOneReg(ri.kvm, value);
249  }
250 
251  for (int i = 0; i < NUM_QREGS; ++i) {
252  KvmFPReg reg;
253  auto v = tc->readVecReg(RegId(VecRegClass, i)).as<VecElem>();
254  for (int j = 0; j < FP_REGS_PER_VFP_REG; j++)
255  reg.s[j].i = v[j];
256 
257  setOneReg(kvmFPReg(i), reg.data);
258  DPRINTF(KvmContext, " Q%i: %s\n", i, getAndFormatOneReg(kvmFPReg(i)));
259  }
260 
261  for (const auto &ri : getSysRegMap()) {
262  uint64_t value;
263  if (ri.is_device) {
264  // This system register is backed by a device. This means
265  // we need to lock the device event queue.
267 
268  value = tc->readMiscReg(ri.idx);
269  } else {
270  value = tc->readMiscReg(ri.idx);
271  }
272 
273  DPRINTF(KvmContext, " %s := 0x%x\n", ri.name, value);
274  setOneReg(ri.kvm, value);
275  }
276 
277  setOneReg(INT_REG(regs.pc), tc->instAddr());
278  DPRINTF(KvmContext, " PC := 0x%x\n", tc->instAddr());
279 }
280 
281 void
283 {
284  DPRINTF(KvmContext, "In updateThreadContext():\n");
285 
286  // Update pstate thread context
287  const CPSR cpsr(getOneRegU64(INT_REG(regs.pstate)));
288  DPRINTF(KvmContext, " %s := 0x%x\n", "PSTATE", cpsr);
290  tc->setCCReg(CCREG_NZ, cpsr.nz);
291  tc->setCCReg(CCREG_C, cpsr.c);
292  tc->setCCReg(CCREG_V, cpsr.v);
293  if (cpsr.width) {
294  tc->setCCReg(CCREG_GE, cpsr.ge);
295  }
296 
297  // Update core misc regs first as they
298  // affect how other registers are mapped.
299  for (const auto &ri : miscRegMap) {
300  const auto value(getOneRegU64(ri.kvm));
301  DPRINTF(KvmContext, " %s := 0x%x\n", ri.name, value);
302  tc->setMiscRegNoEffect(ri.idx, value);
303  }
304 
305  for (int i = 0; i < NUM_XREGS; ++i) {
306  const auto value(getOneRegU64(kvmXReg(i)));
307  DPRINTF(KvmContext, " X%i := 0x%x\n", i, value);
308  // KVM64 returns registers in 64-bit layout. If we are in aarch32
309  // mode, we need to map these to banked ARM32 registers.
310  if (inAArch64(tc)) {
311  tc->setIntReg(INTREG_X0 + i, value);
312  } else {
313  tc->setIntRegFlat(IntReg64Map[INTREG_X0 + i], value);
314  }
315  }
316 
317  for (const auto &ri : intRegMap) {
318  const auto value(getOneRegU64(ri.kvm));
319  DPRINTF(KvmContext, " %s := 0x%x\n", ri.name, value);
320  tc->setIntReg(ri.idx, value);
321  }
322 
323  for (int i = 0; i < NUM_QREGS; ++i) {
324  KvmFPReg reg;
325  DPRINTF(KvmContext, " Q%i: %s\n", i, getAndFormatOneReg(kvmFPReg(i)));
326  getOneReg(kvmFPReg(i), reg.data);
328  for (int j = 0; j < FP_REGS_PER_VFP_REG; j++)
329  v[j] = reg.s[j].i;
330  }
331 
332  for (const auto &ri : getSysRegMap()) {
333  const auto value(getOneRegU64(ri.kvm));
334  DPRINTF(KvmContext, " %s := 0x%x\n", ri.name, value);
335  if (ri.is_device) {
336  // This system register is backed by a device. This means
337  // we need to lock the device event queue.
339 
340  tc->setMiscReg(ri.idx, value);
341  } else {
342  tc->setMiscRegNoEffect(ri.idx, value);
343  }
344  }
345 
346  PCState pc(getOneRegU64(INT_REG(regs.pc)));
347  pc.aarch64(inAArch64(tc));
348  pc.thumb(cpsr.t);
349  pc.nextAArch64(inAArch64(tc));
350  // TODO: This is a massive assumption that will break when
351  // switching to thumb.
352  pc.nextThumb(cpsr.t);
353  DPRINTF(KvmContext, " PC := 0x%x (t: %i, a64: %i)\n",
354  pc.instAddr(), pc.thumb(), pc.aarch64());
355  tc->pcState(pc);
356 }
357 
360 {
361  // Try to use the cached map
362  if (!sysRegMap.empty())
363  return sysRegMap;
364 
365  for (const auto &reg : getRegList()) {
366  const uint64_t arch(reg & KVM_REG_ARCH_MASK);
367  if (arch != KVM_REG_ARM64)
368  continue;
369 
370  const uint64_t type(reg & KVM_REG_ARM_COPROC_MASK);
371  if (type != KVM_REG_ARM64_SYSREG)
372  continue;
373 
374  const uint64_t op0(EXTRACT_FIELD(reg, KVM_REG_ARM64_SYSREG_OP0));
375  const uint64_t op1(EXTRACT_FIELD(reg, KVM_REG_ARM64_SYSREG_OP1));
376  const uint64_t crn(EXTRACT_FIELD(reg, KVM_REG_ARM64_SYSREG_CRN));
377  const uint64_t crm(EXTRACT_FIELD(reg, KVM_REG_ARM64_SYSREG_CRM));
378  const uint64_t op2(EXTRACT_FIELD(reg, KVM_REG_ARM64_SYSREG_OP2));
379  const MiscRegIndex idx(decodeAArch64SysReg(op0, op1, crn, crm, op2));
380  const auto &info(miscRegInfo[idx]);
381  const bool writeable(
382  info[MISCREG_USR_NS_WR] || info[MISCREG_USR_S_WR] ||
383  info[MISCREG_PRI_S_WR] || info[MISCREG_PRI_NS_WR] ||
384  info[MISCREG_HYP_WR] ||
385  info[MISCREG_MON_NS0_WR] || info[MISCREG_MON_NS1_WR]);
386  const bool implemented(
388 
389  // Only add implemented registers that we are going to be able
390  // to write.
391  if (implemented && writeable)
392  sysRegMap.emplace_back(reg, idx, miscRegName[idx],
393  deviceRegSet.find(idx) != deviceRegSet.end());
394  }
395 
396  return sysRegMap;
397 }
398 
399 ArmV8KvmCPU *
400 ArmV8KvmCPUParams::create()
401 {
402  return new ArmV8KvmCPU(this);
403 }
BaseKvmCPU::setOneReg
void setOneReg(uint64_t id, const void *addr)
Get/Set single register using the KVM_(SET|GET)_ONE_REG API.
Definition: base.cc:841
ArmISA::IntReg64Map
const IntRegMap IntReg64Map
Definition: intregs.hh:304
ArmV8KvmCPU::miscRegMap
static const std::vector< ArmV8KvmCPU::MiscRegInfo > miscRegMap
Mapping between gem5 misc registers and registers in kvm.
Definition: armv8_cpu.hh:138
ArmISA::MISCREG_IMPLEMENTED
@ MISCREG_IMPLEMENTED
Definition: miscregs.hh:1092
INT_REG
#define INT_REG(name)
Definition: armv8_cpu.cc:65
ArmISA::CCREG_NZ
@ CCREG_NZ
Definition: ccregs.hh:45
ArmV8KvmCPU::~ArmV8KvmCPU
virtual ~ArmV8KvmCPU()
Definition: armv8_cpu.cc:131
data
const char data[]
Definition: circlebuf.test.cc:42
ArmISA::MISCREG_SPSR_UND
@ MISCREG_SPSR_UND
Definition: miscregs.hh:65
ThreadContext::getWritableVecReg
virtual VecRegContainer & getWritableVecReg(const RegId &reg)=0
ArmISA::i
Bitfield< 7 > i
Definition: miscregs_types.hh:63
NUM_XREGS
constexpr static unsigned NUM_XREGS
Definition: armv8_cpu.cc:49
BaseKvmCPU::getAndFormatOneReg
std::string getAndFormatOneReg(uint64_t id) const
Get and format one register for printout.
Definition: base.cc:875
ArmISA::MISCREG_FPSR
@ MISCREG_FPSR
Definition: miscregs.hh:614
ArmISA::MISCREG_CNTV_CVAL_EL0
@ MISCREG_CNTV_CVAL_EL0
Definition: miscregs.hh:752
type
uint8_t type
Definition: inet.hh:421
ThreadContext::setIntReg
virtual void setIntReg(RegIndex reg_idx, RegVal val)=0
ArmV8KvmCPU::getSysRegMap
const std::vector< ArmV8KvmCPU::MiscRegInfo > & getSysRegMap() const
Get a map between system registers in kvm and gem5 registers.
Definition: armv8_cpu.cc:359
ArmV8KvmCPU
This is an implementation of a KVM-based ARMv8-compatible CPU.
Definition: armv8_cpu.hh:79
SYS_MPIDR_EL1
#define SYS_MPIDR_EL1
Definition: armv8_cpu.cc:68
ArmISA::CCREG_V
@ CCREG_V
Definition: ccregs.hh:47
ArmISA::MISCREG_MON_NS0_WR
@ MISCREG_MON_NS0_WR
Definition: miscregs.hh:1129
ArmISA::MISCREG_USR_NS_WR
@ MISCREG_USR_NS_WR
Definition: miscregs.hh:1113
std::vector< ArmV8KvmCPU::IntRegInfo >
KvmFPReg::f
double f
Definition: armv8_cpu.cc:92
ArmV8KvmCPU::miscRegIdMap
static const std::vector< ArmV8KvmCPU::MiscRegInfo > miscRegIdMap
Mapping between gem5 ID misc registers and registers in kvm.
Definition: armv8_cpu.hh:142
ArmV8KvmCPU::updateThreadContext
void updateThreadContext() override
Update the current thread context with the KVM state.
Definition: armv8_cpu.cc:282
ArmISA::MISCREG_ELR_EL1
@ MISCREG_ELR_EL1
Definition: miscregs.hh:606
ArmISA::MISCREG_CNTV_CTL_EL0
@ MISCREG_CNTV_CTL_EL0
Definition: miscregs.hh:751
BaseKvmCPU::getOneReg
void getOneReg(uint64_t id, void *addr) const
Definition: base.cc:858
ArmISA::NumVecV8ArchRegs
const int NumVecV8ArchRegs
Definition: registers.hh:94
ArmISA::miscRegName
const char *const miscRegName[]
Definition: miscregs.hh:1159
ArmISA
Definition: ccregs.hh:41
X86ISA::reg
Bitfield< 5, 3 > reg
Definition: types.hh:87
BaseKvmCPU::getOneRegU64
uint64_t getOneRegU64(uint64_t id) const
Definition: base.hh:370
ArmISA::MISCREG_CNTKCTL_EL1
@ MISCREG_CNTKCTL_EL1
Definition: miscregs.hh:760
RegId
Register ID: describe an architectural register with its class and index.
Definition: reg_class.hh:75
VecRegContainer::as
VecRegT< VecElem, NumElems, true > as() const
View interposers.
Definition: vec_reg.hh:386
armv8_cpu.hh
ArmISA::CCREG_GE
@ CCREG_GE
Definition: ccregs.hh:48
ArmISA::CCREG_C
@ CCREG_C
Definition: ccregs.hh:46
kvmXReg
constexpr uint64_t kvmXReg(const int num)
Definition: armv8_cpu.cc:71
ArmISA::j
Bitfield< 24 > j
Definition: miscregs_types.hh:54
ArmISA::VecElem
uint32_t VecElem
Definition: registers.hh:68
ArmISA::MISCREG_USR_S_WR
@ MISCREG_USR_S_WR
Definition: miscregs.hh:1115
ArmV8KvmCPU::updateKvmState
void updateKvmState() override
Update the KVM state from the current thread context.
Definition: armv8_cpu.cc:216
ArmV8KvmCPU::ArmV8KvmCPU
ArmV8KvmCPU(ArmV8KvmCPUParams *params)
Definition: armv8_cpu.cc:126
DPRINTF
#define DPRINTF(x,...)
Definition: trace.hh:234
ThreadContext::setIntRegFlat
virtual void setIntRegFlat(RegIndex idx, RegVal val)=0
ArmISA::d
Bitfield< 9 > d
Definition: miscregs_types.hh:60
MipsISA::pc
Bitfield< 4 > pc
Definition: pra_constants.hh:240
FP_REGS_PER_VFP_REG
#define FP_REGS_PER_VFP_REG
Definition: armv8_cpu.cc:98
ArmISA::MISCREG_SPSR_IRQ
@ MISCREG_SPSR_IRQ
Definition: miscregs.hh:60
ArmISA::MISCREG_SPSR_ABT
@ MISCREG_SPSR_ABT
Definition: miscregs.hh:63
ThreadContext::readVecReg
virtual const VecRegContainer & readVecReg(const RegId &reg) const =0
ArmISA::MISCREG_HYP_WR
@ MISCREG_HYP_WR
Definition: miscregs.hh:1123
SIMD_REG
#define SIMD_REG(name)
Definition: armv8_cpu.cc:66
ArmISA::INTREG_SP0
@ INTREG_SP0
Definition: intregs.hh:118
ArmISA::INTREG_X0
@ INTREG_X0
Definition: intregs.hh:127
BaseArmKvmCPU::getRegList
const RegIndexVector & getRegList() const
Get a list of registers supported by getOneReg() and setOneReg().
Definition: base_cpu.cc:151
ArmV8KvmCPU::dump
void dump() const override
Dump the internal state to the terminal.
Definition: armv8_cpu.cc:149
BaseKvmCPU::deviceEventQueue
EventQueue * deviceEventQueue()
Get a pointer to the event queue owning devices.
Definition: base.hh:427
ArmISA::MISCREG_PRI_S_WR
@ MISCREG_PRI_S_WR
Definition: miscregs.hh:1120
X86ISA::val
Bitfield< 63 > val
Definition: misc.hh:769
ArmV8KvmCPU::deviceRegSet
static const std::set< ArmISA::MiscRegIndex > deviceRegSet
Device registers (needing "effectful" MiscReg writes)
Definition: armv8_cpu.hh:140
KvmFPReg::i
uint32_t i
Definition: armv8_cpu.cc:86
ArmV8KvmCPU::startup
void startup() override
Definition: armv8_cpu.cc:136
KvmFPReg::i
uint64_t i
Definition: armv8_cpu.cc:91
ArmISA::MISCREG_WARN_NOT_FAIL
@ MISCREG_WARN_NOT_FAIL
Definition: miscregs.hh:1095
NUM_QREGS
constexpr static unsigned NUM_QREGS
Definition: armv8_cpu.cc:54
ThreadContext::pcState
virtual TheISA::PCState pcState() const =0
ArmV8KvmCPU::sysRegMap
std::vector< ArmV8KvmCPU::MiscRegInfo > sysRegMap
Cached mapping between system registers in kvm and misc regs in gem5.
Definition: armv8_cpu.hh:145
ArmISA::MISCREG_MON_NS1_WR
@ MISCREG_MON_NS1_WR
Definition: miscregs.hh:1132
ThreadContext::readCCReg
virtual RegVal readCCReg(RegIndex reg_idx) const =0
EventQueue::ScopedMigration
Definition: eventq.hh:665
VecRegClass
@ VecRegClass
Vector Register.
Definition: reg_class.hh:56
ArmISA::NUM_ARCH_INTREGS
@ NUM_ARCH_INTREGS
Definition: intregs.hh:124
ArmISA::MISCREG_CPSR
@ MISCREG_CPSR
Definition: miscregs.hh:57
inform
#define inform(...)
Definition: logging.hh:240
ArmISA::MISCREG_FPCR
@ MISCREG_FPCR
Definition: miscregs.hh:613
ThreadContext::setCCReg
virtual void setCCReg(RegIndex reg_idx, RegVal val)=0
BaseKvmCPU::tc
ThreadContext * tc
ThreadContext object, provides an interface for external objects to modify this thread's state.
Definition: base.hh:148
MipsISA::PCState
GenericISA::DelaySlotPCState< MachInst > PCState
Definition: types.hh:41
ArmISA::MISCREG_PRI_NS_WR
@ MISCREG_PRI_NS_WR
Definition: miscregs.hh:1118
ThreadContext::readMiscReg
virtual RegVal readMiscReg(RegIndex misc_reg)=0
ArmISA::MiscRegInfo
MiscRegInfo
Definition: miscregs.hh:1091
ArmISA::MiscRegIndex
MiscRegIndex
Definition: miscregs.hh:56
ThreadContext::setMiscReg
virtual void setMiscReg(RegIndex misc_reg, RegVal val)=0
ArmISA::decodeAArch64SysReg
MiscRegIndex decodeAArch64SysReg(unsigned op0, unsigned op1, unsigned crn, unsigned crm, unsigned op2)
Definition: miscregs.cc:1442
ArmISA::MISCREG_MPIDR_EL1
@ MISCREG_MPIDR_EL1
Definition: miscregs.hh:534
kvmFPReg
constexpr uint64_t kvmFPReg(const int num)
Definition: armv8_cpu.cc:78
BaseArmKvmCPU
Definition: base_cpu.hh:48
ThreadContext::setMiscRegNoEffect
virtual void setMiscRegNoEffect(RegIndex misc_reg, RegVal val)=0
EXTRACT_FIELD
#define EXTRACT_FIELD(v, name)
Definition: armv8_cpu.cc:57
KvmFPReg::f
float f
Definition: armv8_cpu.cc:87
ArmISA::inAArch64
bool inAArch64(ThreadContext *tc)
Definition: utility.cc:222
ArmISA::s
Bitfield< 4 > s
Definition: miscregs_types.hh:556
ThreadContext::readIntReg
virtual RegVal readIntReg(RegIndex reg_idx) const =0
ArmISA::INTREG_SP1
@ INTREG_SP1
Definition: intregs.hh:119
ArmV8KvmCPU::intRegMap
static const std::vector< ArmV8KvmCPU::IntRegInfo > intRegMap
Mapping between gem5 integer registers and integer registers in kvm.
Definition: armv8_cpu.hh:136
ThreadContext::instAddr
virtual Addr instAddr() const =0
BaseArmKvmCPU::startup
void startup() override
Definition: base_cpu.cc:74
ArmISA::miscRegInfo
bitset< NUM_MISCREG_INFOS > miscRegInfo[NUM_MISCREGS]
Definition: miscregs.cc:3381
CORE_REG
#define CORE_REG(name, size)
Definition: armv8_cpu.cc:60
ArmISA::MISCREG_SPSR_FIQ
@ MISCREG_SPSR_FIQ
Definition: miscregs.hh:59
ArmISA::v
Bitfield< 28 > v
Definition: miscregs_types.hh:51
ArmISA::id
Bitfield< 33 > id
Definition: miscregs_types.hh:247
KvmFPReg
Definition: armv8_cpu.cc:84
ArmISA::MISCREG_SPSR_EL1
@ MISCREG_SPSR_EL1
Definition: miscregs.hh:604

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