gem5  v20.1.0.0
pagetable_walker.cc
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1 /*
2  * Copyright (c) 2012 ARM Limited
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50 
52 
53 #include <memory>
54 
55 #include "arch/riscv/faults.hh"
56 #include "arch/riscv/pagetable.hh"
57 #include "arch/riscv/tlb.hh"
58 #include "base/bitfield.hh"
59 #include "base/trie.hh"
60 #include "cpu/base.hh"
61 #include "cpu/thread_context.hh"
62 #include "debug/PageTableWalker.hh"
63 #include "mem/packet_access.hh"
64 #include "mem/request.hh"
65 
66 namespace RiscvISA {
67 
68 Fault
70  const RequestPtr &_req, BaseTLB::Mode _mode)
71 {
72  // TODO: in timing mode, instead of blocking when there are other
73  // outstanding requests, see if this request can be coalesced with
74  // another one (i.e. either coalesce or start walk)
75  WalkerState * newState = new WalkerState(this, _translation, _req);
76  newState->initState(_tc, _mode, sys->isTimingMode());
77  if (currStates.size()) {
78  assert(newState->isTiming());
79  DPRINTF(PageTableWalker, "Walks in progress: %d\n", currStates.size());
80  currStates.push_back(newState);
81  return NoFault;
82  } else {
83  currStates.push_back(newState);
84  Fault fault = newState->startWalk();
85  if (!newState->isTiming()) {
86  currStates.pop_front();
87  delete newState;
88  }
89  return fault;
90  }
91 }
92 
93 Fault
94 Walker::startFunctional(ThreadContext * _tc, Addr &addr, unsigned &logBytes,
95  BaseTLB::Mode _mode)
96 {
97  funcState.initState(_tc, _mode);
98  return funcState.startFunctional(addr, logBytes);
99 }
100 
101 bool
103 {
104  return walker->recvTimingResp(pkt);
105 }
106 
107 bool
109 {
110  WalkerSenderState * senderState =
111  dynamic_cast<WalkerSenderState *>(pkt->popSenderState());
112  WalkerState * senderWalk = senderState->senderWalk;
113  bool walkComplete = senderWalk->recvPacket(pkt);
114  delete senderState;
115  if (walkComplete) {
117  for (iter = currStates.begin(); iter != currStates.end(); iter++) {
118  WalkerState * walkerState = *(iter);
119  if (walkerState == senderWalk) {
120  iter = currStates.erase(iter);
121  break;
122  }
123  }
124  delete senderWalk;
125  // Since we block requests when another is outstanding, we
126  // need to check if there is a waiting request to be serviced
127  if (currStates.size() && !startWalkWrapperEvent.scheduled())
128  // delay sending any new requests until we are finished
129  // with the responses
131  }
132  return true;
133 }
134 
135 void
137 {
138  walker->recvReqRetry();
139 }
140 
141 void
143 {
145  for (iter = currStates.begin(); iter != currStates.end(); iter++) {
146  WalkerState * walkerState = *(iter);
147  if (walkerState->isRetrying()) {
148  walkerState->retry();
149  }
150  }
151 }
152 
153 bool Walker::sendTiming(WalkerState* sendingState, PacketPtr pkt)
154 {
155  WalkerSenderState* walker_state = new WalkerSenderState(sendingState);
156  pkt->pushSenderState(walker_state);
157  if (port.sendTimingReq(pkt)) {
158  return true;
159  } else {
160  // undo the adding of the sender state and delete it, as we
161  // will do it again the next time we attempt to send it
162  pkt->popSenderState();
163  delete walker_state;
164  return false;
165  }
166 
167 }
168 
169 Port &
170 Walker::getPort(const std::string &if_name, PortID idx)
171 {
172  if (if_name == "port")
173  return port;
174  else
175  return ClockedObject::getPort(if_name, idx);
176 }
177 
178 void
180  BaseTLB::Mode _mode, bool _isTiming)
181 {
182  assert(state == Ready);
183  started = false;
184  tc = _tc;
185  mode = _mode;
186  timing = _isTiming;
187  // fetch these now in case they change during the walk
188  status = tc->readMiscReg(MISCREG_STATUS);
189  pmode = walker->tlb->getMemPriv(tc, mode);
190  satp = tc->readMiscReg(MISCREG_SATP);
191  assert(satp.mode == AddrXlateMode::SV39);
192 }
193 
194 void
196 {
197  unsigned num_squashed = 0;
198  WalkerState *currState = currStates.front();
199  while ((num_squashed < numSquashable) && currState &&
200  currState->translation->squashed()) {
201  currStates.pop_front();
202  num_squashed++;
203 
204  DPRINTF(PageTableWalker, "Squashing table walk for address %#x\n",
205  currState->req->getVaddr());
206 
207  // finish the translation which will delete the translation object
208  currState->translation->finish(
209  std::make_shared<UnimpFault>("Squashed Inst"),
210  currState->req, currState->tc, currState->mode);
211 
212  // delete the current request if there are no inflight packets.
213  // if there is something in flight, delete when the packets are
214  // received and inflight is zero.
215  if (currState->numInflight() == 0) {
216  delete currState;
217  } else {
218  currState->squash();
219  }
220 
221  // check the next translation request, if it exists
222  if (currStates.size())
223  currState = currStates.front();
224  else
225  currState = NULL;
226  }
227  if (currState && !currState->wasStarted())
228  currState->startWalk();
229 }
230 
231 Fault
233 {
234  Fault fault = NoFault;
235  assert(!started);
236  started = true;
237  setupWalk(req->getVaddr());
238  if (timing) {
239  nextState = state;
240  state = Waiting;
241  timingFault = NoFault;
242  sendPackets();
243  } else {
244  do {
245  walker->port.sendAtomic(read);
246  PacketPtr write = NULL;
247  fault = stepWalk(write);
248  assert(fault == NoFault || read == NULL);
249  state = nextState;
250  nextState = Ready;
251  if (write)
252  walker->port.sendAtomic(write);
253  } while (read);
254  state = Ready;
255  nextState = Waiting;
256  }
257  return fault;
258 }
259 
260 Fault
262 {
263  Fault fault = NoFault;
264  assert(!started);
265  started = true;
266  setupWalk(addr);
267 
268  do {
269  walker->port.sendFunctional(read);
270  // On a functional access (page table lookup), writes should
271  // not happen so this pointer is ignored after stepWalk
272  PacketPtr write = NULL;
273  fault = stepWalk(write);
274  assert(fault == NoFault || read == NULL);
275  state = nextState;
276  nextState = Ready;
277  } while (read);
278  logBytes = entry.logBytes;
279  addr = entry.paddr << PageShift;
280 
281  return fault;
282 }
283 
284 Fault
286 {
287  assert(state != Ready && state != Waiting);
288  Fault fault = NoFault;
289  write = NULL;
290  PTESv39 pte = read->getLE<uint64_t>();
291  Addr nextRead = 0;
292  bool doWrite = false;
293  bool doTLBInsert = false;
294  bool doEndWalk = false;
295 
296  DPRINTF(PageTableWalker, "Got level%d PTE: %#x\n", level, pte);
297 
298  // step 2: TODO check PMA and PMP
299 
300  // step 3:
301  if (!pte.v || (!pte.r && pte.w)) {
302  doEndWalk = true;
303  DPRINTF(PageTableWalker, "PTE invalid, raising PF\n");
304  fault = pageFault(pte.v);
305  }
306  else {
307  // step 4:
308  if (pte.r || pte.x) {
309  // step 5: leaf PTE
310  doEndWalk = true;
311  fault = walker->tlb->checkPermissions(status, pmode,
312  entry.vaddr, mode, pte);
313 
314  // step 6
315  if (fault == NoFault) {
316  if (level >= 1 && pte.ppn0 != 0) {
317  DPRINTF(PageTableWalker,
318  "PTE has misaligned PPN, raising PF\n");
319  fault = pageFault(true);
320  }
321  else if (level == 2 && pte.ppn1 != 0) {
322  DPRINTF(PageTableWalker,
323  "PTE has misaligned PPN, raising PF\n");
324  fault = pageFault(true);
325  }
326  }
327 
328  if (fault == NoFault) {
329  // step 7
330  if (!pte.a) {
331  pte.a = 1;
332  doWrite = true;
333  }
334  if (!pte.d && mode == TLB::Write) {
335  pte.d = 1;
336  doWrite = true;
337  }
338  // TODO check if this violates a PMA or PMP
339 
340  // step 8
341  entry.logBytes = PageShift + (level * LEVEL_BITS);
342  entry.paddr = pte.ppn;
343  entry.vaddr &= ~((1 << entry.logBytes) - 1);
344  entry.pte = pte;
345  // put it non-writable into the TLB to detect writes and redo
346  // the page table walk in order to update the dirty flag.
347  if (!pte.d && mode != TLB::Write)
348  entry.pte.w = 0;
349  doTLBInsert = true;
350  }
351  }
352  else {
353  level--;
354  if (level < 0) {
355  DPRINTF(PageTableWalker, "No leaf PTE found, raising PF\n");
356  doEndWalk = true;
357  fault = pageFault(true);
358  }
359  else {
361  Addr idx = (entry.vaddr >> shift) & LEVEL_MASK;
362  nextRead = (pte.ppn << PageShift) + (idx * sizeof(pte));
363  nextState = Translate;
364  }
365  }
366  }
367 
368  PacketPtr oldRead = read;
369  Request::Flags flags = oldRead->req->getFlags();
370 
371  if (doEndWalk) {
372  // If we need to write, adjust the read packet to write the modified
373  // value back to memory.
374  if (!functional && doWrite) {
375  DPRINTF(PageTableWalker, "Writing level%d PTE to %#x: %#x\n",
376  level, oldRead->getAddr(), pte);
377  write = oldRead;
378  write->setLE<uint64_t>(pte);
379  write->cmd = MemCmd::WriteReq;
380  read = NULL;
381  } else {
382  write = NULL;
383  }
384 
385  if (doTLBInsert) {
386  if (!functional)
387  walker->tlb->insert(entry.vaddr, entry);
388  else {
389  DPRINTF(PageTableWalker, "Translated %#x -> %#x\n",
390  entry.vaddr, entry.paddr << PageShift |
391  (entry.vaddr & mask(entry.logBytes)));
392  }
393  }
394  endWalk();
395  }
396  else {
397  //If we didn't return, we're setting up another read.
398  RequestPtr request = std::make_shared<Request>(
399  nextRead, oldRead->getSize(), flags, walker->requestorId);
400  read = new Packet(request, MemCmd::ReadReq);
401  read->allocate();
402 
403  DPRINTF(PageTableWalker,
404  "Loading level%d PTE from %#x\n", level, nextRead);
405  }
406 
407  return fault;
408 }
409 
410 void
412 {
413  nextState = Ready;
414  delete read;
415  read = NULL;
416 }
417 
418 void
420 {
421  vaddr &= (static_cast<Addr>(1) << VADDR_BITS) - 1;
422 
423  Addr shift = PageShift + LEVEL_BITS * 2;
424  Addr idx = (vaddr >> shift) & LEVEL_MASK;
425  Addr topAddr = (satp.ppn << PageShift) + (idx * sizeof(PTESv39));
426  level = 2;
427 
428  DPRINTF(PageTableWalker, "Performing table walk for address %#x\n", vaddr);
429  DPRINTF(PageTableWalker, "Loading level%d PTE from %#x\n", level, topAddr);
430 
431  state = Translate;
432  nextState = Ready;
433  entry.vaddr = vaddr;
434  entry.asid = satp.asid;
435 
437  RequestPtr request = std::make_shared<Request>(
438  topAddr, sizeof(PTESv39), flags, walker->requestorId);
439 
440  read = new Packet(request, MemCmd::ReadReq);
441  read->allocate();
442 }
443 
444 bool
446 {
447  assert(pkt->isResponse());
448  assert(inflight);
449  assert(state == Waiting);
450  inflight--;
451  if (squashed) {
452  // if were were squashed, return true once inflight is zero and
453  // this WalkerState will be freed there.
454  return (inflight == 0);
455  }
456  if (pkt->isRead()) {
457  // should not have a pending read it we also had one outstanding
458  assert(!read);
459 
460  // @todo someone should pay for this
461  pkt->headerDelay = pkt->payloadDelay = 0;
462 
463  state = nextState;
464  nextState = Ready;
465  PacketPtr write = NULL;
466  read = pkt;
467  timingFault = stepWalk(write);
468  state = Waiting;
469  assert(timingFault == NoFault || read == NULL);
470  if (write) {
471  writes.push_back(write);
472  }
473  sendPackets();
474  } else {
475  sendPackets();
476  }
477  if (inflight == 0 && read == NULL && writes.size() == 0) {
478  state = Ready;
479  nextState = Waiting;
480  if (timingFault == NoFault) {
481  /*
482  * Finish the translation. Now that we know the right entry is
483  * in the TLB, this should work with no memory accesses.
484  * There could be new faults unrelated to the table walk like
485  * permissions violations, so we'll need the return value as
486  * well.
487  */
488  Addr vaddr = req->getVaddr();
489  vaddr &= (static_cast<Addr>(1) << VADDR_BITS) - 1;
490  Addr paddr = walker->tlb->translateWithTLB(vaddr, satp.asid, mode);
491  req->setPaddr(paddr);
492  // Let the CPU continue.
493  translation->finish(NoFault, req, tc, mode);
494  } else {
495  // There was a fault during the walk. Let the CPU know.
496  translation->finish(timingFault, req, tc, mode);
497  }
498  return true;
499  }
500 
501  return false;
502 }
503 
504 void
506 {
507  //If we're already waiting for the port to become available, just return.
508  if (retrying)
509  return;
510 
511  //Reads always have priority
512  if (read) {
513  PacketPtr pkt = read;
514  read = NULL;
515  inflight++;
516  if (!walker->sendTiming(this, pkt)) {
517  retrying = true;
518  read = pkt;
519  inflight--;
520  return;
521  }
522  }
523  //Send off as many of the writes as we can.
524  while (writes.size()) {
525  PacketPtr write = writes.back();
526  writes.pop_back();
527  inflight++;
528  if (!walker->sendTiming(this, write)) {
529  retrying = true;
530  writes.push_back(write);
531  inflight--;
532  return;
533  }
534  }
535 }
536 
537 unsigned
539 {
540  return inflight;
541 }
542 
543 bool
545 {
546  return retrying;
547 }
548 
549 bool
551 {
552  return timing;
553 }
554 
555 bool
557 {
558  return started;
559 }
560 
561 void
563 {
564  squashed = true;
565 }
566 
567 void
569 {
570  retrying = false;
571  sendPackets();
572 }
573 
574 Fault
576 {
577  DPRINTF(PageTableWalker, "Raising page fault.\n");
578  return walker->tlb->createPagefault(entry.vaddr, mode);
579 }
580 
581 } /* end namespace RiscvISA */
582 
584 RiscvPagetableWalkerParams::create()
585 {
586  return new RiscvISA::Walker(this);
587 }
ArmISA::status
Bitfield< 5, 0 > status
Definition: miscregs_types.hh:417
BaseTLB::Translation::finish
virtual void finish(const Fault &fault, const RequestPtr &req, ThreadContext *tc, Mode mode)=0
BaseTLB::Translation::squashed
virtual bool squashed() const
This function is used by the page table walker to determine if it should translate the a pending requ...
Definition: tlb.hh:84
Event::scheduled
bool scheduled() const
Determine if the current event is scheduled.
Definition: eventq.hh:460
RiscvISA::Walker::numSquashable
unsigned numSquashable
Definition: pagetable_walker.hh:172
Packet::isResponse
bool isResponse() const
Definition: packet.hh:560
RiscvISA::Walker::WalkerState::req
RequestPtr req
Definition: pagetable_walker.hh:92
RiscvISA::mode
mode
Definition: pagetable.hh:42
RiscvISA::Walker::funcState
WalkerState funcState
Definition: pagetable_walker.hh:147
faults.hh
System::isTimingMode
bool isTimingMode() const
Is the system in timing mode?
Definition: system.hh:269
Packet::getAddr
Addr getAddr() const
Definition: packet.hh:754
RiscvISA::Walker::WalkerState
friend class WalkerState
Definition: pagetable_walker.hh:142
RiscvISA::Walker::WalkerState::setupWalk
void setupWalk(Addr vaddr)
Definition: pagetable_walker.cc:419
Packet::payloadDelay
uint32_t payloadDelay
The extra pipelining delay from seeing the packet until the end of payload is transmitted by the comp...
Definition: packet.hh:412
RiscvISA::Walker::WalkerState::sendPackets
void sendPackets()
Definition: pagetable_walker.cc:505
RiscvISA::PageShift
const Addr PageShift
Definition: isa_traits.hh:52
Flags< FlagsType >
X86ISA::present
Bitfield< 7 > present
Definition: misc.hh:992
RiscvISA::Walker::sys
System * sys
Definition: pagetable_walker.hh:168
Packet::isRead
bool isRead() const
Definition: packet.hh:556
RiscvISA::Walker::WalkerPort::recvTimingResp
bool recvTimingResp(PacketPtr pkt)
Receive a timing response from the peer.
Definition: pagetable_walker.cc:102
BaseTLB::Mode
Mode
Definition: tlb.hh:57
MemCmd::ReadReq
@ ReadReq
Definition: packet.hh:82
RiscvISA::Walker::WalkerState::isRetrying
bool isRetrying()
Definition: pagetable_walker.cc:544
PortID
int16_t PortID
Port index/ID type, and a symbolic name for an invalid port id.
Definition: types.hh:237
RiscvISA::Walker::sendTiming
bool sendTiming(WalkerState *sendingState, PacketPtr pkt)
Definition: pagetable_walker.cc:153
RequestPtr
std::shared_ptr< Request > RequestPtr
Definition: request.hh:82
RiscvISA::Walker::WalkerState::isTiming
bool isTiming()
Definition: pagetable_walker.cc:550
Packet::req
RequestPtr req
A pointer to the original request.
Definition: packet.hh:340
RiscvISA::Walker::WalkerState::endWalk
void endWalk()
Definition: pagetable_walker.cc:411
Packet::getSize
unsigned getSize() const
Definition: packet.hh:764
RiscvISA::Walker::recvTimingResp
bool recvTimingResp(PacketPtr pkt)
Definition: pagetable_walker.cc:108
RiscvISA::Walker::WalkerSenderState::senderWalk
WalkerState * senderWalk
Definition: pagetable_walker.hh:151
RiscvISA::MISCREG_STATUS
@ MISCREG_STATUS
Definition: registers.hh:135
request.hh
Packet::headerDelay
uint32_t headerDelay
The extra delay from seeing the packet until the header is transmitted.
Definition: packet.hh:394
RiscvISA
Definition: fs_workload.cc:36
RiscvISA::VADDR_BITS
const Addr VADDR_BITS
Definition: pagetable.hh:55
RiscvISA::Walker::WalkerPort::walker
Walker * walker
Definition: pagetable_walker.hh:69
MemCmd::WriteReq
@ WriteReq
Definition: packet.hh:85
RiscvISA::Walker::start
Fault start(ThreadContext *_tc, BaseTLB::Translation *translation, const RequestPtr &req, BaseTLB::Mode mode)
Definition: pagetable_walker.cc:69
RiscvISA::vaddr
vaddr
Definition: pra_constants.hh:275
Request::PHYSICAL
@ PHYSICAL
The virtual address is also the physical address.
Definition: request.hh:106
EventManager::schedule
void schedule(Event &event, Tick when)
Definition: eventq.hh:1005
RiscvISA::Walker::WalkerState::initState
void initState(ThreadContext *_tc, BaseTLB::Mode _mode, bool _isTiming=false)
Definition: pagetable_walker.cc:179
ThreadContext
ThreadContext is the external interface to all thread state for anything outside of the CPU.
Definition: thread_context.hh:88
bitfield.hh
RequestPort::sendTimingReq
bool sendTimingReq(PacketPtr pkt)
Attempt to send a timing request to the responder port by calling its corresponding receive function.
Definition: port.hh:492
tlb.hh
SimObject::getPort
virtual Port & getPort(const std::string &if_name, PortID idx=InvalidPortID)
Get a port with a given name and index.
Definition: sim_object.cc:123
RiscvISA::Walker::WalkerState
Definition: pagetable_walker.hh:79
ArmISA::shift
Bitfield< 6, 5 > shift
Definition: types.hh:126
DPRINTF
#define DPRINTF(x,...)
Definition: trace.hh:234
Fault
std::shared_ptr< FaultBase > Fault
Definition: types.hh:240
Port
Ports are used to interface objects to each other.
Definition: port.hh:56
RiscvISA::Walker::WalkerState::startWalk
Fault startWalk()
Definition: pagetable_walker.cc:232
Clocked::clockEdge
Tick clockEdge(Cycles cycles=Cycles(0)) const
Determine the tick when a cycle begins, by default the current one, but the argument also enables the...
Definition: clocked_object.hh:174
RiscvISA::Walker
Definition: pagetable_walker.hh:57
RiscvISA::Walker::WalkerState::wasStarted
bool wasStarted()
Definition: pagetable_walker.cc:556
RiscvISA::LEVEL_MASK
const Addr LEVEL_MASK
Definition: pagetable.hh:57
BaseTLB::Translation
Definition: tlb.hh:59
RiscvISA::Walker::WalkerState::pageFault
Fault pageFault(bool present)
Definition: pagetable_walker.cc:575
RiscvISA::Walker::WalkerState::retry
void retry()
Definition: pagetable_walker.cc:568
NoFault
constexpr decltype(nullptr) NoFault
Definition: types.hh:245
ProbePoints::Packet
ProbePointArg< PacketInfo > Packet
Packet probe point.
Definition: mem.hh:103
Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:142
RiscvISA::Walker::WalkerState::stepWalk
Fault stepWalk(PacketPtr &write)
Definition: pagetable_walker.cc:285
packet_access.hh
RiscvISA::Walker::WalkerState::mode
BaseTLB::Mode mode
Definition: pagetable_walker.hh:102
RiscvISA::Walker::WalkerState::recvPacket
bool recvPacket(PacketPtr pkt)
Definition: pagetable_walker.cc:445
BaseTLB::Write
@ Write
Definition: tlb.hh:57
Packet::cmd
MemCmd cmd
The command field of the packet.
Definition: packet.hh:335
RiscvISA::Walker::startWalkWrapper
void startWalkWrapper()
Definition: pagetable_walker.cc:195
RiscvISA::Walker::WalkerState::numInflight
unsigned numInflight() const
Definition: pagetable_walker.cc:538
RiscvISA::mask
mask
Definition: pra_constants.hh:70
X86ISA::level
Bitfield< 20 > level
Definition: intmessage.hh:47
RiscvISA::Walker::WalkerSenderState
Definition: pagetable_walker.hh:149
RiscvISA::LEVEL_BITS
const Addr LEVEL_BITS
Definition: pagetable.hh:56
RiscvISA::Walker::WalkerState::translation
TLB::Translation * translation
Definition: pagetable_walker.hh:101
Packet::getLE
T getLE() const
Get the data in the packet byte swapped from little endian to host endian.
Definition: packet_access.hh:75
Packet::pushSenderState
void pushSenderState(SenderState *sender_state)
Push a new sender state to the packet and make the current sender state the predecessor of the new on...
Definition: packet.cc:332
RiscvISA::Walker::getPort
Port & getPort(const std::string &if_name, PortID idx=InvalidPortID) override
Get a port with a given name and index.
Definition: pagetable_walker.cc:170
RiscvISA::Walker::recvReqRetry
void recvReqRetry()
Definition: pagetable_walker.cc:142
base.hh
RiscvISA::Walker::port
WalkerPort port
Definition: pagetable_walker.hh:76
Packet
A Packet is used to encapsulate a transfer between two objects in the memory system (e....
Definition: packet.hh:257
Packet::popSenderState
SenderState * popSenderState()
Pop the top of the state stack and return a pointer to it.
Definition: packet.cc:340
addr
ip6_addr_t addr
Definition: inet.hh:423
RiscvISA::Walker::WalkerState::squash
void squash()
Definition: pagetable_walker.cc:562
Packet::setLE
void setLE(T v)
Set the value in the data pointer to v as little endian.
Definition: packet_access.hh:105
RiscvISA::MISCREG_SATP
@ MISCREG_SATP
Definition: registers.hh:244
RiscvISA::Walker::startWalkWrapperEvent
EventFunctionWrapper startWalkWrapperEvent
Event used to call startWalkWrapper.
Definition: pagetable_walker.hh:180
std::list
STL list class.
Definition: stl.hh:51
RiscvISA::Walker::WalkerPort::recvReqRetry
void recvReqRetry()
Called by the peer if sendTimingReq was called on this peer (causing recvTimingReq to be called on th...
Definition: pagetable_walker.cc:136
RiscvISA::Walker::startFunctional
Fault startFunctional(ThreadContext *_tc, Addr &addr, unsigned &logBytes, BaseTLB::Mode mode)
Definition: pagetable_walker.cc:94
RiscvISA::Walker::WalkerState::tc
ThreadContext * tc
Definition: pagetable_walker.hh:91
pagetable.hh
thread_context.hh
trie.hh
RiscvISA::Walker::currStates
std::list< WalkerState * > currStates
Definition: pagetable_walker.hh:145
pagetable_walker.hh
RiscvISA::Walker::WalkerState::startFunctional
Fault startFunctional(Addr &addr, unsigned &logBytes)
Definition: pagetable_walker.cc:261

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