gem5  v22.1.0.0
InputUnit.cc
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30 
31 
33 
34 #include "debug/RubyNetwork.hh"
37 
38 namespace gem5
39 {
40 
41 namespace ruby
42 {
43 
44 namespace garnet
45 {
46 
47 InputUnit::InputUnit(int id, PortDirection direction, Router *router)
48  : Consumer(router), m_router(router), m_id(id), m_direction(direction),
49  m_vc_per_vnet(m_router->get_vc_per_vnet())
50 {
51  const int m_num_vcs = m_router->get_num_vcs();
52  m_num_buffer_reads.resize(m_num_vcs/m_vc_per_vnet);
53  m_num_buffer_writes.resize(m_num_vcs/m_vc_per_vnet);
54  for (int i = 0; i < m_num_buffer_reads.size(); i++) {
55  m_num_buffer_reads[i] = 0;
57  }
58 
59  // Instantiating the virtual channels
60  virtualChannels.reserve(m_num_vcs);
61  for (int i=0; i < m_num_vcs; i++) {
62  virtualChannels.emplace_back();
63  }
64 }
65 
66 /*
67  * The InputUnit wakeup function reads the input flit from its input link.
68  * Each flit arrives with an input VC.
69  * For HEAD/HEAD_TAIL flits, performs route computation,
70  * and updates route in the input VC.
71  * The flit is buffered for (m_latency - 1) cycles in the input VC
72  * and marked as valid for SwitchAllocation starting that cycle.
73  *
74  */
75 
76 void
78 {
79  flit *t_flit;
80  if (m_in_link->isReady(curTick())) {
81 
82  t_flit = m_in_link->consumeLink();
83  DPRINTF(RubyNetwork, "Router[%d] Consuming:%s Width: %d Flit:%s\n",
85  m_router->getBitWidth(), *t_flit);
86  assert(t_flit->m_width == m_router->getBitWidth());
87  int vc = t_flit->get_vc();
88  t_flit->increment_hops(); // for stats
89 
90  if ((t_flit->get_type() == HEAD_) ||
91  (t_flit->get_type() == HEAD_TAIL_)) {
92 
93  assert(virtualChannels[vc].get_state() == IDLE_);
94  set_vc_active(vc, curTick());
95 
96  // Route computation for this vc
97  int outport = m_router->route_compute(t_flit->get_route(),
98  m_id, m_direction);
99 
100  // Update output port in VC
101  // All flits in this packet will use this output port
102  // The output port field in the flit is updated after it wins SA
103  grant_outport(vc, outport);
104 
105  } else {
106  assert(virtualChannels[vc].get_state() == ACTIVE_);
107  }
108 
109 
110  // Buffer the flit
111  virtualChannels[vc].insertFlit(t_flit);
112 
113  int vnet = vc/m_vc_per_vnet;
114  // number of writes same as reads
115  // any flit that is written will be read only once
116  m_num_buffer_writes[vnet]++;
117  m_num_buffer_reads[vnet]++;
118 
119  Cycles pipe_stages = m_router->get_pipe_stages();
120  if (pipe_stages == 1) {
121  // 1-cycle router
122  // Flit goes for SA directly
123  t_flit->advance_stage(SA_, curTick());
124  } else {
125  assert(pipe_stages > 1);
126  // Router delay is modeled by making flit wait in buffer for
127  // (pipe_stages cycles - 1) cycles before going for SA
128 
129  Cycles wait_time = pipe_stages - Cycles(1);
130  t_flit->advance_stage(SA_, m_router->clockEdge(wait_time));
131 
132  // Wakeup the router in that cycle to perform SA
133  m_router->schedule_wakeup(Cycles(wait_time));
134  }
135 
136  if (m_in_link->isReady(curTick())) {
138  }
139  }
140 }
141 
142 // Send a credit back to upstream router for this VC.
143 // Called by SwitchAllocator when the flit in this VC wins the Switch.
144 void
145 InputUnit::increment_credit(int in_vc, bool free_signal, Tick curTime)
146 {
147  DPRINTF(RubyNetwork, "Router[%d]: Sending a credit vc:%d free:%d to %s\n",
148  m_router->get_id(), in_vc, free_signal, m_credit_link->name());
149  Credit *t_credit = new Credit(in_vc, free_signal, curTime);
150  creditQueue.insert(t_credit);
152 }
153 
154 bool
156 {
157  bool read = false;
158  for (auto& virtual_channel : virtualChannels) {
159  if (virtual_channel.functionalRead(pkt, mask))
160  read = true;
161  }
162 
163  return read;
164 }
165 
166 uint32_t
168 {
169  uint32_t num_functional_writes = 0;
170  for (auto& virtual_channel : virtualChannels) {
171  num_functional_writes += virtual_channel.functionalWrite(pkt);
172  }
173 
174  return num_functional_writes;
175 }
176 
177 void
179 {
180  for (int j = 0; j < m_num_buffer_reads.size(); j++) {
181  m_num_buffer_reads[j] = 0;
182  m_num_buffer_writes[j] = 0;
183  }
184 }
185 
186 } // namespace garnet
187 } // namespace ruby
188 } // namespace gem5
#define DPRINTF(x,...)
Definition: trace.hh:186
Tick clockEdge(Cycles cycles=Cycles(0)) const
Determine the tick when a cycle begins, by default the current one, but the argument also enables the...
Cycles is a wrapper class for representing cycle counts, i.e.
Definition: types.hh:79
virtual std::string name() const
Definition: named.hh:47
A Packet is used to encapsulate a transfer between two objects in the memory system (e....
Definition: packet.hh:294
void scheduleEventAbsolute(Tick timeAbs)
Definition: Consumer.cc:63
std::vector< double > m_num_buffer_reads
Definition: InputUnit.hh:174
void set_vc_active(int vc, Tick curTime)
Definition: InputUnit.hh:73
std::vector< VirtualChannel > virtualChannels
Definition: InputUnit.hh:170
void grant_outport(int vc, int outport)
Definition: InputUnit.hh:79
InputUnit(int id, PortDirection direction, Router *router)
Definition: InputUnit.cc:47
void increment_credit(int in_vc, bool free_signal, Tick curTime)
Definition: InputUnit.cc:145
bool functionalRead(Packet *pkt, WriteMask &mask)
Definition: InputUnit.cc:155
uint32_t functionalWrite(Packet *pkt)
Definition: InputUnit.cc:167
std::vector< double > m_num_buffer_writes
Definition: InputUnit.hh:173
int route_compute(RouteInfo route, int inport, PortDirection direction)
Definition: Router.cc:162
void schedule_wakeup(Cycles time)
Definition: Router.cc:174
uint32_t get_num_vcs()
Definition: Router.hh:86
RouteInfo get_route()
Definition: flit.hh:68
flit_type get_type()
Definition: flit.hh:70
void advance_stage(flit_stage t_stage, Tick newTime)
Definition: flit.hh:93
constexpr uint64_t mask(unsigned nbits)
Generate a 64-bit mask of 'nbits' 1s, right justified.
Definition: bitfield.hh:63
Bitfield< 7 > i
Definition: misc_types.hh:67
Bitfield< 33 > id
Definition: misc_types.hh:257
Bitfield< 24 > j
Definition: misc_types.hh:57
std::string PortDirection
Definition: TypeDefines.hh:44
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Tick curTick()
The universal simulation clock.
Definition: cur_tick.hh:46
uint64_t Tick
Tick count type.
Definition: types.hh:58

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