gem5 v24.0.0.0
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OutputUnit.cc
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1/*
2 * Copyright (c) 2020 Inria
3 * Copyright (c) 2016 Georgia Institute of Technology
4 * Copyright (c) 2008 Princeton University
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions are
9 * met: redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer;
11 * redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution;
14 * neither the name of the copyright holders nor the names of its
15 * contributors may be used to endorse or promote products derived from
16 * this software without specific prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
19 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
20 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
21 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
22 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
23 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
24 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
25 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
26 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
28 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
29 */
30
31
33
34#include "debug/RubyNetwork.hh"
39
40namespace gem5
41{
42
43namespace ruby
44{
45
46namespace garnet
47{
48
49OutputUnit::OutputUnit(int id, PortDirection direction, Router *router,
50 uint32_t consumerVcs)
51 : Consumer(router), m_router(router), m_id(id), m_direction(direction),
52 m_vc_per_vnet(consumerVcs)
53{
54 const int m_num_vcs = consumerVcs * m_router->get_num_vnets();
55 outVcState.reserve(m_num_vcs);
56 for (int i = 0; i < m_num_vcs; i++) {
57 outVcState.emplace_back(i, m_router->get_net_ptr(), consumerVcs);
58 }
59}
60
61void
63{
64 DPRINTF(RubyNetwork, "Router %d OutputUnit %s decrementing credit:%d for "
65 "outvc %d at time: %lld for %s\n", m_router->get_id(),
68 out_vc, m_router->curCycle(), m_credit_link->name());
69
70 outVcState[out_vc].decrement_credit();
71}
72
73void
75{
76 DPRINTF(RubyNetwork, "Router %d OutputUnit %s incrementing credit:%d for "
77 "outvc %d at time: %lld from:%s\n", m_router->get_id(),
80 out_vc, m_router->curCycle(), m_credit_link->name());
81
82 outVcState[out_vc].increment_credit();
83}
84
85// Check if the output VC (i.e., input VC at next router)
86// has free credits (i..e, buffer slots).
87// This is tracked by OutVcState
88bool
90{
91 assert(outVcState[out_vc].isInState(ACTIVE_, curTick()));
92 return outVcState[out_vc].has_credit();
93}
94
95
96// Check if the output port (i.e., input port at next router) has free VCs.
97bool
99{
100 int vc_base = vnet*m_vc_per_vnet;
101 for (int vc = vc_base; vc < vc_base + m_vc_per_vnet; vc++) {
102 if (is_vc_idle(vc, curTick()))
103 return true;
104 }
105
106 return false;
107}
108
109// Assign a free output VC to the winner of Switch Allocation
110int
112{
113 int vc_base = vnet*m_vc_per_vnet;
114 for (int vc = vc_base; vc < vc_base + m_vc_per_vnet; vc++) {
115 if (is_vc_idle(vc, curTick())) {
116 outVcState[vc].setState(ACTIVE_, curTick());
117 return vc;
118 }
119 }
120
121 return -1;
122}
123
124/*
125 * The wakeup function of the OutputUnit reads the credit signal from the
126 * downstream router for the output VC (i.e., input VC at downstream router).
127 * It increments the credit count in the appropriate output VC state.
128 * If the credit carries is_free_signal as true,
129 * the output VC is marked IDLE.
130 */
131
132void
134{
135 if (m_credit_link->isReady(curTick())) {
136 Credit *t_credit = (Credit*) m_credit_link->consumeLink();
137 increment_credit(t_credit->get_vc());
138
139 if (t_credit->is_free_signal())
140 set_vc_state(IDLE_, t_credit->get_vc(), curTick());
141
142 delete t_credit;
143
144 if (m_credit_link->isReady(curTick())) {
146 }
147 }
148}
149
152{
153 return &outBuffer;
154}
155
156void
161
162void
164{
165 m_credit_link = credit_link;
166}
167
168void
174
175bool
180
181uint32_t
186
187} // namespace garnet
188} // namespace ruby
189} // namespace gem5
#define DPRINTF(x,...)
Definition trace.hh:210
Cycles curCycle() const
Determine the current cycle, corresponding to a tick aligned to a clock edge.
Tick clockEdge(Cycles cycles=Cycles(0)) const
Determine the tick when a cycle begins, by default the current one, but the argument also enables the...
Cycles is a wrapper class for representing cycle counts, i.e.
Definition types.hh:79
virtual std::string name() const
Definition named.hh:47
A Packet is used to encapsulate a transfer between two objects in the memory system (e....
Definition packet.hh:295
void scheduleEventAbsolute(Tick timeAbs)
Definition Consumer.cc:63
void scheduleEvent(Cycles timeDelta)
Definition Consumer.cc:56
void increment_credit(int out_vc)
Definition OutputUnit.cc:74
void set_out_link(NetworkLink *link)
void decrement_credit(int out_vc)
Definition OutputUnit.cc:62
uint32_t functionalWrite(Packet *pkt)
void set_vc_state(VC_state_type state, int vc, Tick curTime)
Definition OutputUnit.hh:88
bool functionalRead(Packet *pkt, WriteMask &mask)
std::vector< OutVcState > outVcState
void insert_flit(flit *t_flit)
bool is_vc_idle(int vc, Tick curTime)
Definition OutputUnit.hh:94
void set_credit_link(CreditLink *credit_link)
OutputUnit(int id, PortDirection direction, Router *router, uint32_t consumerVcs)
Definition OutputUnit.cc:49
GarnetNetwork * get_net_ptr()
Definition Router.hh:98
std::string getPortDirectionName(PortDirection direction)
Definition Router.cc:181
bool functionalRead(Packet *pkt, WriteMask &mask)
Definition flitBuffer.cc:89
uint32_t functionalWrite(Packet *pkt)
Bitfield< 3, 0 > mask
Definition pcstate.hh:63
Bitfield< 7 > i
Definition misc_types.hh:67
Bitfield< 33 > id
std::string PortDirection
Copyright (c) 2024 - Pranith Kumar Copyright (c) 2020 Inria All rights reserved.
Definition binary32.hh:36
Tick curTick()
The universal simulation clock.
Definition cur_tick.hh:46

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