tlb.hh File Reference

#include <fstream>
#include <list>
#include <queue>
#include <string>
#include <vector>
#include "arch/generic/tlb.hh"
#include "arch/x86/pagetable.hh"
#include "arch/x86/pagetable_walker.hh"
#include "arch/x86/regs/segment.hh"
#include "base/callback.hh"
#include "base/logging.hh"
#include "base/statistics.hh"
#include "base/stats/group.hh"
#include "gpu-compute/compute_unit.hh"
#include "mem/port.hh"
#include "mem/request.hh"
#include "params/X86GPUTLB.hh"
#include "sim/clocked_object.hh"
#include "sim/sim_object.hh"

Go to the source code of this file.

Classes
class	gem5::X86ISA::GpuTLB
class	gem5::X86ISA::GpuTLB::Translation
class	gem5::X86ISA::GpuTLB::CpuSidePort
class	gem5::X86ISA::GpuTLB::MemSidePort
	MemSidePort is the TLB Port closer to the memory side If this is a last level TLB then this port will not be connected. More...
class	gem5::X86ISA::GpuTLB::TLBEvent
struct	gem5::X86ISA::GpuTLB::AccessInfo
	This hash map will use the virtual page address as a key and will keep track of total number of accesses per page. More...
struct	gem5::X86ISA::GpuTLB::GpuTLBStats

Namespaces
namespace	gem5
	Copyright (c) 2024 - Pranith Kumar Copyright (c) 2020 Inria All rights reserved.
namespace	gem5::X86ISA
	This is exposed globally, independent of the ISA.