gem5  v21.2.1.1
tlb.hh
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31 
32 #ifndef __GPU_TLB_HH__
33 #define __GPU_TLB_HH__
34 
35 #include <fstream>
36 #include <list>
37 #include <queue>
38 #include <string>
39 #include <vector>
40 
41 #include "arch/generic/tlb.hh"
42 #include "arch/x86/pagetable.hh"
44 #include "arch/x86/regs/segment.hh"
45 #include "base/callback.hh"
46 #include "base/logging.hh"
47 #include "base/statistics.hh"
48 #include "base/stats/group.hh"
50 #include "mem/port.hh"
51 #include "mem/request.hh"
52 #include "params/X86GPUTLB.hh"
53 #include "sim/clocked_object.hh"
54 #include "sim/sim_object.hh"
55 
56 namespace gem5
57 {
58 
59 class BaseTLB;
60 class Packet;
61 class ThreadContext;
62 
63 namespace X86ISA
64 {
65  class GpuTLB : public ClockedObject
66  {
67  protected:
68  friend class Walker;
69 
71 
72  uint32_t configAddress;
73 
74  public:
75  typedef X86GPUTLBParams Params;
76  GpuTLB(const Params &p);
77  ~GpuTLB();
78 
79  typedef enum BaseMMU::Mode Mode;
80 
82  {
83  public:
84  virtual ~Translation() { }
85 
90  virtual void markDelayed() = 0;
91 
97  virtual void finish(Fault fault, const RequestPtr &req,
98  ThreadContext *tc, Mode mode) = 0;
99  };
100 
101  void dumpAll();
102  TlbEntry *lookup(Addr va, bool update_lru=true);
103  void setConfigAddress(uint32_t addr);
104 
105  protected:
106  EntryList::iterator lookupIt(Addr va, bool update_lru=true);
108 
109  public:
110  Walker *getWalker();
111  void invalidateAll();
112  void invalidateNonGlobal();
113  void demapPage(Addr va, uint64_t asn);
114 
115  protected:
116  int size;
117  int assoc;
118  int numSets;
119 
123  bool FA;
125 
131 
136 
142 
144 
145  /*
146  * It's a per-set list. As long as we have not reached
147  * the full capacity of the given set, grab an entry from
148  * the freeList.
149  */
151 
160 
161  Fault translateInt(bool read, const RequestPtr &req,
162  ThreadContext *tc);
163 
164  Fault translate(const RequestPtr &req, ThreadContext *tc,
165  Translation *translation, Mode mode, bool &delayedResponse,
166  bool timing, int &latency);
167 
168  public:
169  // latencies for a TLB hit, miss and page fault
173 
174  void updatePageFootprint(Addr virt_page_addr);
175  void printAccessPattern();
176 
177 
179  Mode mode, int &latency);
180 
181  void translateTiming(const RequestPtr &req, ThreadContext *tc,
182  Translation *translation, Mode mode,
183  int &latency);
184 
187 
188  TlbEntry *insert(Addr vpn, TlbEntry &entry);
189 
190  // Checkpointing
191  virtual void serialize(CheckpointOut& cp) const override;
192  virtual void unserialize(CheckpointIn& cp) override;
193  void issueTranslation();
195  bool tlbLookup(const RequestPtr &req,
196  ThreadContext *tc, bool update_stats);
197 
199  PacketPtr pkt);
200 
202 
204  TlbEntry *tlb_entry, Mode mode);
205 
206  void updatePhysAddresses(Addr virt_page_addr, TlbEntry *tlb_entry,
207  Addr phys_page_addr);
208 
209  void issueTLBLookup(PacketPtr pkt);
210 
211  // CpuSidePort is the TLB Port closer to the CPU/CU side
212  class CpuSidePort : public ResponsePort
213  {
214  public:
215  CpuSidePort(const std::string &_name, GpuTLB * gpu_TLB,
216  PortID _index)
217  : ResponsePort(_name, gpu_TLB), tlb(gpu_TLB), index(_index) { }
218 
219  protected:
221  int index;
222 
223  virtual bool recvTimingReq(PacketPtr pkt);
224  virtual Tick recvAtomic(PacketPtr pkt) { return 0; }
225  virtual void recvFunctional(PacketPtr pkt);
226  virtual void recvRangeChange() { }
227  virtual void recvReqRetry();
228  virtual void recvRespRetry() { panic("recvRespRetry called"); }
229  virtual AddrRangeList getAddrRanges() const;
230  };
231 
239  class MemSidePort : public RequestPort
240  {
241  public:
242  MemSidePort(const std::string &_name, GpuTLB * gpu_TLB,
243  PortID _index)
244  : RequestPort(_name, gpu_TLB), tlb(gpu_TLB), index(_index) { }
245 
247 
248  protected:
250  int index;
251 
252  virtual bool recvTimingResp(PacketPtr pkt);
253  virtual Tick recvAtomic(PacketPtr pkt) { return 0; }
254  virtual void recvFunctional(PacketPtr pkt) { }
255  virtual void recvRangeChange() { }
256  virtual void recvReqRetry();
257  };
258 
259  // TLB ports on the cpu Side
261  // TLB ports on the memory side
263 
264  Port &getPort(const std::string &if_name,
265  PortID idx=InvalidPortID) override;
266 
284  {
285  // TLB mode, read or write
287  // Thread context associated with this req
289 
290  /*
291  * TLB entry to be populated and passed back and filled in
292  * previous TLBs. Equivalent to the data cache concept of
293  * "data return."
294  */
296  // Is this a TLB prefetch request?
298  // When was the req for this translation issued
299  uint64_t issueTime;
300  // Remember where this came from
302 
303  // keep track of #uncoalesced reqs per packet per TLB level;
304  // reqCnt per level >= reqCnt higher level
306  // TLB level this packet hit in; 0 if it hit in the page table
307  int hitLevel;
309 
311  bool is_prefetch=false,
312  Packet::SenderState *_saved=nullptr)
313  : tlbMode(tlb_mode), tc(_tc), tlbEntry(nullptr),
314  isPrefetch(is_prefetch), issueTime(0),
315  hitLevel(0),saved(_saved) { }
316  };
317 
318  // maximum number of permitted coalesced requests per cycle
320 
321  // Current number of outstandings coalesced requests.
322  // Should be <= maxCoalescedReqs
324 
332  void translationReturn(Addr virtPageAddr, tlbOutcome outcome,
333  PacketPtr pkt);
334 
335  class TLBEvent : public Event
336  {
337  private:
345 
346  public:
347  TLBEvent(GpuTLB *_tlb, Addr _addr, tlbOutcome outcome,
348  PacketPtr _pkt);
349 
350  void process();
351  const char *description() const;
352 
353  // updateOutcome updates the tlbOutcome of a TLBEvent
354  void updateOutcome(tlbOutcome _outcome);
356  };
357 
358  std::unordered_map<Addr, TLBEvent*> translationReturnEvent;
359 
360  // this FIFO queue keeps track of the virt. page addresses
361  // that are pending cleanup
362  std::queue<Addr> cleanupQueue;
363 
364  // the cleanupEvent is scheduled after a TLBEvent triggers in order to
365  // free memory and do the required clean-up
366  void cleanup();
367 
369 
375  struct AccessInfo
376  {
377  unsigned int lastTimeAccessed; // last access to this page
378  unsigned int accessesPerPage;
379  // need to divide it by accessesPerPage at the end
380  unsigned int totalReuseDistance;
381 
391  unsigned int sumDistance;
392  unsigned int meanDistance;
393  };
394 
395  typedef std::unordered_map<Addr, AccessInfo> AccessPatternTable;
397 
398  // Called at the end of simulation to dump page access stats.
399  void exitCallback();
400 
402 
403  protected:
405  {
407 
408  // local_stats are as seen from the TLB
409  // without taking into account coalescing
414 
415  // global_stats are as seen from the
416  // CU's perspective taking into account
417  // all coalesced requests.
422 
423  // from the CU perspective (global)
425  // from the CU perspective (global)
428  // from the perspective of this TLB
430  // from the perspective of this TLB
432  // I take the avg. per page and then
433  // the avg. over all pages.
435  } stats;
436  };
437 }
438 
440 
441 } // namespace gem5
442 
443 #endif // __GPU_TLB_HH__
gem5::statistics::Scalar
This is a simple scalar statistic, like a counter.
Definition: statistics.hh:1930
gem5::X86ISA::GpuTLB::issueTranslation
void issueTranslation()
gem5::PortID
int16_t PortID
Port index/ID type, and a symbolic name for an invalid port id.
Definition: types.hh:252
pagetable.hh
gem5::X86ISA::GpuTLB::configAddress
uint32_t configAddress
Definition: tlb.hh:72
gem5::X86ISA::GpuTLB::GpuTLBStats::numUniquePages
statistics::Scalar numUniquePages
Definition: tlb.hh:427
gem5::X86ISA::GpuTLB::printAccessPattern
void printAccessPattern()
gem5::X86ISA::GpuTLB::updatePhysAddresses
void updatePhysAddresses(Addr virt_page_addr, TlbEntry *tlb_entry, Addr phys_page_addr)
gem5::X86ISA::GpuTLB::MemSidePort::index
int index
Definition: tlb.hh:250
gem5::X86ISA::GpuTLB::GpuTLBStats::GpuTLBStats
GpuTLBStats(statistics::Group *parent)
Definition: tlb.cc:1433
gem5::X86ISA::GpuTLB::GpuTLBStats::accessCycles
statistics::Scalar accessCycles
Definition: tlb.hh:424
gem5::X86ISA::GpuTLB::CpuSidePort::CpuSidePort
CpuSidePort(const std::string &_name, GpuTLB *gpu_TLB, PortID _index)
Definition: tlb.hh:215
gem5::X86ISA::GpuTLB::CpuSidePort::recvFunctional
virtual void recvFunctional(PacketPtr pkt)
Receive a functional request packet from the peer.
Definition: tlb.cc:1121
gem5::X86ISA::GpuTLB::translationReturn
void translationReturn(Addr virtPageAddr, tlbOutcome outcome, PacketPtr pkt)
A TLBEvent is scheduled after the TLB lookup and helps us take the appropriate actions: (e....
Definition: tlb.cc:882
gem5::X86ISA::GpuTLB::stats
gem5::X86ISA::GpuTLB::GpuTLBStats stats
gem5::X86ISA::GpuTLB::memSidePort
std::vector< MemSidePort * > memSidePort
Definition: tlb.hh:262
gem5::X86ISA::GpuTLB::GpuTLBStats::avgReuseDistance
statistics::Scalar avgReuseDistance
Definition: tlb.hh:434
gem5::X86ISA::GpuTLB::size
int size
Definition: tlb.hh:116
gem5::X86ISA::GpuTLB::AccessInfo::localTLBAccesses
std::vector< unsigned int > localTLBAccesses
The field below will help us compute the access distance, that is the number of (coalesced) TLB acces...
Definition: tlb.hh:390
gem5::X86ISA::GpuTLB::TranslationState::tc
ThreadContext * tc
Definition: tlb.hh:288
group.hh
gem5::X86ISA::GpuTLB::TLBEvent::virtPageAddr
Addr virtPageAddr
Definition: tlb.hh:339
gem5::X86ISA::GpuTLB::GpuTLBStats::localNumTLBAccesses
statistics::Scalar localNumTLBAccesses
Definition: tlb.hh:410
gem5::X86ISA::GpuTLB::numSets
int numSets
Definition: tlb.hh:118
gem5::BaseMMU::Mode
Mode
Definition: mmu.hh:56
gem5::X86ISA::GpuTLB::exitCallback
void exitCallback()
Definition: tlb.cc:1341
gem5::X86ISA::GpuTLB::cleanup
void cleanup()
Definition: tlb.cc:1282
gem5::CheckpointIn
Definition: serialize.hh:68
gem5::X86ISA::GpuTLB::outstandingReqs
int outstandingReqs
Definition: tlb.hh:323
compute_unit.hh
gem5::X86ISA::GpuTLB::AccessInfo::totalReuseDistance
unsigned int totalReuseDistance
Definition: tlb.hh:380
gem5::X86ISA::GpuTLB::TranslationState::saved
Packet::SenderState * saved
Definition: tlb.hh:308
tlb.hh
gem5::X86ISA::GpuTLB::TLBEvent::outcome
tlbOutcome outcome
outcome can be TLB_HIT, TLB_MISS, or PAGE_WALK
Definition: tlb.hh:343
gem5::X86ISA::GpuTLB::walker
Walker * walker
Definition: tlb.hh:107
gem5::X86ISA::GpuTLB::TLB_MISS
@ TLB_MISS
Definition: tlb.hh:194
gem5::X86ISA::GpuTLB::Mode
enum BaseMMU::Mode Mode
Definition: tlb.hh:79
gem5::X86ISA::GpuTLB::MemSidePort::tlb
GpuTLB * tlb
Definition: tlb.hh:249
gem5::X86ISA::GpuTLB::GpuTLBStats::localTLBMissRate
statistics::Formula localTLBMissRate
Definition: tlb.hh:413
pagetable_walker.hh
gem5::X86ISA::GpuTLB::CpuSidePort::tlb
GpuTLB * tlb
Definition: tlb.hh:220
gem5::X86ISA::GpuTLB::TLBEvent::pkt
PacketPtr pkt
Definition: tlb.hh:344
gem5::X86ISA::GpuTLB::TranslationState::tlbMode
Mode tlbMode
Definition: tlb.hh:286
gem5::X86ISA::GpuTLB::~GpuTLB
~GpuTLB()
Definition: tlb.cc:129
gem5::X86ISA::GpuTLB::getWalker
Walker * getWalker()
Definition: tlb.cc:646
gem5::X86ISA::GpuTLB::GpuTLBStats
Definition: tlb.hh:404
gem5::X86ISA::GpuTLB::EntryList
std::list< TlbEntry * > EntryList
Definition: tlb.hh:70
gem5::statistics::Formula
A formula for statistics that is calculated when printed.
Definition: statistics.hh:2539
std::vector
STL vector class.
Definition: stl.hh:37
gem5::X86ISA::GpuTLB::lookup
TlbEntry * lookup(Addr va, bool update_lru=true)
Definition: tlb.cc:214
gem5::X86ISA::GpuTLB::TranslationState::issueTime
uint64_t issueTime
Definition: tlb.hh:299
gem5::X86ISA::Walker
Definition: pagetable_walker.hh:60
gem5::X86ISA::GpuTLB::GpuTLBStats::globalTLBMissRate
statistics::Formula globalTLBMissRate
Definition: tlb.hh:421
gem5::X86ISA::GpuTLB::FA
bool FA
true if this is a fully-associative TLB
Definition: tlb.hh:123
gem5::X86ISA::GpuTLB::TLBEvent::getTLBEventVaddr
Addr getTLBEventVaddr()
Definition: tlb.cc:1014
gem5::X86ISA::GpuTLB::CpuSidePort::recvRespRetry
virtual void recvRespRetry()
Called by the peer if sendTimingResp was called on this protocol (causing recvTimingResp to be called...
Definition: tlb.hh:228
gem5::InvalidPortID
const PortID InvalidPortID
Definition: types.hh:253
gem5::X86ISA::GpuTLB::insert
TlbEntry * insert(Addr vpn, TlbEntry &entry)
Definition: tlb.cc:158
gem5::X86ISA::GpuTLB::GpuTLBStats::globalNumTLBAccesses
statistics::Scalar globalNumTLBAccesses
Definition: tlb.hh:418
gem5::X86ISA::GpuTLB::tlbOutcome
tlbOutcome
Definition: tlb.hh:194
gem5::X86ISA::GpuTLB::lookupIt
EntryList::iterator lookupIt(Addr va, bool update_lru=true)
Definition: tlb.cc:184
gem5::X86ISA::GpuTLB::CpuSidePort::index
int index
Definition: tlb.hh:221
request.hh
gem5::X86ISA::GpuTLB::AccessInfo::lastTimeAccessed
unsigned int lastTimeAccessed
Definition: tlb.hh:377
gem5::X86ISA::GpuTLB::allocationPolicy
bool allocationPolicy
Allocation Policy: true if we always allocate on a hit, false otherwise.
Definition: tlb.hh:130
gem5::X86ISA::GpuTLB::setConfigAddress
void setConfigAddress(uint32_t addr)
Definition: tlb.cc:241
gem5::X86ISA::GpuTLB::Translation::finish
virtual void finish(Fault fault, const RequestPtr &req, ThreadContext *tc, Mode mode)=0
The memory for this object may be dynamically allocated, and it may be responsible for cleaning itsle...
gem5::X86ISA::GpuTLB::hasMemSidePort
bool hasMemSidePort
if true, then this is not the last level TLB
Definition: tlb.hh:135
gem5::X86ISA::GpuTLB::missLatency1
int missLatency1
Definition: tlb.hh:171
gem5::X86ISA::GpuTLB::TranslationState::isPrefetch
bool isPrefetch
Definition: tlb.hh:297
gem5::RequestPort
A RequestPort is a specialisation of a Port, which implements the default protocol for the three diff...
Definition: port.hh:77
gem5::X86ISA::GpuTLB::GpuTLBStats::localLatency
statistics::Formula localLatency
Definition: tlb.hh:431
gem5::X86ISA::GpuTLB::cleanupQueue
std::queue< Addr > cleanupQueue
Definition: tlb.hh:362
gem5::X86ISA::TlbEntry
Definition: pagetable.hh:65
gem5::X86ISA::GpuTLB::CpuSidePort::getAddrRanges
virtual AddrRangeList getAddrRanges() const
Get a list of the non-overlapping address ranges the owner is responsible for.
Definition: tlb.cc:1241
gem5::X86ISA::GpuTLB::translateAtomic
Fault translateAtomic(const RequestPtr &req, ThreadContext *tc, Mode mode, int &latency)
Definition: tlb.cc:622
gem5::X86ISA::GpuTLB::serialize
virtual void serialize(CheckpointOut &cp) const override
Serialize an object.
Definition: tlb.cc:653
gem5::X86ISA::GpuTLB::TranslationState
TLB TranslationState: this currently is a somewhat bastardization of the usage of SenderState,...
Definition: tlb.hh:283
gem5::X86ISA::GpuTLB::TranslationState::hitLevel
int hitLevel
Definition: tlb.hh:307
gem5::X86ISA::GpuTLB::translate
Fault translate(const RequestPtr &req, ThreadContext *tc, Translation *translation, Mode mode, bool &delayedResponse, bool timing, int &latency)
Definition: tlb.cc:418
gem5::X86ISA::GpuTLB::TranslationState::ports
std::vector< ResponsePort * > ports
Definition: tlb.hh:301
gem5::X86ISA::GpuTLB::accessDistance
bool accessDistance
Print out accessDistance stats.
Definition: tlb.hh:141
gem5::X86ISA::GpuTLB::unserialize
virtual void unserialize(CheckpointIn &cp) override
Unserialize an object.
Definition: tlb.cc:658
gem5::X86ISA::GpuTLB::handleFuncTranslationReturn
void handleFuncTranslationReturn(PacketPtr pkt, tlbOutcome outcome)
handleFuncTranslationReturn is called on a TLB hit, when a TLB miss returns or when a page fault retu...
Definition: tlb.cc:1049
gem5::ThreadContext
ThreadContext is the external interface to all thread state for anything outside of the CPU.
Definition: thread_context.hh:94
gem5::X86ISA::GpuTLB::issueTLBLookup
void issueTLBLookup(PacketPtr pkt)
Do the TLB lookup for this coalesced request and schedule another event <TLB access latency> cycles l...
Definition: tlb.cc:668
gem5::Fault
std::shared_ptr< FaultBase > Fault
Definition: types.hh:255
gem5::X86ISA::GpuTLB::GpuTLB
GpuTLB(const Params &p)
Definition: tlb.cc:65
sim_object.hh
gem5::X86ISA::GpuTLB::CpuSidePort::recvAtomic
virtual Tick recvAtomic(PacketPtr pkt)
Receive an atomic request packet from the peer.
Definition: tlb.hh:224
gem5::Event
Definition: eventq.hh:251
gem5::Packet
A Packet is used to encapsulate a transfer between two objects in the memory system (e....
Definition: packet.hh:283
gem5::X86ISA::GpuTLB::exitEvent
EventFunctionWrapper exitEvent
Definition: tlb.hh:401
gem5::probing::Packet
ProbePointArg< PacketInfo > Packet
Packet probe point.
Definition: mem.hh:109
statistics.hh
gem5::X86ISA::GpuTLB::doMmuRegRead
Tick doMmuRegRead(ThreadContext *tc, Packet *pkt)
gem5::X86ISA::GpuTLB::Params
X86GPUTLBParams Params
Definition: tlb.hh:75
gem5::Tick
uint64_t Tick
Tick count type.
Definition: types.hh:58
gem5::X86ISA::GpuTLB::updatePageFootprint
void updatePageFootprint(Addr virt_page_addr)
Definition: tlb.cc:1306
segment.hh
gem5::X86ISA::GpuTLB::translateInt
Fault translateInt(bool read, const RequestPtr &req, ThreadContext *tc)
Definition: tlb.cc:300
gem5::X86ISA::GpuTLB::TLBEvent
Definition: tlb.hh:335
gem5::RequestPtr
std::shared_ptr< Request > RequestPtr
Definition: request.hh:92
gem5::X86ISA::GpuTLB
Definition: tlb.hh:65
gem5::X86ISA::GpuTLB::MemSidePort::MemSidePort
MemSidePort(const std::string &_name, GpuTLB *gpu_TLB, PortID _index)
Definition: tlb.hh:242
gem5::X86ISA::GpuTLB::Translation
Definition: tlb.hh:81
port.hh
gem5::X86ISA::GpuTLB::tlbLookup
bool tlbLookup(const RequestPtr &req, ThreadContext *tc, bool update_stats)
TLB_lookup will only perform a TLB lookup returning true on a TLB hit and false on a TLB miss.
Definition: tlb.cc:369
gem5::X86ISA::GpuTLB::MemSidePort
MemSidePort is the TLB Port closer to the memory side If this is a last level TLB then this port will...
Definition: tlb.hh:239
gem5::X86ISA::GpuTLB::AccessInfo::accessesPerPage
unsigned int accessesPerPage
Definition: tlb.hh:378
gem5::X86ISA::GpuTLB::dumpAll
void dumpAll()
gem5::X86ISA::GpuTLB::getPort
Port & getPort(const std::string &if_name, PortID idx=InvalidPortID) override
Get a port with a given name and index.
Definition: tlb.cc:136
gem5::X86ISA::GpuTLB::GpuTLBStats::globalNumTLBMisses
statistics::Scalar globalNumTLBMisses
Definition: tlb.hh:420
gem5::X86ISA::GpuTLB::translationReturnEvent
std::unordered_map< Addr, TLBEvent * > translationReturnEvent
Definition: tlb.hh:358
gem5::X86ISA::GpuTLB::GpuTLBStats::pageTableCycles
statistics::Scalar pageTableCycles
Definition: tlb.hh:426
gem5::Packet::SenderState
A virtual base opaque structure used to hold state associated with the packet (e.g....
Definition: packet.hh:457
gem5::X86ISA::GpuTLB::CpuSidePort::recvReqRetry
virtual void recvReqRetry()
Definition: tlb.cc:1233
gem5::X86ISA::GpuTLB::freeList
std::vector< EntryList > freeList
Definition: tlb.hh:150
gem5::X86ISA::GpuTLB::TranslationState::TranslationState
TranslationState(Mode tlb_mode, ThreadContext *_tc, bool is_prefetch=false, Packet::SenderState *_saved=nullptr)
Definition: tlb.hh:310
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::X86ISA::GpuTLB::Translation::markDelayed
virtual void markDelayed()=0
Signal that the translation has been delayed due to a hw page table walk.
gem5::X86ISA::GpuTLB::GpuTLBStats::localNumTLBHits
statistics::Scalar localNumTLBHits
Definition: tlb.hh:411
gem5::X86ISA::GpuTLB::cpuSidePort
std::vector< CpuSidePort * > cpuSidePort
Definition: tlb.hh:260
gem5::X86ISA::GpuTLB::invalidateNonGlobal
void invalidateNonGlobal()
Definition: tlb.cc:247
gem5::X86ISA::GpuTLB::CpuSidePort::recvRangeChange
virtual void recvRangeChange()
Definition: tlb.hh:226
gem5::X86ISA::GpuTLB::GpuTLBStats::localCycles
statistics::Scalar localCycles
Definition: tlb.hh:429
gem5::ArmISA::va
Bitfield< 8 > va
Definition: misc_types.hh:276
gem5::ClockedObject
The ClockedObject class extends the SimObject with a clock and accessor functions to relate ticks to ...
Definition: clocked_object.hh:234
gem5::X86ISA::GpuTLB::setMask
Addr setMask
Definition: tlb.hh:124
gem5::X86ISA::GpuTLB::TLBFootprint
AccessPatternTable TLBFootprint
Definition: tlb.hh:396
gem5::X86ISA::GpuTLB::entryList
std::vector< EntryList > entryList
An entryList per set is the equivalent of an LRU stack; it's used to guide replacement decisions.
Definition: tlb.hh:159
gem5::X86ISA::GpuTLB::MemSidePort::recvTimingResp
virtual bool recvTimingResp(PacketPtr pkt)
MemSidePort receives the packet back.
Definition: tlb.cc:1255
gem5::X86ISA::GpuTLB::TLB_HIT
@ TLB_HIT
Definition: tlb.hh:194
gem5::EventFunctionWrapper
Definition: eventq.hh:1115
gem5::X86ISA::GpuTLB::MISS_RETURN
@ MISS_RETURN
Definition: tlb.hh:194
gem5::X86ISA::GpuTLB::AccessInfo::sumDistance
unsigned int sumDistance
Definition: tlb.hh:391
gem5::X86ISA::GpuTLB::MemSidePort::retries
std::deque< PacketPtr > retries
Definition: tlb.hh:246
gem5::ResponsePort
A ResponsePort is a specialization of a port.
Definition: port.hh:268
gem5::X86ISA::GpuTLB::TLBEvent::tlb
GpuTLB * tlb
Definition: tlb.hh:338
gem5::X86ISA::GpuTLB::TLBEvent::process
void process()
Definition: tlb.cc:996
gem5::X86ISA::GpuTLB::TLBEvent::description
const char * description() const
Return a C string describing the event.
Definition: tlb.cc:1002
gem5::X86ISA::GpuTLB::hitLatency
int hitLatency
Definition: tlb.hh:170
gem5::X86ISA::GpuTLB::TranslationState::tlbEntry
TlbEntry * tlbEntry
Definition: tlb.hh:295
gem5::X86ISA::GpuTLB::TLBEvent::TLBEvent
TLBEvent(GpuTLB *_tlb, Addr _addr, tlbOutcome outcome, PacketPtr _pkt)
Definition: tlb.cc:748
gem5::X86ISA::GpuTLB::TLBEvent::updateOutcome
void updateOutcome(tlbOutcome _outcome)
Definition: tlb.cc:1008
gem5::X86ISA::GpuTLB::missLatency2
int missLatency2
Definition: tlb.hh:172
gem5::Port
Ports are used to interface objects to each other.
Definition: port.hh:61
gem5::X86ISA::GpuTLB::MemSidePort::recvRangeChange
virtual void recvRangeChange()
Called to receive an address range change from the peer response port.
Definition: tlb.hh:255
gem5::X86ISA::GpuTLB::Translation::~Translation
virtual ~Translation()
Definition: tlb.hh:84
gem5::X86ISA::GpuTLB::MemSidePort::recvAtomic
virtual Tick recvAtomic(PacketPtr pkt)
Definition: tlb.hh:253
clocked_object.hh
std::deque
STL deque class.
Definition: stl.hh:44
gem5::X86ISA::GpuTLB::pagingProtectionChecks
void pagingProtectionChecks(ThreadContext *tc, PacketPtr pkt, TlbEntry *tlb_entry, Mode mode)
Do Paging protection checks.
Definition: tlb.cc:760
gem5::X86ISA::GpuTLB::PAGE_WALK
@ PAGE_WALK
Definition: tlb.hh:194
logging.hh
gem5::statistics::Group
Statistics container.
Definition: group.hh:93
gem5::X86ISA::GpuTLB::MemSidePort::recvFunctional
virtual void recvFunctional(PacketPtr pkt)
Definition: tlb.hh:254
gem5::X86ISA::GpuTLB::AccessInfo::meanDistance
unsigned int meanDistance
Definition: tlb.hh:392
gem5::X86ISA::p
Bitfield< 0 > p
Definition: pagetable.hh:151
gem5::X86ISA::GpuTLB::AccessPatternTable
std::unordered_map< Addr, AccessInfo > AccessPatternTable
Definition: tlb.hh:395
gem5::X86ISA::GpuTLB::invalidateAll
void invalidateAll()
Definition: tlb.cc:227
gem5::CheckpointOut
std::ostream CheckpointOut
Definition: serialize.hh:66
gem5::X86ISA::GpuTLB::AccessInfo
This hash map will use the virtual page address as a key and will keep track of total number of acces...
Definition: tlb.hh:375
gem5::X86ISA::GpuTLB::tlb
std::vector< TlbEntry > tlb
Definition: tlb.hh:143
gem5::X86ISA::GpuTLB::GpuTLBStats::globalNumTLBHits
statistics::Scalar globalNumTLBHits
Definition: tlb.hh:419
gem5::X86ISA::GpuTLB::assoc
int assoc
Definition: tlb.hh:117
std::list< TlbEntry * >
gem5::X86ISA::GpuTLB::CpuSidePort::recvTimingReq
virtual bool recvTimingReq(PacketPtr pkt)
recvTiming receives a coalesced timing request from a TLBCoalescer and it calls issueTLBLookup() It o...
Definition: tlb.cc:1026
gem5::X86ISA::GpuTLB::translateTiming
void translateTiming(const RequestPtr &req, ThreadContext *tc, Translation *translation, Mode mode, int &latency)
Definition: tlb.cc:632
gem5::X86ISA::GpuTLB::handleTranslationReturn
void handleTranslationReturn(Addr addr, tlbOutcome outcome, PacketPtr pkt)
handleTranslationReturn is called on a TLB hit, when a TLB miss returns or when a page fault returns.
Definition: tlb.cc:795
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: tlb.cc:60
gem5::X86ISA::GpuTLB::doMmuRegWrite
Tick doMmuRegWrite(ThreadContext *tc, Packet *pkt)
gem5::X86ISA::GpuTLB::MemSidePort::recvReqRetry
virtual void recvReqRetry()
Called by the peer if sendTimingReq was called on this peer (causing recvTimingReq to be called on th...
Definition: tlb.cc:1274
gem5::X86ISA::GpuTLB::TranslationState::reqCnt
std::vector< int > reqCnt
Definition: tlb.hh:305
gem5::X86ISA::GpuTLB::demapPage
void demapPage(Addr va, uint64_t asn)
Definition: tlb.cc:265
gem5::X86ISA::GpuTLB::GpuTLBStats::localNumTLBMisses
statistics::Scalar localNumTLBMisses
Definition: tlb.hh:412
callback.hh
gem5::Named::_name
const std::string _name
Definition: named.hh:41
gem5::X86ISA::GpuTLB::CpuSidePort
Definition: tlb.hh:212
gem5::X86ISA::GpuTLB::maxCoalescedReqs
int maxCoalescedReqs
Definition: tlb.hh:319
panic
#define panic(...)
This implements a cprintf based panic() function.
Definition: logging.hh:178
gem5::X86ISA::GpuTLB::cleanupEvent
EventFunctionWrapper cleanupEvent
Definition: tlb.hh:368
gem5::ArmISA::mode
Bitfield< 4, 0 > mode
Definition: misc_types.hh:74
gem5::X86ISA::addr
Bitfield< 3 > addr
Definition: types.hh:84

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