gem5  v22.0.0.1
Namespaces | Functions
faults.cc File Reference
#include "arch/sparc/faults.hh"
#include <algorithm>
#include "arch/sparc/mmu.hh"
#include "arch/sparc/process.hh"
#include "arch/sparc/se_workload.hh"
#include "arch/sparc/sparc_traits.hh"
#include "arch/sparc/types.hh"
#include "base/bitfield.hh"
#include "base/compiler.hh"
#include "base/trace.hh"
#include "cpu/base.hh"
#include "cpu/thread_context.hh"
#include "mem/page_table.hh"
#include "sim/full_system.hh"
#include "sim/process.hh"

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Namespaces

 gem5
 Reference material can be found at the JEDEC website: UFS standard http://www.jedec.org/standards-documents/results/jesd220 UFS HCI specification http://www.jedec.org/standards-documents/results/jesd223.
 
 gem5::SparcISA
 

Functions

void gem5::SparcISA::enterREDState (ThreadContext *tc)
 This causes the thread context to enter RED state. More...
 
void gem5::SparcISA::doREDFault (ThreadContext *tc, TrapType tt)
 This sets everything up for a RED state trap except for actually jumping to the handler. More...
 
void gem5::SparcISA::doNormalFault (ThreadContext *tc, TrapType tt, bool gotoHpriv)
 This sets everything up for a normal trap except for actually jumping to the handler. More...
 
void gem5::SparcISA::getREDVector (RegVal TT, Addr &PC, Addr &NPC)
 
void gem5::SparcISA::getHyperVector (ThreadContext *tc, Addr &PC, Addr &NPC, RegVal TT)
 
void gem5::SparcISA::getPrivVector (ThreadContext *tc, Addr &PC, Addr &NPC, RegVal TT, RegVal TL)
 

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