gem5  v22.0.0.1
mmu.hh
Go to the documentation of this file.
1 /*
2  * Copyright (c) 2020 ARM Limited
3  * All rights reserved
4  *
5  * The license below extends only to copyright in the software and shall
6  * not be construed as granting a license to any other intellectual
7  * property including but not limited to intellectual property relating
8  * to a hardware implementation of the functionality of the software
9  * licensed hereunder. You may use the software subject to the license
10  * terms below provided that you ensure that this notice is replicated
11  * unmodified and in its entirety in all distributions of the software,
12  * modified or unmodified, in source code or in binary form.
13  *
14  * Redistribution and use in source and binary forms, with or without
15  * modification, are permitted provided that the following conditions are
16  * met: redistributions of source code must retain the above copyright
17  * notice, this list of conditions and the following disclaimer;
18  * redistributions in binary form must reproduce the above copyright
19  * notice, this list of conditions and the following disclaimer in the
20  * documentation and/or other materials provided with the distribution;
21  * neither the name of the copyright holders nor the names of its
22  * contributors may be used to endorse or promote products derived from
23  * this software without specific prior written permission.
24  *
25  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36  */
37 
38 #ifndef __ARCH_SPARC_MMU_HH__
39 #define __ARCH_SPARC_MMU_HH__
40 
41 #include "arch/generic/mmu.hh"
42 #include "arch/sparc/page_size.hh"
43 #include "arch/sparc/tlb.hh"
44 
45 #include "params/SparcMMU.hh"
46 
47 namespace gem5
48 {
49 
50 namespace SparcISA {
51 
52 class MMU : public BaseMMU
53 {
54  public:
55  MMU(const SparcMMUParams &p)
56  : BaseMMU(p)
57  {}
58 
61  Mode mode, Request::Flags flags) override
62  {
64  PageBytes, start, size, tc, this, mode, flags));
65  }
66 
67  void
68  insertItlbEntry(Addr vpn, int partition_id, int context_id, bool real,
69  const PageTableEntry& PTE, int entry=-1)
70  {
71  static_cast<TLB*>(itb)->insert(vpn, partition_id,
72  context_id, real, PTE, entry);
73  }
74 
75  void
76  insertDtlbEntry(Addr vpn, int partition_id, int context_id, bool real,
77  const PageTableEntry& PTE, int entry=-1)
78  {
79  static_cast<TLB*>(dtb)->insert(vpn, partition_id,
80  context_id, real, PTE, entry);
81  }
82 };
83 
84 } // namespace SparcISA
85 } // namespace gem5
86 
87 #endif // __ARCH_SPARC_MMU_HH__
gem5::SparcISA::MMU
Definition: mmu.hh:52
gem5::SparcISA::MMU::MMU
MMU(const SparcMMUParams &p)
Definition: mmu.hh:55
gem5::BaseMMU::dtb
BaseTLB * dtb
Definition: mmu.hh:158
gem5::BaseMMU::Mode
Mode
Definition: mmu.hh:56
gem5::BaseMMU
Definition: mmu.hh:53
gem5::Flags< FlagsType >
gem5::ThreadContext
ThreadContext is the external interface to all thread state for anything outside of the CPU.
Definition: thread_context.hh:94
gem5::VegaISA::p
Bitfield< 54 > p
Definition: pagetable.hh:70
gem5::SparcISA::MMU::insertItlbEntry
void insertItlbEntry(Addr vpn, int partition_id, int context_id, bool real, const PageTableEntry &PTE, int entry=-1)
Definition: mmu.hh:68
mmu.hh
gem5::SparcISA::PageTableEntry
Definition: pagetable.hh:68
flags
uint8_t flags
Definition: helpers.cc:66
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
page_size.hh
gem5::SparcISA::PageBytes
const Addr PageBytes
Definition: page_size.hh:41
gem5::SparcISA::MMU::translateFunctional
TranslationGenPtr translateFunctional(Addr start, Addr size, ThreadContext *tc, Mode mode, Request::Flags flags) override
Returns a translation generator for a region of virtual addresses, instead of directly translating a ...
Definition: mmu.hh:60
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: gpu_translation_state.hh:37
gem5::SparcISA::TLB
Definition: tlb.hh:53
gem5::SparcISA::MMU::insertDtlbEntry
void insertDtlbEntry(Addr vpn, int partition_id, int context_id, bool real, const PageTableEntry &PTE, int entry=-1)
Definition: mmu.hh:76
gem5::ArmISA::PTE
Definition: pagetable.hh:76
tlb.hh
gem5::TranslationGenPtr
std::unique_ptr< TranslationGen > TranslationGenPtr
Definition: translation_gen.hh:128
gem5::BaseMMU::itb
BaseTLB * itb
Definition: mmu.hh:159
gem5::BaseMMU::MMUTranslationGen
Definition: mmu.hh:126
gem5::ArmISA::mode
Bitfield< 4, 0 > mode
Definition: misc_types.hh:74

Generated on Sat Jun 18 2022 08:12:13 for gem5 by doxygen 1.8.17