55 (
"power_on_reset", 0x001, 0, {{
H,
H,
H}});
59 (
"watch_dog_reset", 0x002, 120, {{
H,
H,
H}});
63 (
"externally_initiated_reset", 0x003, 110, {{
H,
H,
H}});
67 (
"software_initiated_reset", 0x004, 130, {{
SH,
SH,
H}});
71 (
"RED_state_exception", 0x005, 1, {{
H,
H,
H}});
75 (
"store_error", 0x007, 201, {{
H,
H,
H}});
79 (
"instruction_access_exception", 0x008, 300, {{
H,
H,
H}});
88 (
"instruction_access_error", 0x00A, 400, {{
H,
H,
H}});
92 (
"illegal_instruction", 0x010, 620, {{
H,
H,
H}});
96 (
"privileged_opcode", 0x011, 700, {{P,
SH,
SH}});
110 (
"fp_disabled", 0x020, 800, {{P, P,
H}});
116 (
"fp_disabled", 0x020, 800, {{P, P,
H}});
120 (
"fp_exception_ieee_754", 0x021, 1110, {{P, P,
H}});
124 (
"fp_exception_other", 0x022, 1110, {{P, P,
H}});
128 (
"tag_overflow", 0x023, 1400, {{P, P,
H}});
132 (
"clean_window", 0x024, 1010, {{P, P,
H}});
136 (
"division_by_zero", 0x028, 1500, {{P, P,
H}});
140 (
"internal_processor_error", 0x029, 4, {{
H,
H,
H}});
144 (
"instruction_invalid_tsb_entry", 0x02A, 210, {{
H,
H,
SH}});
148 (
"data_invalid_tsb_entry", 0x02B, 1203, {{
H,
H,
H}});
152 (
"data_access_exception", 0x030, 1201, {{
H,
H,
H}});
161 (
"data_access_error", 0x032, 1210, {{
H,
H,
H}});
165 (
"data_access_protection", 0x033, 1207, {{
H,
H,
H}});
169 (
"mem_address_not_aligned", 0x034, 1020, {{
H,
H,
H}});
173 (
"LDDF_mem_address_not_aligned", 0x035, 1010, {{
H,
H,
H}});
177 (
"STDF_mem_address_not_aligned", 0x036, 1010, {{
H,
H,
H}});
181 (
"privileged_action", 0x037, 1110, {{
H,
H,
SH}});
185 (
"LDQF_mem_address_not_aligned", 0x038, 1010, {{
H,
H,
H}});
189 (
"STQF_mem_address_not_aligned", 0x039, 1010, {{
H,
H,
H}});
193 (
"instruction_real_translation_miss", 0x03E, 208, {{
H,
H,
SH}});
197 (
"data_real_translation_miss", 0x03F, 1203, {{
H,
H,
H}});
206 (
"interrupt_level_n", 0x040, 0, {{P, P,
SH}});
210 (
"hstick_match", 0x05E, 1601, {{
H,
H,
H}});
214 (
"trap_level_zero", 0x05F, 202, {{
H,
H,
SH}});
218 (
"interrupt_vector", 0x060, 2630, {{
H,
H,
H}});
222 (
"PA_watchpoint", 0x061, 1209, {{
H,
H,
H}});
226 (
"VA_watchpoint", 0x062, 1120, {{P, P,
SH}});
230 (
"fast_instruction_access_MMU_miss", 0x064, 208, {{
H,
H,
SH}});
234 (
"fast_data_access_MMU_miss", 0x068, 1203, {{
H,
H,
H}});
238 (
"fast_data_access_protection", 0x06C, 1207, {{
H,
H,
H}});
242 (
"instruction_break", 0x076, 610, {{
H,
H,
H}});
246 (
"cpu_mondo", 0x07C, 1608, {{P, P,
SH}});
250 (
"dev_mondo", 0x07D, 1611, {{P, P,
SH}});
254 (
"resume_error", 0x07E, 3330, {{P, P,
SH}});
258 (
"spill_n_normal", 0x080, 900, {{P, P,
H}});
262 (
"spill_n_other", 0x0A0, 900, {{P, P,
H}});
266 (
"fill_n_normal", 0x0C0, 900, {{P, P,
H}});
270 (
"fill_n_other", 0x0E0, 900, {{P, P,
H}});
274 (
"trap_instruction", 0x100, 1602, {{P, P,
H}});
348 bool priv = pstate.priv;
360 bool changedCWP =
true;
363 else if (0x80 <= tt && tt <= 0xbf)
364 CWP += (CANSAVE + 2);
365 else if (0xc0 <= tt && tt <= 0xff)
451 pstate.cle = pstate.tle;
456 bool changedCWP =
true;
459 else if (0x80 <= tt && tt <= 0xbf)
460 CWP += (CANSAVE + 2);
461 else if (0xc0 <= tt && tt <= 0xff)
476 const Addr RSTVAddr = 0xFFF0000000ULL;
477 PC = RSTVAddr | ((TT << 5) & 0xFF);
485 PC = (HTBA & ~
mask(14)) | ((TT << 5) &
mask(14));
493 PC = (TBA & ~
mask(15)) |
494 (TL > 1 ? (1 << 14) : 0) |
495 ((TT << 5) &
mask(14));
519 else if (pstate.priv)
526 if (hpstate.red || (
tl ==
MaxTL - 1)) {
533 panic(
"Should go to error state here.. crap\n");
633 panic_if(!pte,
"Tried to execute unmapped address %#x.\n",
vaddr);
635 Addr alignedvaddr =
p->pTable->pageAlign(
vaddr);
646 bool is_real_address = !
bits(tlbdata, 4);
650 bool trapped =
bits(tlbdata, 18, 16) > 0;
656 int primary_context =
bits(tlbdata, 47, 32);
659 int const partition_id = 0;
663 int context_id = (is_real_address || trapped) ? 0 : primary_context;
675 alignedvaddr, partition_id, context_id,
689 if (!pte &&
p->fixupFault(
vaddr))
690 pte =
p->pTable->lookup(
vaddr);
691 panic_if(!pte,
"Tried to access unmapped address %#x.\n",
vaddr);
693 Addr alignedvaddr =
p->pTable->pageAlign(
vaddr);
707 int primary_context =
bits(tlbdata, 47, 32);
723 int is_real_address = !
bits(tlbdata, 5);
735 ASI asi =
static_cast<ASI>(reg_asi);
741 bool trapped =
bits(tlbdata, 18, 16) > 0;
745 int context_id = ((!
hpriv && !
red && is_real_address) ||
748 ? 0 : primary_context;
751 int const partition_id = 0;
763 alignedvaddr, partition_id, context_id,
virtual void invoke(ThreadContext *tc, const StaticInstPtr &inst=nullStaticInstPtr)
void invoke(ThreadContext *tc, const StaticInstPtr &inst=nullStaticInstPtr)
void invoke(ThreadContext *tc, const StaticInstPtr &inst=nullStaticInstPtr)
void invoke(ThreadContext *tc, const StaticInstPtr &inst=nullStaticInstPtr)
void invoke(ThreadContext *tc, const StaticInstPtr &inst=nullStaticInstPtr)
virtual void handleTrap(ThreadContext *tc, int trapNum)
virtual PrivilegeLevel getNextLevel(PrivilegeLevel current)=0
void invoke(ThreadContext *tc, const StaticInstPtr &inst=nullStaticInstPtr)
virtual TrapType trapType()=0
void invoke(ThreadContext *tc, const StaticInstPtr &inst=nullStaticInstPtr)
void invoke(ThreadContext *tc, const StaticInstPtr &inst=nullStaticInstPtr)
Workload * workload
OS kernel.
ThreadContext is the external interface to all thread state for anything outside of the CPU.
virtual void setMiscReg(RegIndex misc_reg, RegVal val)=0
virtual RegVal getReg(const RegId ®) const
virtual void setMiscRegNoEffect(RegIndex misc_reg, RegVal val)=0
virtual const PCStateBase & pcState() const =0
virtual System * getSystemPtr()=0
virtual RegVal readMiscRegNoEffect(RegIndex misc_reg) const =0
virtual Process * getProcessPtr()=0
virtual BaseMMU * getMMUPtr()=0
constexpr T bits(T val, unsigned first, unsigned last)
Extract the bitfield from position 'first' to 'last' (inclusive) from 'val' and right justify it.
constexpr uint64_t mask(unsigned nbits)
Generate a 64-bit mask of 'nbits' 1s, right justified.
constexpr void replaceBits(T &val, unsigned first, unsigned last, B bit_val)
A convenience function to replace bits first to last of val with bit_val in place.
#define panic(...)
This implements a cprintf based panic() function.
#define panic_if(cond,...)
Conditional panic macro that checks the supplied condition and only panics if the condition is true a...
MipsFaultBase::FaultVals FaultVals
@ MISCREG_HPSTATE
Hyper privileged registers.
@ MISCREG_ASI
Ancillary State Registers.
@ MISCREG_TPC
Privilged Registers.
void getREDVector(RegVal TT, Addr &PC, Addr &NPC)
void getHyperVector(ThreadContext *tc, Addr &PC, Addr &NPC, RegVal TT)
void doREDFault(ThreadContext *tc, TrapType tt)
This sets everything up for a RED state trap except for actually jumping to the handler.
void getPrivVector(ThreadContext *tc, Addr &PC, Addr &NPC, RegVal TT, RegVal TL)
void enterREDState(ThreadContext *tc)
This causes the thread context to enter RED state.
void doNormalFault(ThreadContext *tc, TrapType tt, bool gotoHpriv)
This sets everything up for a normal trap except for actually jumping to the handler.
SignedBitfield< 15, 8 > SH
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
bool FullSystem
The FullSystem variable can be used to determine the current mode of simulation.
Declarations of a non-full system Page Table.