gem5  v21.2.1.1
faults.cc
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28 
29 #include "arch/sparc/faults.hh"
30 
31 #include <algorithm>
32 
33 #include "arch/sparc/mmu.hh"
34 #include "arch/sparc/process.hh"
37 #include "arch/sparc/types.hh"
38 #include "base/bitfield.hh"
39 #include "base/compiler.hh"
40 #include "base/trace.hh"
41 #include "cpu/base.hh"
42 #include "cpu/thread_context.hh"
43 #include "mem/page_table.hh"
44 #include "sim/full_system.hh"
45 #include "sim/process.hh"
46 
47 namespace gem5
48 {
49 
50 namespace SparcISA
51 {
52 
55 ("power_on_reset", 0x001, 0, {{H, H, H}});
56 
59 ("watch_dog_reset", 0x002, 120, {{H, H, H}});
60 
63 ("externally_initiated_reset", 0x003, 110, {{H, H, H}});
64 
67 ("software_initiated_reset", 0x004, 130, {{SH, SH, H}});
68 
71 ("RED_state_exception", 0x005, 1, {{H, H, H}});
72 
75 ("store_error", 0x007, 201, {{H, H, H}});
76 
79 ("instruction_access_exception", 0x008, 300, {{H, H, H}});
80 
81 //XXX This trap is apparently dropped from ua2005
82 /*template<> SparcFaultBase::FaultVals
83  SparcFault<InstructionAccessMMUMiss>::vals
84  ("inst_mmu", 0x009, 2, {{H, H, H}});*/
85 
88 ("instruction_access_error", 0x00A, 400, {{H, H, H}});
89 
92 ("illegal_instruction", 0x010, 620, {{H, H, H}});
93 
96 ("privileged_opcode", 0x011, 700, {{P, SH, SH}});
97 
98 //XXX This trap is apparently dropped from ua2005
99 /*template<> SparcFaultBase::FaultVals
100  SparcFault<UnimplementedLDD>::vals
101  ("unimp_ldd", 0x012, 6, {{H, H, H}});*/
102 
103 //XXX This trap is apparently dropped from ua2005
104 /*template<> SparcFaultBase::FaultVals
105  SparcFault<UnimplementedSTD>::vals
106  ("unimp_std", 0x013, 6, {{H, H, H}});*/
107 
108 template<> SparcFaultBase::FaultVals
110 ("fp_disabled", 0x020, 800, {{P, P, H}});
111 
112 /* SPARCv8 and SPARCv9 define just fp_disabled trap. SIMD is not contemplated
113  * as a separate part. Therefore, we use the same code and TT */
114 template<> SparcFaultBase::FaultVals
116 ("fp_disabled", 0x020, 800, {{P, P, H}});
117 
118 template<> SparcFaultBase::FaultVals
120 ("fp_exception_ieee_754", 0x021, 1110, {{P, P, H}});
121 
122 template<> SparcFaultBase::FaultVals
124 ("fp_exception_other", 0x022, 1110, {{P, P, H}});
125 
126 template<> SparcFaultBase::FaultVals
128 ("tag_overflow", 0x023, 1400, {{P, P, H}});
129 
130 template<> SparcFaultBase::FaultVals
132 ("clean_window", 0x024, 1010, {{P, P, H}});
133 
134 template<> SparcFaultBase::FaultVals
136 ("division_by_zero", 0x028, 1500, {{P, P, H}});
137 
138 template<> SparcFaultBase::FaultVals
140 ("internal_processor_error", 0x029, 4, {{H, H, H}});
141 
142 template<> SparcFaultBase::FaultVals
144 ("instruction_invalid_tsb_entry", 0x02A, 210, {{H, H, SH}});
145 
146 template<> SparcFaultBase::FaultVals
148 ("data_invalid_tsb_entry", 0x02B, 1203, {{H, H, H}});
149 
150 template<> SparcFaultBase::FaultVals
152 ("data_access_exception", 0x030, 1201, {{H, H, H}});
153 
154 //XXX This trap is apparently dropped from ua2005
155 /*template<> SparcFaultBase::FaultVals
156  SparcFault<DataAccessMMUMiss>::vals
157  ("data_mmu", 0x031, 12, {{H, H, H}});*/
158 
159 template<> SparcFaultBase::FaultVals
161 ("data_access_error", 0x032, 1210, {{H, H, H}});
162 
163 template<> SparcFaultBase::FaultVals
165 ("data_access_protection", 0x033, 1207, {{H, H, H}});
166 
167 template<> SparcFaultBase::FaultVals
169 ("mem_address_not_aligned", 0x034, 1020, {{H, H, H}});
170 
171 template<> SparcFaultBase::FaultVals
173 ("LDDF_mem_address_not_aligned", 0x035, 1010, {{H, H, H}});
174 
175 template<> SparcFaultBase::FaultVals
177 ("STDF_mem_address_not_aligned", 0x036, 1010, {{H, H, H}});
178 
179 template<> SparcFaultBase::FaultVals
181 ("privileged_action", 0x037, 1110, {{H, H, SH}});
182 
183 template<> SparcFaultBase::FaultVals
185 ("LDQF_mem_address_not_aligned", 0x038, 1010, {{H, H, H}});
186 
187 template<> SparcFaultBase::FaultVals
189 ("STQF_mem_address_not_aligned", 0x039, 1010, {{H, H, H}});
190 
191 template<> SparcFaultBase::FaultVals
193 ("instruction_real_translation_miss", 0x03E, 208, {{H, H, SH}});
194 
195 template<> SparcFaultBase::FaultVals
197 ("data_real_translation_miss", 0x03F, 1203, {{H, H, H}});
198 
199 //XXX This trap is apparently dropped from ua2005
200 /*template<> SparcFaultBase::FaultVals
201  SparcFault<AsyncDataError>::vals
202  ("async_data", 0x040, 2, {{H, H, H}});*/
203 
204 template<> SparcFaultBase::FaultVals
206 ("interrupt_level_n", 0x040, 0, {{P, P, SH}});
207 
208 template<> SparcFaultBase::FaultVals
210 ("hstick_match", 0x05E, 1601, {{H, H, H}});
211 
212 template<> SparcFaultBase::FaultVals
214 ("trap_level_zero", 0x05F, 202, {{H, H, SH}});
215 
216 template<> SparcFaultBase::FaultVals
218 ("interrupt_vector", 0x060, 2630, {{H, H, H}});
219 
220 template<> SparcFaultBase::FaultVals
222 ("PA_watchpoint", 0x061, 1209, {{H, H, H}});
223 
224 template<> SparcFaultBase::FaultVals
226 ("VA_watchpoint", 0x062, 1120, {{P, P, SH}});
227 
228 template<> SparcFaultBase::FaultVals
230 ("fast_instruction_access_MMU_miss", 0x064, 208, {{H, H, SH}});
231 
232 template<> SparcFaultBase::FaultVals
234 ("fast_data_access_MMU_miss", 0x068, 1203, {{H, H, H}});
235 
236 template<> SparcFaultBase::FaultVals
238 ("fast_data_access_protection", 0x06C, 1207, {{H, H, H}});
239 
240 template<> SparcFaultBase::FaultVals
242 ("instruction_break", 0x076, 610, {{H, H, H}});
243 
244 template<> SparcFaultBase::FaultVals
246 ("cpu_mondo", 0x07C, 1608, {{P, P, SH}});
247 
248 template<> SparcFaultBase::FaultVals
250 ("dev_mondo", 0x07D, 1611, {{P, P, SH}});
251 
252 template<> SparcFaultBase::FaultVals
254 ("resume_error", 0x07E, 3330, {{P, P, SH}});
255 
256 template<> SparcFaultBase::FaultVals
258 ("spill_n_normal", 0x080, 900, {{P, P, H}});
259 
260 template<> SparcFaultBase::FaultVals
262 ("spill_n_other", 0x0A0, 900, {{P, P, H}});
263 
264 template<> SparcFaultBase::FaultVals
266 ("fill_n_normal", 0x0C0, 900, {{P, P, H}});
267 
268 template<> SparcFaultBase::FaultVals
270 ("fill_n_other", 0x0E0, 900, {{P, P, H}});
271 
272 template<> SparcFaultBase::FaultVals
274 ("trap_instruction", 0x100, 1602, {{P, P, H}});
275 
281 void
283 {
284  //@todo Disable the mmu?
285  //@todo Disable watchpoints?
286  HPSTATE hpstate= tc->readMiscRegNoEffect(MISCREG_HPSTATE);
287  hpstate.red = 1;
288  hpstate.hpriv = 1;
289  tc->setMiscReg(MISCREG_HPSTATE, hpstate);
290  // PSTATE.priv is set to 1 here. The manual says it should be 0, but
291  // Legion sets it to 1.
292  PSTATE pstate = tc->readMiscRegNoEffect(MISCREG_PSTATE);
293  pstate.priv = 1;
294  tc->setMiscReg(MISCREG_PSTATE, pstate);
295 }
296 
302 void
304 {
307  PSTATE pstate = tc->readMiscRegNoEffect(MISCREG_PSTATE);
308  HPSTATE hpstate = tc->readMiscRegNoEffect(MISCREG_HPSTATE);
309  CCR ccr = tc->readIntReg(INTREG_CCR);
314  auto &pc = tc->pcState().as<PCState>();
315 
316  TL++;
317 
318  Addr pcMask = pstate.am ? mask(32) : mask(64);
319 
320  // set TSTATE.gl to gl
321  replaceBits(TSTATE, 42, 40, GL);
322  // set TSTATE.ccr to ccr
323  replaceBits(TSTATE, 39, 32, ccr);
324  // set TSTATE.asi to asi
325  replaceBits(TSTATE, 31, 24, ASI);
326  // set TSTATE.pstate to pstate
327  replaceBits(TSTATE, 20, 8, pstate);
328  // set TSTATE.cwp to cwp
329  replaceBits(TSTATE, 4, 0, CWP);
330 
331  // Write back TSTATE
332  tc->setMiscRegNoEffect(MISCREG_TSTATE, TSTATE);
333 
334  // set TPC to PC
335  tc->setMiscRegNoEffect(MISCREG_TPC, pc.pc() & pcMask);
336  // set TNPC to NPC
337  tc->setMiscRegNoEffect(MISCREG_TNPC, pc.npc() & pcMask);
338 
339  // set HTSTATE.hpstate to hpstate
340  tc->setMiscRegNoEffect(MISCREG_HTSTATE, hpstate);
341 
342  // TT = trap type;
344 
345  // Update GL
346  tc->setMiscReg(MISCREG_GL, std::min<int>(GL+1, MaxGL));
347 
348  bool priv = pstate.priv; // just save the priv bit
349  pstate = 0;
350  pstate.priv = priv;
351  pstate.pef = 1;
352  tc->setMiscRegNoEffect(MISCREG_PSTATE, pstate);
353 
354  hpstate.red = 1;
355  hpstate.hpriv = 1;
356  hpstate.ibe = 0;
357  hpstate.tlz = 0;
358  tc->setMiscRegNoEffect(MISCREG_HPSTATE, hpstate);
359 
360  bool changedCWP = true;
361  if (tt == 0x24)
362  CWP++;
363  else if (0x80 <= tt && tt <= 0xbf)
364  CWP += (CANSAVE + 2);
365  else if (0xc0 <= tt && tt <= 0xff)
366  CWP--;
367  else
368  changedCWP = false;
369 
370  if (changedCWP) {
371  CWP = (CWP + NWindows) % NWindows;
372  tc->setMiscReg(MISCREG_CWP, CWP);
373  }
374 }
375 
381 void
382 doNormalFault(ThreadContext *tc, TrapType tt, bool gotoHpriv)
383 {
386  PSTATE pstate = tc->readMiscRegNoEffect(MISCREG_PSTATE);
387  HPSTATE hpstate = tc->readMiscRegNoEffect(MISCREG_HPSTATE);
388  CCR ccr = tc->readIntReg(INTREG_CCR);
391  RegVal CANSAVE = tc->readIntReg(INTREG_CANSAVE);
393  auto &pc = tc->pcState().as<PCState>();
394 
395  // Increment the trap level
396  TL++;
398 
399  Addr pcMask = pstate.am ? mask(32) : mask(64);
400 
401  // Save off state
402 
403  // set TSTATE.gl to gl
404  replaceBits(TSTATE, 42, 40, GL);
405  // set TSTATE.ccr to ccr
406  replaceBits(TSTATE, 39, 32, ccr);
407  // set TSTATE.asi to asi
408  replaceBits(TSTATE, 31, 24, ASI);
409  // set TSTATE.pstate to pstate
410  replaceBits(TSTATE, 20, 8, pstate);
411  // set TSTATE.cwp to cwp
412  replaceBits(TSTATE, 4, 0, CWP);
413 
414  // Write back TSTATE
415  tc->setMiscRegNoEffect(MISCREG_TSTATE, TSTATE);
416 
417  // set TPC to PC
418  tc->setMiscRegNoEffect(MISCREG_TPC, pc.pc() & pcMask);
419  // set TNPC to NPC
420  tc->setMiscRegNoEffect(MISCREG_TNPC, pc.npc() & pcMask);
421 
422  // set HTSTATE.hpstate to hpstate
423  tc->setMiscRegNoEffect(MISCREG_HTSTATE, hpstate);
424 
425  // TT = trap type;
427 
428  // Update the global register level
429  if (!gotoHpriv)
430  tc->setMiscReg(MISCREG_GL, std::min<int>(GL + 1, MaxPGL));
431  else
432  tc->setMiscReg(MISCREG_GL, std::min<int>(GL + 1, MaxGL));
433 
434  // pstate.mm is unchanged
435  pstate.pef = 1; // PSTATE.pef = whether or not an fpu is present
436  pstate.am = 0;
437  pstate.ie = 0;
438  // pstate.tle is unchanged
439  // pstate.tct = 0
440 
441  if (gotoHpriv) {
442  pstate.cle = 0;
443  // The manual says PSTATE.priv should be 0, but Legion leaves it alone
444  hpstate.red = 0;
445  hpstate.hpriv = 1;
446  hpstate.ibe = 0;
447  // hpstate.tlz is unchanged
448  tc->setMiscRegNoEffect(MISCREG_HPSTATE, hpstate);
449  } else { // we are going to priv
450  pstate.priv = 1;
451  pstate.cle = pstate.tle;
452  }
453  tc->setMiscRegNoEffect(MISCREG_PSTATE, pstate);
454 
455 
456  bool changedCWP = true;
457  if (tt == 0x24)
458  CWP++;
459  else if (0x80 <= tt && tt <= 0xbf)
460  CWP += (CANSAVE + 2);
461  else if (0xc0 <= tt && tt <= 0xff)
462  CWP--;
463  else
464  changedCWP = false;
465 
466  if (changedCWP) {
467  CWP = (CWP + NWindows) % NWindows;
468  tc->setMiscReg(MISCREG_CWP, CWP);
469  }
470 }
471 
472 void
473 getREDVector(RegVal TT, Addr &PC, Addr &NPC)
474 {
475  //XXX The following constant might belong in a header file.
476  const Addr RSTVAddr = 0xFFF0000000ULL;
477  PC = RSTVAddr | ((TT << 5) & 0xFF);
478  NPC = PC + sizeof(MachInst);
479 }
480 
481 void
483 {
485  PC = (HTBA & ~mask(14)) | ((TT << 5) & mask(14));
486  NPC = PC + sizeof(MachInst);
487 }
488 
489 void
491 {
493  PC = (TBA & ~mask(15)) |
494  (TL > 1 ? (1 << 14) : 0) |
495  ((TT << 5) & mask(14));
496  NPC = PC + sizeof(MachInst);
497 }
498 
499 void
501 {
502  FaultBase::invoke(tc);
503  if (!FullSystem)
504  return;
505 
506 
507  // We can refer to this to see what the trap level -was-, but something
508  // in the middle could change it in the regfile out from under us.
511  PSTATE pstate = tc->readMiscRegNoEffect(MISCREG_PSTATE);
512  HPSTATE hpstate = tc->readMiscRegNoEffect(MISCREG_HPSTATE);
513 
514  Addr PC, NPC;
515 
516  PrivilegeLevel current;
517  if (hpstate.hpriv)
518  current = Hyperprivileged;
519  else if (pstate.priv)
520  current = Privileged;
521  else
522  current = User;
523 
524  PrivilegeLevel level = getNextLevel(current);
525 
526  if (hpstate.red || (tl == MaxTL - 1)) {
527  getREDVector(5, PC, NPC);
528  doREDFault(tc, tt);
529  // This changes the hpstate and pstate, so we need to make sure we
530  // save the old version on the trap stack in doREDFault.
531  enterREDState(tc);
532  } else if (tl == MaxTL) {
533  panic("Should go to error state here.. crap\n");
534  // Do error_state somehow?
535  // Probably inject a WDR fault using the interrupt mechanism.
536  // What should the PC and NPC be set to?
537  } else if (tl > MaxPTL && level == Privileged) {
538  // guest_watchdog fault
539  doNormalFault(tc, trapType(), true);
540  getHyperVector(tc, PC, NPC, 2);
541  } else if (level == Hyperprivileged ||
542  (level == Privileged && trapType() >= 384)) {
543  doNormalFault(tc, trapType(), true);
544  getHyperVector(tc, PC, NPC, trapType());
545  } else {
546  doNormalFault(tc, trapType(), false);
547  getPrivVector(tc, PC, NPC, trapType(), tl + 1);
548  }
549 
550  PCState pc;
551  pc.pc(PC);
552  pc.npc(NPC);
553  pc.nnpc(NPC + sizeof(MachInst));
554  pc.upc(0);
555  pc.nupc(1);
556  tc->pcState(pc);
557 }
558 
559 void
561 {
562  // For SPARC, when a system is first started, there is a power
563  // on reset Trap which sets the processor into the following state.
564  // Bits that aren't set aren't defined on startup.
565 
569 
570  PSTATE pstate = 0;
571  pstate.pef = 1;
572  pstate.priv = 1;
573  tc->setMiscRegNoEffect(MISCREG_PSTATE, pstate);
574 
575  // Turn on red and hpriv, set everything else to 0
576  HPSTATE hpstate = tc->readMiscRegNoEffect(MISCREG_HPSTATE);
577  hpstate.red = 1;
578  hpstate.hpriv = 1;
579  hpstate.ibe = 0;
580  hpstate.tlz = 0;
581  tc->setMiscRegNoEffect(MISCREG_HPSTATE, hpstate);
582 
583  // The tick register is unreadable by nonprivileged software
584  tc->setMiscRegNoEffect(MISCREG_TICK, 1ULL << 63);
585 
586  // Enter RED state. We do this last so that the actual state preserved in
587  // the trap stack is the state from before this fault.
588  enterREDState(tc);
589 
590  Addr PC, NPC;
591  getREDVector(trapType(), PC, NPC);
592 
593  PCState pc;
594  pc.pc(PC);
595  pc.npc(NPC);
596  pc.nnpc(NPC + sizeof(MachInst));
597  pc.upc(0);
598  pc.nupc(1);
599  tc->pcState(pc);
600 
601  // These registers are specified as "undefined" after a POR, and they
602  // should have reasonable values after the miscregfile is reset
603  /*
604  // Clear all the soft interrupt bits
605  softint = 0;
606  // disable timer compare interrupts, reset tick_cmpr
607  tc->setMiscRegNoEffect(MISCREG_
608  tick_cmprFields.int_dis = 1;
609  tick_cmprFields.tick_cmpr = 0; // Reset to 0 for pretty printing
610  stickFields.npt = 1; // The TICK register is unreadable by by !priv
611  stick_cmprFields.int_dis = 1; // disable timer compare interrupts
612  stick_cmprFields.tick_cmpr = 0; // Reset to 0 for pretty printing
613 
614  tt[tl] = _trapType;
615 
616  hintp = 0; // no interrupts pending
617  hstick_cmprFields.int_dis = 1; // disable timer compare interrupts
618  hstick_cmprFields.tick_cmpr = 0; // Reset to 0 for pretty printing
619  */
620 }
621 
622 void
624  const StaticInstPtr &inst)
625 {
626  if (FullSystem) {
627  SparcFaultBase::invoke(tc, inst);
628  return;
629  }
630 
631  Process *p = tc->getProcessPtr();
632  const EmulationPageTable::Entry *pte = p->pTable->lookup(vaddr);
633  panic_if(!pte, "Tried to execute unmapped address %#x.\n", vaddr);
634 
635  Addr alignedvaddr = p->pTable->pageAlign(vaddr);
636 
637  // Grab fields used during instruction translation to figure out
638  // which context to use.
639  uint64_t tlbdata = tc->readMiscRegNoEffect(MISCREG_TLB_DATA);
640 
641  // Inside a VM, a real address is the address that guest OS would
642  // interpret to be a physical address. To map to the physical address,
643  // it still needs to undergo a translation. The instruction
644  // translation code in the SPARC ITLB code assumes that the context is
645  // zero (kernel-level) if real addressing is being used.
646  bool is_real_address = !bits(tlbdata, 4);
647 
648  // The SPARC ITLB code assumes that traps are executed in context
649  // zero so we carry that assumption through here.
650  bool trapped = bits(tlbdata, 18, 16) > 0;
651 
652  // The primary context acts as a PASID. It allows the MMU to
653  // distinguish between virtual addresses that would alias to the
654  // same physical address (if two or more processes shared the same
655  // virtual address mapping).
656  int primary_context = bits(tlbdata, 47, 32);
657 
658  // The partition id distinguishes between virtualized environments.
659  int const partition_id = 0;
660 
661  // Given the assumptions in the translateInst code in the SPARC ITLB,
662  // the logic works out to the following for the context.
663  int context_id = (is_real_address || trapped) ? 0 : primary_context;
664 
665  TlbEntry entry(p->pTable->pid(), alignedvaddr, pte->paddr,
668 
669  // Insert the TLB entry.
670  // The entry specifying whether the address is "real" is set to
671  // false for syscall emulation mode regardless of whether the
672  // address is real in preceding code. Not sure sure that this is
673  // correct, but also not sure if it matters at all.
674  static_cast<MMU *>(tc->getMMUPtr())->insertItlbEntry(
675  alignedvaddr, partition_id, context_id,
676  false, entry.pte);
677 }
678 
679 void
681 {
682  if (FullSystem) {
683  SparcFaultBase::invoke(tc, inst);
684  return;
685  }
686 
687  Process *p = tc->getProcessPtr();
688  const EmulationPageTable::Entry *pte = p->pTable->lookup(vaddr);
689  if (!pte && p->fixupFault(vaddr))
690  pte = p->pTable->lookup(vaddr);
691  panic_if(!pte, "Tried to access unmapped address %#x.\n", vaddr);
692 
693  Addr alignedvaddr = p->pTable->pageAlign(vaddr);
694 
695  // Grab fields used during data translation to figure out
696  // which context to use.
697  uint64_t tlbdata = tc->readMiscRegNoEffect(MISCREG_TLB_DATA);
698 
699  // The primary context acts as a PASID. It allows the MMU to
700  // distinguish between virtual addresses that would alias to the
701  // same physical address (if two or more processes shared the same
702  // virtual address mapping). There's a secondary context used in the
703  // DTLB translation code, but it should __probably__ be zero for
704  // syscall emulation code. (The secondary context is used by Solaris
705  // to allow kernel privilege code to access user space code:
706  // [ISBN 0-13-022496-0]:PG199.)
707  int primary_context = bits(tlbdata, 47, 32);
708 
709  // "Hyper-Privileged Mode" is in use. There are three main modes of
710  // operation for Sparc: Hyper-Privileged Mode, Privileged Mode, and
711  // User Mode.
712  int hpriv = bits(tlbdata, 0);
713 
714  // Reset, Error and Debug state is in use. Something horrible has
715  // happened or the system is operating in Reset Mode.
716  int red = bits(tlbdata, 1);
717 
718  // Inside a VM, a real address is the address that guest OS would
719  // interpret to be a physical address. To map to the physical address,
720  // it still needs to undergo a translation. The instruction
721  // translation code in the SPARC ITLB code assumes that the context is
722  // zero (kernel-level) if real addressing is being used.
723  int is_real_address = !bits(tlbdata, 5);
724 
725  // Grab the address space identifier register from the thread context.
726  // XXX: Inspecting how setMiscReg and setMiscRegNoEffect behave for
727  // MISCREG_ASI causes me to think that the ASI register implementation
728  // might be bugged. The NoEffect variant changes the ASI register
729  // value in the architectural state while the normal variant changes
730  // the context field in the thread context's currently decoded request
731  // but does not directly affect the ASI register value in the
732  // architectural state. The ASI values and the context field in the
733  // request packet seem to have completely different uses.
734  RegVal reg_asi = tc->readMiscRegNoEffect(MISCREG_ASI);
735  ASI asi = static_cast<ASI>(reg_asi);
736 
737  // The SPARC DTLB code assumes that traps are executed in context
738  // zero if the asi value is ASI_IMPLICIT (which is 0x0). There's also
739  // an assumption that the nucleus address space is being used, but
740  // the context is the relevant issue since we need to pass it to TLB.
741  bool trapped = bits(tlbdata, 18, 16) > 0;
742 
743  // Given the assumptions in the translateData code in the SPARC DTLB,
744  // the logic works out to the following for the context.
745  int context_id = ((!hpriv && !red && is_real_address) ||
746  asiIsReal(asi) ||
747  (trapped && asi == ASI_IMPLICIT))
748  ? 0 : primary_context;
749 
750  // The partition id distinguishes between virtualized environments.
751  int const partition_id = 0;
752 
753  TlbEntry entry(p->pTable->pid(), alignedvaddr, pte->paddr,
756 
757  // Insert the TLB entry.
758  // The entry specifying whether the address is "real" is set to
759  // false for syscall emulation mode regardless of whether the
760  // address is real in preceding code. Not sure sure that this is
761  // correct, but also not sure if it matters at all.
762  static_cast<MMU *>(tc->getMMUPtr())->insertDtlbEntry(
763  alignedvaddr, partition_id, context_id,
764  false, entry.pte);
765 }
766 
767 void
769 {
770  if (FullSystem) {
771  SparcFaultBase::invoke(tc, inst);
772  return;
773  }
774 
775  doNormalFault(tc, trapType(), false);
776 
777  Process *p = tc->getProcessPtr();
778 
779  SparcProcess *sp = dynamic_cast<SparcProcess *>(p);
780  assert(sp);
781 
782  // Then adjust the PC and NPC
783  tc->pcState(sp->readSpillStart());
784 }
785 
786 void
788 {
789  if (FullSystem) {
790  SparcFaultBase::invoke(tc, inst);
791  return;
792  }
793 
794  doNormalFault(tc, trapType(), false);
795 
796  Process *p = tc->getProcessPtr();
797 
798  SparcProcess *sp = dynamic_cast<SparcProcess *>(p);
799  assert(sp);
800 
801  // Then adjust the PC and NPC
802  tc->pcState(sp->readFillStart());
803 }
804 
805 void
807 {
808  if (FullSystem) {
809  SparcFaultBase::invoke(tc, inst);
810  return;
811  }
812 
813  // In SE, this mechanism is how the process requests a service from
814  // the operating system. We'll get the process object from the thread
815  // context and let it service the request.
816 
817  Process *p = tc->getProcessPtr();
818 
819  [[maybe_unused]] SparcProcess *sp = dynamic_cast<SparcProcess *>(p);
820  assert(sp);
821 
822  auto *workload = dynamic_cast<SEWorkload *>(tc->getSystemPtr()->workload);
823  workload->handleTrap(tc, _n);
824 
825  // We need to explicitly advance the pc, since that's not done for us
826  // on a faulting instruction
827  PCState pc = tc->pcState().as<PCState>();
828  pc.advance();
829  tc->pcState(pc);
830 }
831 
832 } // namespace SparcISA
833 } // namespace gem5
gem5::SparcISA::EnumeratedFault< SpillNNormal >::trapType
TrapType trapType()
Definition: faults.hh:185
gem5::EmulationPageTable::Entry::flags
uint64_t flags
Definition: page_table.hh:59
gem5::X86ISA::level
Bitfield< 20 > level
Definition: intmessage.hh:51
gem5::SparcISA::MISCREG_ASI
@ MISCREG_ASI
Ancillary State Registers.
Definition: misc.hh:45
gem5::SparcISA::SparcFaultBase::Hyperprivileged
@ Hyperprivileged
Definition: faults.hh:56
gem5::ThreadContext::getSystemPtr
virtual System * getSystemPtr()=0
gem5::SparcISA::MMU
Definition: mmu.hh:52
gem5::SparcISA::SparcFaultBase::trapType
virtual TrapType trapType()=0
gem5::RegVal
uint64_t RegVal
Definition: types.hh:173
process.hh
gem5::EmulationPageTable::Uncacheable
@ Uncacheable
Definition: page_table.hh:99
gem5::SparcISA::FastDataAccessMMUMiss::invoke
void invoke(ThreadContext *tc, const StaticInstPtr &inst=nullStaticInstPtr)
Definition: faults.cc:680
gem5::SparcISA::MISCREG_TT
@ MISCREG_TT
Definition: misc.hh:62
gem5::SparcISA::SparcFaultBase::PrivilegeLevel
PrivilegeLevel
Definition: faults.hh:52
gem5::SparcISA::INTREG_CANSAVE
@ INTREG_CANSAVE
Definition: int.hh:60
gem5::SparcISA::TrapInstruction::invoke
void invoke(ThreadContext *tc, const StaticInstPtr &inst=nullStaticInstPtr)
Definition: faults.cc:806
gem5::PCStateBase::as
Target & as()
Definition: pcstate.hh:72
gem5::ThreadContext::getMMUPtr
virtual BaseMMU * getMMUPtr()=0
gem5::ThreadContext::pcState
virtual const PCStateBase & pcState() const =0
gem5::SparcISA::PowerOnReset::invoke
void invoke(ThreadContext *tc, const StaticInstPtr &inst=nullStaticInstPtr)
Definition: faults.cc:560
gem5::replaceBits
constexpr void replaceBits(T &val, unsigned first, unsigned last, B bit_val)
A convenience function to replace bits first to last of val with bit_val in place.
Definition: bitfield.hh:197
gem5::SparcISA::SparcFaultBase::getNextLevel
virtual PrivilegeLevel getNextLevel(PrivilegeLevel current)=0
gem5::System::workload
Workload * workload
OS kernel.
Definition: system.hh:330
gem5::SparcISA::MachInst
uint32_t MachInst
Definition: types.hh:41
gem5::SparcISA::MaxTL
const int MaxTL
Definition: sparc_traits.hh:39
gem5::EmulationPageTable::ReadOnly
@ ReadOnly
Definition: page_table.hh:100
gem5::SparcISA::MISCREG_HPSTATE
@ MISCREG_HPSTATE
Hyper privileged registers.
Definition: misc.hh:77
gem5::SparcISA::doNormalFault
void doNormalFault(ThreadContext *tc, TrapType tt, bool gotoHpriv)
This sets everything up for a normal trap except for actually jumping to the handler.
Definition: faults.cc:382
gem5::SparcISA::FastInstructionAccessMMUMiss::vaddr
Addr vaddr
Definition: faults.hh:209
gem5::SparcISA::SparcFaultBase::Privileged
@ Privileged
Definition: faults.hh:55
gem5::RefCountingPtr< StaticInst >
gem5::mask
constexpr uint64_t mask(unsigned nbits)
Generate a 64-bit mask of 'nbits' 1s, right justified.
Definition: bitfield.hh:63
gem5::SparcProcess
Definition: process.hh:44
gem5::SparcISA::INTREG_CCR
@ INTREG_CCR
Definition: int.hh:59
gem5::SparcISA::getPrivVector
void getPrivVector(ThreadContext *tc, Addr &PC, Addr &NPC, RegVal TT, RegVal TL)
Definition: faults.cc:490
gem5::SparcISA::getHyperVector
void getHyperVector(ThreadContext *tc, Addr &PC, Addr &NPC, RegVal TT)
Definition: faults.cc:482
gem5::X86ISA::H
Bitfield< 15, 8 > H
Definition: int.hh:57
bitfield.hh
gem5::ThreadContext
ThreadContext is the external interface to all thread state for anything outside of the CPU.
Definition: thread_context.hh:94
faults.hh
gem5::SparcISA::SpillNNormal::invoke
void invoke(ThreadContext *tc, const StaticInstPtr &inst=nullStaticInstPtr)
Definition: faults.cc:768
gem5::SparcISA::MISCREG_TL
@ MISCREG_TL
Definition: misc.hh:66
gem5::X86ISA::SH
SignedBitfield< 15, 8 > SH
Definition: int.hh:58
gem5::MipsISA::p
Bitfield< 0 > p
Definition: pra_constants.hh:326
gem5::SparcISA::getREDVector
void getREDVector(RegVal TT, Addr &PC, Addr &NPC)
Definition: faults.cc:473
gem5::SparcISA::MISCREG_TSTATE
@ MISCREG_TSTATE
Definition: misc.hh:61
process.hh
gem5::SparcISA::TrapType
uint32_t TrapType
Definition: faults.hh:44
gem5::bits
constexpr T bits(T val, unsigned first, unsigned last)
Extract the bitfield from position 'first' to 'last' (inclusive) from 'val' and right justify it.
Definition: bitfield.hh:76
compiler.hh
gem5::SparcISA::SEWorkload
Definition: se_workload.hh:47
gem5::ThreadContext::readMiscRegNoEffect
virtual RegVal readMiscRegNoEffect(RegIndex misc_reg) const =0
gem5::SparcISA::SparcFault< PowerOnReset >::trapType
TrapType trapType()
Definition: faults.hh:88
gem5::SparcISA::FastInstructionAccessMMUMiss::invoke
void invoke(ThreadContext *tc, const StaticInstPtr &inst=nullStaticInstPtr)
Definition: faults.cc:623
mmu.hh
types.hh
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::SparcISA::MaxPTL
const int MaxPTL
Definition: sparc_traits.hh:38
gem5::ThreadContext::readIntReg
virtual RegVal readIntReg(RegIndex reg_idx) const =0
gem5::SparcISA::doREDFault
void doREDFault(ThreadContext *tc, TrapType tt)
This sets everything up for a RED state trap except for actually jumping to the handler.
Definition: faults.cc:303
gem5::SparcISA::red
Bitfield< 5 > red
Definition: misc.hh:122
gem5::FaultBase::invoke
virtual void invoke(ThreadContext *tc, const StaticInstPtr &inst=nullStaticInstPtr)
Definition: faults.cc:58
full_system.hh
gem5::SparcISA::ASI_IMPLICIT
@ ASI_IMPLICIT
Definition: asi.hh:40
gem5::Process
Definition: process.hh:68
gem5::SparcISA::priv
Bitfield< 2 > priv
Definition: misc.hh:129
gem5::ThreadContext::getProcessPtr
virtual Process * getProcessPtr()=0
gem5::FullSystem
bool FullSystem
The FullSystem variable can be used to determine the current mode of simulation.
Definition: root.cc:220
gem5::MipsISA::FaultVals
MipsFaultBase::FaultVals FaultVals
Definition: faults.cc:46
gem5::EmulationPageTable::Entry::paddr
Addr paddr
Definition: page_table.hh:58
panic_if
#define panic_if(cond,...)
Conditional panic macro that checks the supplied condition and only panics if the condition is true a...
Definition: logging.hh:204
gem5::SparcISA::NWindows
const int NWindows
Definition: sparc_traits.hh:44
gem5::SparcISA::MISCREG_HTBA
@ MISCREG_HTBA
Definition: misc.hh:80
gem5::SparcISA::MISCREG_TNPC
@ MISCREG_TNPC
Definition: misc.hh:60
gem5::SparcISA::FillNNormal::invoke
void invoke(ThreadContext *tc, const StaticInstPtr &inst=nullStaticInstPtr)
Definition: faults.cc:787
gem5::SparcISA::MISCREG_TICK
@ MISCREG_TICK
Definition: misc.hh:46
gem5::SparcISA::MISCREG_TBA
@ MISCREG_TBA
Definition: misc.hh:64
base.hh
gem5::SparcISA::asiIsReal
bool asiIsReal(ASI asi)
Definition: asi.cc:142
gem5::SparcISA::SparcFaultBase::User
@ User
Definition: faults.hh:54
gem5::ThreadContext::setMiscReg
virtual void setMiscReg(RegIndex misc_reg, RegVal val)=0
gem5::SparcISA::MaxGL
const int MaxGL
Definition: sparc_traits.hh:40
gem5::GenericISA::DelaySlotUPCState
Definition: pcstate.hh:530
gem5::MipsISA::tl
Bitfield< 23, 20 > tl
Definition: pra_constants.hh:254
gem5::MipsISA::pc
Bitfield< 4 > pc
Definition: pra_constants.hh:243
gem5::SparcISA::MISCREG_PSTATE
@ MISCREG_PSTATE
Definition: misc.hh:65
se_workload.hh
gem5::SparcISA::ASI
ASI
Definition: asi.hh:38
gem5::SparcISA::FastDataAccessMMUMiss::vaddr
Addr vaddr
Definition: faults.hh:222
gem5::SparcISA::MISCREG_TLB_DATA
@ MISCREG_TLB_DATA
Definition: misc.hh:115
trace.hh
gem5::SparcISA::SEWorkload::handleTrap
virtual void handleTrap(ThreadContext *tc, int trapNum)
Definition: se_workload.cc:55
gem5::SparcISA::MISCREG_HTSTATE
@ MISCREG_HTSTATE
Definition: misc.hh:78
gem5::SparcISA::MISCREG_CWP
@ MISCREG_CWP
Definition: misc.hh:68
gem5::SparcISA::SparcFault::vals
static FaultVals vals
Definition: faults.hh:85
gem5::ArmISA::sp
Bitfield< 0 > sp
Definition: misc_types.hh:75
gem5::SparcISA::TlbEntry::pte
PageTableEntry pte
Definition: pagetable.hh:261
gem5::SparcISA::SparcFaultBase::invoke
void invoke(ThreadContext *tc, const StaticInstPtr &inst=nullStaticInstPtr)
Definition: faults.cc:500
gem5::SparcISA::MISCREG_GL
@ MISCREG_GL
Definition: misc.hh:74
gem5::SparcISA::hpriv
Bitfield< 2 > hpriv
Definition: misc.hh:121
gem5::SparcISA::MISCREG_TPC
@ MISCREG_TPC
Privilged Registers.
Definition: misc.hh:59
page_table.hh
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: tlb.cc:60
gem5::EmulationPageTable::Entry
Definition: page_table.hh:56
gem5::SparcISA::enterREDState
void enterREDState(ThreadContext *tc)
This causes the thread context to enter RED state.
Definition: faults.cc:282
sparc_traits.hh
thread_context.hh
gem5::SparcISA::EnumeratedFault< TrapInstruction >::_n
uint32_t _n
Definition: faults.hh:182
gem5::SparcISA::MaxPGL
const int MaxPGL
Definition: sparc_traits.hh:41
gem5::SparcISA::TlbEntry
Definition: pagetable.hh:225
panic
#define panic(...)
This implements a cprintf based panic() function.
Definition: logging.hh:178
gem5::ThreadContext::setMiscRegNoEffect
virtual void setMiscRegNoEffect(RegIndex misc_reg, RegVal val)=0

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