se_workload.hh

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#ifndef __ARCH_SPARC_SE_WORKLOAD_HH__
#define __ARCH_SPARC_SE_WORKLOAD_HH__
 
#include <vector>
 
#include "arch/sparc/regs/int.hh"
#include "arch/sparc/regs/misc.hh"
#include "arch/sparc/remote_gdb.hh"
#include "base/loader/object_file.hh"
#include "cpu/thread_context.hh"
#include "sim/se_workload.hh"
#include "sim/syscall_abi.hh"
 
namespace gem5
{
 
namespace SparcISA
{
 
class SEWorkload : public gem5::SEWorkload
{
  public:
    using gem5::SEWorkload::SEWorkload;
 
    void
    setSystem(System *sys) override
    {
        gem5::SEWorkload::setSystem(sys);
        gdb = BaseRemoteGDB::build<RemoteGDB>(system);
    }
 
    virtual void handleTrap(ThreadContext *tc, int trapNum);
    virtual void flushWindows(ThreadContext *tc);
 
    bool is64(ThreadContext *tc);
 
    struct BaseSyscallABI
    {
        static const std::vector<int> ArgumentRegs;
    };
 
    struct SyscallABI32 : public GenericSyscallABI32,
                          public BaseSyscallABI
    {};
 
    struct SyscallABI64 : public GenericSyscallABI64,
                          public BaseSyscallABI
    {};
};
 
} // namespace SparcISA
 
GEM5_DEPRECATED_NAMESPACE(GuestABI, guest_abi);
namespace guest_abi
{
 
template <typename ABI>
struct Result<ABI, SyscallReturn,
    typename std::enable_if_t<std::is_base_of_v<
        SparcISA::SEWorkload::BaseSyscallABI, ABI>>>
{
    static void
    store(ThreadContext *tc, const SyscallReturn &ret)
    {
        // check for error condition.  SPARC syscall convention is to
        // indicate success/failure in reg the carry bit of the ccr
        // and put the return value itself in the standard return value reg.
        SparcISA::PSTATE pstate =
            tc->readMiscRegNoEffect(SparcISA::MISCREG_PSTATE);
        SparcISA::CCR ccr = tc->readIntReg(SparcISA::INTREG_CCR);
        RegVal val;
        if (ret.successful()) {
            ccr.xcc.c = ccr.icc.c = 0;
            val = ret.returnValue();
        } else {
            ccr.xcc.c = ccr.icc.c = 1;
            val = ret.errnoValue();
        }
        tc->setIntReg(SparcISA::INTREG_CCR, ccr);
        if (pstate.am)
            val = bits(val, 31, 0);
        tc->setIntReg(SparcISA::ReturnValueReg, val);
        if (ret.count() == 2)
            tc->setIntReg(SparcISA::SyscallPseudoReturnReg, ret.value2());
    }
};
 
template <typename Arg>
struct Argument<SparcISA::SEWorkload::SyscallABI32, Arg,
    typename std::enable_if_t<
        std::is_integral_v<Arg> &&
        SparcISA::SEWorkload::SyscallABI32::IsWideV<Arg>>>
{
    using ABI = SparcISA::SEWorkload::SyscallABI32;
 
    static Arg
    get(ThreadContext *tc, typename ABI::State &state)
    {
        panic_if(state + 1 >= ABI::ArgumentRegs.size(),
                "Ran out of syscall argument registers.");
        auto high = ABI::ArgumentRegs[state++];
        auto low = ABI::ArgumentRegs[state++];
        return (Arg)ABI::mergeRegs(tc, low, high);
    }
};
 
} // namespace guest_abi
} // namespace gem5
 
#endif // __ARCH_SPARC_SE_WORKLOAD_HH__