gem5  v21.1.0.2
mem.cc
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40 
41 #include "arch/arm/insts/mem.hh"
42 
43 #include "base/loader/symtab.hh"
44 
45 namespace gem5
46 {
47 
48 namespace ArmISA
49 {
50 
51 void
52 MemoryReg::printOffset(std::ostream &os) const
53 {
54  if (!add)
55  os << "-";
57  if (shiftType != LSL || shiftAmt != 0) {
58  switch (shiftType) {
59  case LSL:
60  ccprintf(os, " LSL #%d", shiftAmt);
61  break;
62  case LSR:
63  ccprintf(os, " LSR #%d", (shiftAmt == 0) ? 32 : shiftAmt);
64  break;
65  case ASR:
66  ccprintf(os, " ASR #%d", (shiftAmt == 0) ? 32 : shiftAmt);
67  break;
68  case ROR:
69  if (shiftAmt == 0) {
70  ccprintf(os, " RRX");
71  } else {
72  ccprintf(os, " ROR #%d", shiftAmt);
73  }
74  break;
75  }
76  }
77 }
78 
79 std::string
81 {
82  std::stringstream ss;
83  switch (mode) {
84  case DecrementAfter:
85  printMnemonic(ss, "da");
86  break;
87  case DecrementBefore:
88  printMnemonic(ss, "db");
89  break;
90  case IncrementAfter:
91  printMnemonic(ss, "ia");
92  break;
93  case IncrementBefore:
94  printMnemonic(ss, "ib");
95  break;
96  }
98  if (wb) {
99  ss << "!";
100  }
101  return ss.str();
102 }
103 
104 std::string
106 {
107  std::stringstream ss;
108  switch (mode) {
109  case DecrementAfter:
110  printMnemonic(ss, "da");
111  break;
112  case DecrementBefore:
113  printMnemonic(ss, "db");
114  break;
115  case IncrementAfter:
116  printMnemonic(ss, "ia");
117  break;
118  case IncrementBefore:
119  printMnemonic(ss, "ib");
120  break;
121  }
122  printIntReg(ss, INTREG_SP);
123  if (wb) {
124  ss << "!";
125  }
126  ss << ", #";
127  switch (regMode) {
128  case MODE_USER:
129  ss << "user";
130  break;
131  case MODE_FIQ:
132  ss << "fiq";
133  break;
134  case MODE_IRQ:
135  ss << "irq";
136  break;
137  case MODE_SVC:
138  ss << "supervisor";
139  break;
140  case MODE_MON:
141  ss << "monitor";
142  break;
143  case MODE_ABORT:
144  ss << "abort";
145  break;
146  case MODE_HYP:
147  ss << "hyp";
148  break;
149  case MODE_UNDEFINED:
150  ss << "undefined";
151  break;
152  case MODE_SYSTEM:
153  ss << "system";
154  break;
155  default:
156  ss << "unrecognized";
157  break;
158  }
159  return ss.str();
160 }
161 
162 void
163 Memory::printInst(std::ostream &os, AddrMode addrMode) const
164 {
165  printMnemonic(os);
166  printDest(os);
167  os << ", [";
168  printIntReg(os, base);
169  if (addrMode != AddrMd_PostIndex) {
170  os << ", ";
171  printOffset(os);
172  os << "]";
173  if (addrMode == AddrMd_PreIndex) {
174  os << "!";
175  }
176  } else {
177  os << "] ";
178  printOffset(os);
179 
180  }
181 }
182 
183 } // namespace ArmISA
184 } // namespace gem5
gem5::ArmISA::RfeOp::wb
bool wb
Definition: mem.hh:86
gem5::ArmISA::SrsOp::IncrementBefore
@ IncrementBefore
Definition: mem.hh:127
gem5::ArmISA::MODE_SVC
@ MODE_SVC
Definition: types.hh:284
gem5::ArmISA::MODE_MON
@ MODE_MON
Definition: types.hh:285
gem5::ArmISA::MODE_FIQ
@ MODE_FIQ
Definition: types.hh:282
gem5::ArmISA::SrsOp::regMode
uint32_t regMode
Definition: mem.hh:130
gem5::ArmISA::MemoryReg::shiftType
ArmShiftType shiftType
Definition: mem.hh:301
gem5::ArmISA::MODE_UNDEFINED
@ MODE_UNDEFINED
Definition: types.hh:288
gem5::ArmISA::MODE_IRQ
@ MODE_IRQ
Definition: types.hh:283
gem5::ArmISA::ArmStaticInst::printMnemonic
void printMnemonic(std::ostream &os, const std::string &suffix="", bool withPred=true, bool withCond64=false, ConditionCode cond64=COND_UC) const
Definition: static_inst.cc:377
gem5::ArmISA::RfeOp::IncrementBefore
@ IncrementBefore
Definition: mem.hh:81
gem5::ArmISA::RfeOp::DecrementBefore
@ DecrementBefore
Definition: mem.hh:79
gem5::ArmISA::Memory::printInst
void printInst(std::ostream &os, AddrMode addrMode) const
Definition: mem.cc:163
gem5::loader::SymbolTable
Definition: symtab.hh:65
gem5::ArmISA::SrsOp::DecrementBefore
@ DecrementBefore
Definition: mem.hh:125
gem5::ccprintf
void ccprintf(cp::Print &print)
Definition: cprintf.hh:130
gem5::ArmISA::MemoryReg::printOffset
void printOffset(std::ostream &os) const
Definition: mem.cc:52
gem5::ArmISA::RfeOp::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: mem.cc:80
gem5::ArmISA::MemoryReg::index
IntRegIndex index
Definition: mem.hh:302
gem5::ArmISA::MODE_HYP
@ MODE_HYP
Definition: types.hh:287
gem5::ArmISA::RfeOp::IncrementAfter
@ IncrementAfter
Definition: mem.hh:80
gem5::ArmISA::SrsOp::wb
bool wb
Definition: mem.hh:132
gem5::ArmISA::Memory::add
bool add
Definition: mem.hh:174
gem5::ArmISA::Memory::AddrMd_PostIndex
@ AddrMd_PostIndex
Definition: mem.hh:167
gem5::ArmISA::Memory::base
IntRegIndex base
Definition: mem.hh:173
gem5::ArmISA::RfeOp::base
IntRegIndex base
Definition: mem.hh:84
gem5::ArmISA::SrsOp::DecrementAfter
@ DecrementAfter
Definition: mem.hh:124
gem5::ArmISA::Memory::printOffset
virtual void printOffset(std::ostream &os) const
Definition: mem.hh:199
gem5::ArmISA::MODE_USER
@ MODE_USER
Definition: types.hh:281
gem5::ArmISA::Memory::printDest
virtual void printDest(std::ostream &os) const
Definition: mem.hh:203
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::ArmISA::Memory::AddrMode
AddrMode
Definition: mem.hh:163
gem5::ArmISA::Memory::AddrMd_PreIndex
@ AddrMd_PreIndex
Definition: mem.hh:166
gem5::ArmISA::SrsOp::IncrementAfter
@ IncrementAfter
Definition: mem.hh:126
gem5::X86ISA::os
Bitfield< 17 > os
Definition: misc.hh:809
gem5::ArmISA::ss
Bitfield< 21 > ss
Definition: misc_types.hh:59
gem5::ArmISA::MemoryReg::shiftAmt
int32_t shiftAmt
Definition: mem.hh:300
gem5::MipsISA::pc
Bitfield< 4 > pc
Definition: pra_constants.hh:243
gem5::ArmISA::RfeOp::DecrementAfter
@ DecrementAfter
Definition: mem.hh:78
gem5::ArmISA::MODE_SYSTEM
@ MODE_SYSTEM
Definition: types.hh:289
mem.hh
symtab.hh
gem5::ArmISA::SrsOp::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: mem.cc:105
gem5::ArmISA::MODE_ABORT
@ MODE_ABORT
Definition: types.hh:286
gem5::ArmISA::ArmStaticInst::printIntReg
void printIntReg(std::ostream &os, RegIndex reg_idx, uint8_t opWidth=0) const
Print a register name for disassembly given the unique dependence tag number (FP or int).
Definition: static_inst.cc:299
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40
gem5::ArmISA::SrsOp::mode
AddrMode mode
Definition: mem.hh:131
gem5::ArmISA::RfeOp::mode
AddrMode mode
Definition: mem.hh:85

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