gem5  v21.1.0.2
mem.hh
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40 
41 #ifndef __ARCH_ARM_MEM_HH__
42 #define __ARCH_ARM_MEM_HH__
43 
45 
46 namespace gem5
47 {
48 
49 namespace ArmISA
50 {
51 
52 class MightBeMicro : public PredOp
53 {
54  protected:
55  MightBeMicro(const char *mnem, ExtMachInst _machInst, OpClass __opClass)
56  : PredOp(mnem, _machInst, __opClass)
57  {}
58 
59  void
60  advancePC(PCState &pcState) const override
61  {
62  if (flags[IsLastMicroop]) {
63  pcState.uEnd();
64  } else if (flags[IsMicroop]) {
65  pcState.uAdvance();
66  } else {
67  pcState.advance();
68  }
69  }
70 };
71 
72 // The address is a base register plus an immediate.
73 class RfeOp : public MightBeMicro
74 {
75  public:
76  enum AddrMode
77  {
82  };
83  protected:
84  IntRegIndex base;
86  bool wb;
87  IntRegIndex ura, urb, urc;
88  static const unsigned numMicroops = 3;
89 
91 
92  RfeOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
93  IntRegIndex _base, AddrMode _mode, bool _wb)
94  : MightBeMicro(mnem, _machInst, __opClass),
95  base(_base), mode(_mode), wb(_wb),
96  ura(INTREG_UREG0), urb(INTREG_UREG1),
97  urc(INTREG_UREG2),
98  uops(NULL)
99  {}
100 
101  virtual
103  {
104  delete [] uops;
105  }
106 
108  fetchMicroop(MicroPC microPC) const override
109  {
110  assert(uops != NULL && microPC < numMicroops);
111  return uops[microPC];
112  }
113 
114  std::string generateDisassembly(
115  Addr pc, const loader::SymbolTable *symtab) const override;
116 };
117 
118 // The address is a base register plus an immediate.
119 class SrsOp : public MightBeMicro
120 {
121  public:
122  enum AddrMode
123  {
128  };
129  protected:
130  uint32_t regMode;
132  bool wb;
133  static const unsigned numMicroops = 2;
134 
136 
137  SrsOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
138  uint32_t _regMode, AddrMode _mode, bool _wb)
139  : MightBeMicro(mnem, _machInst, __opClass),
140  regMode(_regMode), mode(_mode), wb(_wb), uops(NULL)
141  {}
142 
143  virtual
145  {
146  delete [] uops;
147  }
148 
150  fetchMicroop(MicroPC microPC) const override
151  {
152  assert(uops != NULL && microPC < numMicroops);
153  return uops[microPC];
154  }
155 
156  std::string generateDisassembly(
157  Addr pc, const loader::SymbolTable *symtab) const override;
158 };
159 
160 class Memory : public MightBeMicro
161 {
162  public:
163  enum AddrMode
164  {
168  };
169 
170  protected:
171 
172  IntRegIndex dest;
173  IntRegIndex base;
174  bool add;
175  static const unsigned numMicroops = 3;
176 
178 
179  Memory(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
180  IntRegIndex _dest, IntRegIndex _base, bool _add)
181  : MightBeMicro(mnem, _machInst, __opClass),
182  dest(_dest), base(_base), add(_add), uops(NULL)
183  {}
184 
185  virtual
187  {
188  delete [] uops;
189  }
190 
192  fetchMicroop(MicroPC microPC) const override
193  {
194  assert(uops != NULL && microPC < numMicroops);
195  return uops[microPC];
196  }
197 
198  virtual void
199  printOffset(std::ostream &os) const
200  {}
201 
202  virtual void
203  printDest(std::ostream &os) const
204  {
205  printIntReg(os, dest);
206  }
207 
208  void printInst(std::ostream &os, AddrMode addrMode) const;
209 };
210 
211 // The address is a base register plus an immediate.
212 class MemoryImm : public Memory
213 {
214  protected:
215  int32_t imm;
216 
217  MemoryImm(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
218  IntRegIndex _dest, IntRegIndex _base, bool _add, int32_t _imm)
219  : Memory(mnem, _machInst, __opClass, _dest, _base, _add), imm(_imm)
220  {}
221 
222  void
223  printOffset(std::ostream &os) const
224  {
225  int32_t pImm = imm;
226  if (!add)
227  pImm = -pImm;
228  ccprintf(os, "#%d", pImm);
229  }
230 };
231 
232 class MemoryExImm : public MemoryImm
233 {
234  protected:
235  IntRegIndex result;
236 
237  MemoryExImm(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
238  IntRegIndex _result, IntRegIndex _dest, IntRegIndex _base,
239  bool _add, int32_t _imm)
240  : MemoryImm(mnem, _machInst, __opClass, _dest, _base, _add, _imm),
241  result(_result)
242  {}
243 
244  void
245  printDest(std::ostream &os) const
246  {
248  os << ", ";
250  }
251 };
252 
253 // The address is a base register plus an immediate.
254 class MemoryDImm : public MemoryImm
255 {
256  protected:
257  IntRegIndex dest2;
258 
259  MemoryDImm(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
260  IntRegIndex _dest, IntRegIndex _dest2,
261  IntRegIndex _base, bool _add, int32_t _imm)
262  : MemoryImm(mnem, _machInst, __opClass, _dest, _base, _add, _imm),
263  dest2(_dest2)
264  {}
265 
266  void
267  printDest(std::ostream &os) const
268  {
270  os << ", ";
271  printIntReg(os, dest2);
272  }
273 };
274 
275 class MemoryExDImm : public MemoryDImm
276 {
277  protected:
278  IntRegIndex result;
279 
280  MemoryExDImm(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
281  IntRegIndex _result, IntRegIndex _dest, IntRegIndex _dest2,
282  IntRegIndex _base, bool _add, int32_t _imm)
283  : MemoryDImm(mnem, _machInst, __opClass, _dest, _dest2,
284  _base, _add, _imm), result(_result)
285  {}
286 
287  void
288  printDest(std::ostream &os) const
289  {
291  os << ", ";
293  }
294 };
295 
296 // The address is a shifted register plus an immediate
297 class MemoryReg : public Memory
298 {
299  protected:
300  int32_t shiftAmt;
301  ArmShiftType shiftType;
302  IntRegIndex index;
303 
304  MemoryReg(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
305  IntRegIndex _dest, IntRegIndex _base, bool _add,
306  int32_t _shiftAmt, ArmShiftType _shiftType,
307  IntRegIndex _index)
308  : Memory(mnem, _machInst, __opClass, _dest, _base, _add),
309  shiftAmt(_shiftAmt), shiftType(_shiftType), index(_index)
310  {}
311 
312  void printOffset(std::ostream &os) const;
313 };
314 
315 class MemoryDReg : public MemoryReg
316 {
317  protected:
318  IntRegIndex dest2;
319 
320  MemoryDReg(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
321  IntRegIndex _dest, IntRegIndex _dest2,
322  IntRegIndex _base, bool _add,
323  int32_t _shiftAmt, ArmShiftType _shiftType,
324  IntRegIndex _index)
325  : MemoryReg(mnem, _machInst, __opClass, _dest, _base, _add,
326  _shiftAmt, _shiftType, _index),
327  dest2(_dest2)
328  {}
329 
330  void
331  printDest(std::ostream &os) const
332  {
334  os << ", ";
335  printIntReg(os, dest2);
336  }
337 };
338 
339 template<class Base>
340 class MemoryOffset : public Base
341 {
342  protected:
343  MemoryOffset(const char *mnem, ExtMachInst _machInst,
344  OpClass __opClass, IntRegIndex _dest, IntRegIndex _base,
345  bool _add, int32_t _imm)
346  : Base(mnem, _machInst, __opClass, _dest, _base, _add, _imm)
347  {}
348 
349  MemoryOffset(const char *mnem, ExtMachInst _machInst,
350  OpClass __opClass, IntRegIndex _dest, IntRegIndex _base,
351  bool _add, int32_t _shiftAmt, ArmShiftType _shiftType,
352  IntRegIndex _index)
353  : Base(mnem, _machInst, __opClass, _dest, _base, _add,
354  _shiftAmt, _shiftType, _index)
355  {}
356 
357  MemoryOffset(const char *mnem, ExtMachInst _machInst,
358  OpClass __opClass, IntRegIndex _dest, IntRegIndex _dest2,
359  IntRegIndex _base, bool _add, int32_t _imm)
360  : Base(mnem, _machInst, __opClass, _dest, _dest2, _base, _add, _imm)
361  {}
362 
363  MemoryOffset(const char *mnem, ExtMachInst _machInst,
364  OpClass __opClass, IntRegIndex _result,
365  IntRegIndex _dest, IntRegIndex _dest2,
366  IntRegIndex _base, bool _add, int32_t _imm)
367  : Base(mnem, _machInst, __opClass, _result,
368  _dest, _dest2, _base, _add, _imm)
369  {}
370 
371  MemoryOffset(const char *mnem, ExtMachInst _machInst,
372  OpClass __opClass, IntRegIndex _dest, IntRegIndex _dest2,
373  IntRegIndex _base, bool _add,
374  int32_t _shiftAmt, ArmShiftType _shiftType,
375  IntRegIndex _index)
376  : Base(mnem, _machInst, __opClass, _dest, _dest2, _base, _add,
377  _shiftAmt, _shiftType, _index)
378  {}
379 
380  std::string
382  const loader::SymbolTable *symtab) const override
383  {
384  std::stringstream ss;
385  this->printInst(ss, Memory::AddrMd_Offset);
386  return ss.str();
387  }
388 };
389 
390 template<class Base>
391 class MemoryPreIndex : public Base
392 {
393  protected:
394  MemoryPreIndex(const char *mnem, ExtMachInst _machInst,
395  OpClass __opClass, IntRegIndex _dest, IntRegIndex _base,
396  bool _add, int32_t _imm)
397  : Base(mnem, _machInst, __opClass, _dest, _base, _add, _imm)
398  {}
399 
400  MemoryPreIndex(const char *mnem, ExtMachInst _machInst,
401  OpClass __opClass, IntRegIndex _dest, IntRegIndex _base,
402  bool _add, int32_t _shiftAmt, ArmShiftType _shiftType,
403  IntRegIndex _index)
404  : Base(mnem, _machInst, __opClass, _dest, _base, _add,
405  _shiftAmt, _shiftType, _index)
406  {}
407 
408  MemoryPreIndex(const char *mnem, ExtMachInst _machInst,
409  OpClass __opClass, IntRegIndex _dest, IntRegIndex _dest2,
410  IntRegIndex _base, bool _add, int32_t _imm)
411  : Base(mnem, _machInst, __opClass, _dest, _dest2, _base, _add, _imm)
412  {}
413 
414  MemoryPreIndex(const char *mnem, ExtMachInst _machInst,
415  OpClass __opClass, IntRegIndex _result,
416  IntRegIndex _dest, IntRegIndex _dest2,
417  IntRegIndex _base, bool _add, int32_t _imm)
418  : Base(mnem, _machInst, __opClass, _result,
419  _dest, _dest2, _base, _add, _imm)
420  {}
421 
422  MemoryPreIndex(const char *mnem, ExtMachInst _machInst,
423  OpClass __opClass, IntRegIndex _dest, IntRegIndex _dest2,
424  IntRegIndex _base, bool _add,
425  int32_t _shiftAmt, ArmShiftType _shiftType,
426  IntRegIndex _index)
427  : Base(mnem, _machInst, __opClass, _dest, _dest2, _base, _add,
428  _shiftAmt, _shiftType, _index)
429  {}
430 
431  std::string
433  const loader::SymbolTable *symtab) const override
434  {
435  std::stringstream ss;
436  this->printInst(ss, Memory::AddrMd_PreIndex);
437  return ss.str();
438  }
439 };
440 
441 template<class Base>
442 class MemoryPostIndex : public Base
443 {
444  protected:
445  MemoryPostIndex(const char *mnem, ExtMachInst _machInst,
446  OpClass __opClass, IntRegIndex _dest, IntRegIndex _base,
447  bool _add, int32_t _imm)
448  : Base(mnem, _machInst, __opClass, _dest, _base, _add, _imm)
449  {}
450 
451  MemoryPostIndex(const char *mnem, ExtMachInst _machInst,
452  OpClass __opClass, IntRegIndex _dest, IntRegIndex _base,
453  bool _add, int32_t _shiftAmt, ArmShiftType _shiftType,
454  IntRegIndex _index)
455  : Base(mnem, _machInst, __opClass, _dest, _base, _add,
456  _shiftAmt, _shiftType, _index)
457  {}
458 
459  MemoryPostIndex(const char *mnem, ExtMachInst _machInst,
460  OpClass __opClass, IntRegIndex _dest, IntRegIndex _dest2,
461  IntRegIndex _base, bool _add, int32_t _imm)
462  : Base(mnem, _machInst, __opClass, _dest, _dest2, _base, _add, _imm)
463  {}
464 
465  MemoryPostIndex(const char *mnem, ExtMachInst _machInst,
466  OpClass __opClass, IntRegIndex _result,
467  IntRegIndex _dest, IntRegIndex _dest2,
468  IntRegIndex _base, bool _add, int32_t _imm)
469  : Base(mnem, _machInst, __opClass, _result,
470  _dest, _dest2, _base, _add, _imm)
471  {}
472 
473  MemoryPostIndex(const char *mnem, ExtMachInst _machInst,
474  OpClass __opClass, IntRegIndex _dest, IntRegIndex _dest2,
475  IntRegIndex _base, bool _add,
476  int32_t _shiftAmt, ArmShiftType _shiftType,
477  IntRegIndex _index)
478  : Base(mnem, _machInst, __opClass, _dest, _dest2, _base, _add,
479  _shiftAmt, _shiftType, _index)
480  {}
481 
482  std::string
484  const loader::SymbolTable *symtab) const override
485  {
486  std::stringstream ss;
487  this->printInst(ss, Memory::AddrMd_PostIndex);
488  return ss.str();
489  }
490 };
491 
492 } // namespace ArmISA
493 } // namespace gem5
494 
495 #endif //__ARCH_ARM_INSTS_MEM_HH__
gem5::ArmISA::MemoryPreIndex::MemoryPreIndex
MemoryPreIndex(const char *mnem, ExtMachInst _machInst, OpClass __opClass, IntRegIndex _dest, IntRegIndex _base, bool _add, int32_t _imm)
Definition: mem.hh:394
gem5::ArmISA::RfeOp::urb
IntRegIndex urb
Definition: mem.hh:87
gem5::ArmISA::SrsOp
Definition: mem.hh:119
gem5::ArmISA::RfeOp::wb
bool wb
Definition: mem.hh:86
gem5::ArmISA::RfeOp::AddrMode
AddrMode
Definition: mem.hh:76
gem5::ArmISA::SrsOp::IncrementBefore
@ IncrementBefore
Definition: mem.hh:127
gem5::ArmISA::MemoryPostIndex::MemoryPostIndex
MemoryPostIndex(const char *mnem, ExtMachInst _machInst, OpClass __opClass, IntRegIndex _dest, IntRegIndex _base, bool _add, int32_t _imm)
Definition: mem.hh:445
gem5::ArmISA::Memory::~Memory
virtual ~Memory()
Definition: mem.hh:186
gem5::ArmISA::MemoryDReg::MemoryDReg
MemoryDReg(const char *mnem, ExtMachInst _machInst, OpClass __opClass, IntRegIndex _dest, IntRegIndex _dest2, IntRegIndex _base, bool _add, int32_t _shiftAmt, ArmShiftType _shiftType, IntRegIndex _index)
Definition: mem.hh:320
gem5::ArmISA::RfeOp::~RfeOp
virtual ~RfeOp()
Definition: mem.hh:102
gem5::ArmISA::MemoryPreIndex::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Definition: mem.hh:432
gem5::ArmISA::SrsOp::regMode
uint32_t regMode
Definition: mem.hh:130
gem5::ArmISA::MemoryReg::shiftType
ArmShiftType shiftType
Definition: mem.hh:301
gem5::ArmISA::MemoryDImm::MemoryDImm
MemoryDImm(const char *mnem, ExtMachInst _machInst, OpClass __opClass, IntRegIndex _dest, IntRegIndex _dest2, IntRegIndex _base, bool _add, int32_t _imm)
Definition: mem.hh:259
gem5::ArmISA::Memory::numMicroops
static const unsigned numMicroops
Definition: mem.hh:175
gem5::ArmISA::MemoryImm
Definition: mem.hh:212
gem5::ArmISA::MemoryDReg::dest2
IntRegIndex dest2
Definition: mem.hh:318
gem5::ArmISA::RfeOp
Definition: mem.hh:73
gem5::ArmISA::Memory::uops
StaticInstPtr * uops
Definition: mem.hh:177
gem5::ArmISA::MemoryPostIndex::MemoryPostIndex
MemoryPostIndex(const char *mnem, ExtMachInst _machInst, OpClass __opClass, IntRegIndex _result, IntRegIndex _dest, IntRegIndex _dest2, IntRegIndex _base, bool _add, int32_t _imm)
Definition: mem.hh:465
gem5::ArmISA::MemoryExDImm::result
IntRegIndex result
Definition: mem.hh:278
gem5::ArmISA::RfeOp::IncrementBefore
@ IncrementBefore
Definition: mem.hh:81
gem5::ArmISA::Memory::AddrMd_Offset
@ AddrMd_Offset
Definition: mem.hh:165
gem5::ArmISA::SrsOp::~SrsOp
virtual ~SrsOp()
Definition: mem.hh:144
gem5::ArmISA::RfeOp::DecrementBefore
@ DecrementBefore
Definition: mem.hh:79
gem5::ArmISA::MemoryPostIndex::MemoryPostIndex
MemoryPostIndex(const char *mnem, ExtMachInst _machInst, OpClass __opClass, IntRegIndex _dest, IntRegIndex _base, bool _add, int32_t _shiftAmt, ArmShiftType _shiftType, IntRegIndex _index)
Definition: mem.hh:451
gem5::ArmISA::MemoryExImm::printDest
void printDest(std::ostream &os) const
Definition: mem.hh:245
gem5::ArmISA::MemoryOffset::MemoryOffset
MemoryOffset(const char *mnem, ExtMachInst _machInst, OpClass __opClass, IntRegIndex _dest, IntRegIndex _dest2, IntRegIndex _base, bool _add, int32_t _imm)
Definition: mem.hh:357
gem5::ArmISA::MemoryReg
Definition: mem.hh:297
gem5::ArmISA::Memory::printInst
void printInst(std::ostream &os, AddrMode addrMode) const
Definition: mem.cc:163
gem5::ArmISA::SrsOp::AddrMode
AddrMode
Definition: mem.hh:122
gem5::loader::SymbolTable
Definition: symtab.hh:65
gem5::ArmISA::RfeOp::ura
IntRegIndex ura
Definition: mem.hh:87
gem5::ArmISA::RfeOp::fetchMicroop
StaticInstPtr fetchMicroop(MicroPC microPC) const override
Return the microop that goes with a particular micropc.
Definition: mem.hh:108
gem5::ArmISA::SrsOp::DecrementBefore
@ DecrementBefore
Definition: mem.hh:125
gem5::ArmISA::MemoryPostIndex::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Definition: mem.hh:483
gem5::ArmISA::RfeOp::numMicroops
static const unsigned numMicroops
Definition: mem.hh:88
gem5::ArmISA::Memory::dest
IntRegIndex dest
Definition: mem.hh:172
gem5::PowerISA::PCState
Definition: pcstate.hh:42
gem5::ArmISA::MemoryPreIndex::MemoryPreIndex
MemoryPreIndex(const char *mnem, ExtMachInst _machInst, OpClass __opClass, IntRegIndex _dest, IntRegIndex _base, bool _add, int32_t _shiftAmt, ArmShiftType _shiftType, IntRegIndex _index)
Definition: mem.hh:400
gem5::ccprintf
void ccprintf(cp::Print &print)
Definition: cprintf.hh:130
gem5::ArmISA::MemoryReg::printOffset
void printOffset(std::ostream &os) const
Definition: mem.cc:52
gem5::ArmISA::RfeOp::urc
IntRegIndex urc
Definition: mem.hh:87
gem5::ArmISA::MemoryExImm::MemoryExImm
MemoryExImm(const char *mnem, ExtMachInst _machInst, OpClass __opClass, IntRegIndex _result, IntRegIndex _dest, IntRegIndex _base, bool _add, int32_t _imm)
Definition: mem.hh:237
gem5::ArmISA::RfeOp::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: mem.cc:80
gem5::RefCountingPtr< StaticInst >
gem5::ArmISA::MemoryReg::index
IntRegIndex index
Definition: mem.hh:302
gem5::ArmISA::MemoryOffset::MemoryOffset
MemoryOffset(const char *mnem, ExtMachInst _machInst, OpClass __opClass, IntRegIndex _dest, IntRegIndex _base, bool _add, int32_t _imm)
Definition: mem.hh:343
gem5::ArmISA::MemoryExDImm::printDest
void printDest(std::ostream &os) const
Definition: mem.hh:288
gem5::SparcISA::INTREG_UREG0
@ INTREG_UREG0
Definition: int.hh:57
gem5::MicroPC
uint16_t MicroPC
Definition: types.hh:149
gem5::auxv::Base
@ Base
Definition: aux_vector.hh:76
gem5::ArmISA::Memory::Memory
Memory(const char *mnem, ExtMachInst _machInst, OpClass __opClass, IntRegIndex _dest, IntRegIndex _base, bool _add)
Definition: mem.hh:179
gem5::ArmISA::MemoryImm::MemoryImm
MemoryImm(const char *mnem, ExtMachInst _machInst, OpClass __opClass, IntRegIndex _dest, IntRegIndex _base, bool _add, int32_t _imm)
Definition: mem.hh:217
gem5::ArmISA::MemoryOffset::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Definition: mem.hh:381
gem5::ArmISA::SrsOp::numMicroops
static const unsigned numMicroops
Definition: mem.hh:133
gem5::ArmISA::MightBeMicro
Definition: mem.hh:52
gem5::ArmISA::MightBeMicro::advancePC
void advancePC(PCState &pcState) const override
Definition: mem.hh:60
gem5::ArmISA::RfeOp::IncrementAfter
@ IncrementAfter
Definition: mem.hh:80
gem5::ArmISA::Memory
Definition: mem.hh:160
gem5::ArmISA::SrsOp::wb
bool wb
Definition: mem.hh:132
gem5::ArmISA::MemoryExDImm::MemoryExDImm
MemoryExDImm(const char *mnem, ExtMachInst _machInst, OpClass __opClass, IntRegIndex _result, IntRegIndex _dest, IntRegIndex _dest2, IntRegIndex _base, bool _add, int32_t _imm)
Definition: mem.hh:280
gem5::ArmISA::Memory::add
bool add
Definition: mem.hh:174
gem5::ArmISA::Memory::AddrMd_PostIndex
@ AddrMd_PostIndex
Definition: mem.hh:167
gem5::ArmISA::Memory::base
IntRegIndex base
Definition: mem.hh:173
gem5::ArmISA::MemoryDReg::printDest
void printDest(std::ostream &os) const
Definition: mem.hh:331
gem5::ArmISA::RfeOp::uops
StaticInstPtr * uops
Definition: mem.hh:90
gem5::StaticInst::flags
std::bitset< Num_Flags > flags
Flag values for this instruction.
Definition: static_inst.hh:103
gem5::ArmISA::RfeOp::base
IntRegIndex base
Definition: mem.hh:84
gem5::ArmISA::MemoryImm::imm
int32_t imm
Definition: mem.hh:215
gem5::ArmISA::SrsOp::DecrementAfter
@ DecrementAfter
Definition: mem.hh:124
gem5::ArmISA::MemoryOffset::MemoryOffset
MemoryOffset(const char *mnem, ExtMachInst _machInst, OpClass __opClass, IntRegIndex _dest, IntRegIndex _dest2, IntRegIndex _base, bool _add, int32_t _shiftAmt, ArmShiftType _shiftType, IntRegIndex _index)
Definition: mem.hh:371
gem5::ArmISA::Memory::fetchMicroop
StaticInstPtr fetchMicroop(MicroPC microPC) const override
Return the microop that goes with a particular micropc.
Definition: mem.hh:192
gem5::ArmISA::Memory::printOffset
virtual void printOffset(std::ostream &os) const
Definition: mem.hh:199
gem5::ArmISA::MemoryDImm::printDest
void printDest(std::ostream &os) const
Definition: mem.hh:267
gem5::ArmISA::Memory::printDest
virtual void printDest(std::ostream &os) const
Definition: mem.hh:203
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::ArmISA::SrsOp::uops
StaticInstPtr * uops
Definition: mem.hh:135
pred_inst.hh
gem5::ArmISA::MemoryPreIndex
Definition: mem.hh:391
gem5::ArmISA::SrsOp::SrsOp
SrsOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass, uint32_t _regMode, AddrMode _mode, bool _wb)
Definition: mem.hh:137
gem5::ArmISA::MemoryOffset
Definition: mem.hh:340
gem5::ArmISA::MemoryDReg
Definition: mem.hh:315
gem5::GenericISA::SimplePCState::advance
void advance()
Definition: types.hh:181
gem5::ArmISA::Memory::AddrMode
AddrMode
Definition: mem.hh:163
gem5::ArmISA::SrsOp::fetchMicroop
StaticInstPtr fetchMicroop(MicroPC microPC) const override
Return the microop that goes with a particular micropc.
Definition: mem.hh:150
gem5::X86ISA::ExtMachInst
Definition: types.hh:206
gem5::ArmISA::MemoryImm::printOffset
void printOffset(std::ostream &os) const
Definition: mem.hh:223
gem5::ArmISA::Memory::AddrMd_PreIndex
@ AddrMd_PreIndex
Definition: mem.hh:166
gem5::ArmISA::SrsOp::IncrementAfter
@ IncrementAfter
Definition: mem.hh:126
gem5::ArmISA::MemoryPreIndex::MemoryPreIndex
MemoryPreIndex(const char *mnem, ExtMachInst _machInst, OpClass __opClass, IntRegIndex _result, IntRegIndex _dest, IntRegIndex _dest2, IntRegIndex _base, bool _add, int32_t _imm)
Definition: mem.hh:414
gem5::X86ISA::os
Bitfield< 17 > os
Definition: misc.hh:809
gem5::ArmISA::ss
Bitfield< 21 > ss
Definition: misc_types.hh:59
gem5::ArmISA::MemoryReg::shiftAmt
int32_t shiftAmt
Definition: mem.hh:300
gem5::ArmISA::MemoryDImm
Definition: mem.hh:254
gem5::MipsISA::pc
Bitfield< 4 > pc
Definition: pra_constants.hh:243
gem5::ArmISA::RfeOp::DecrementAfter
@ DecrementAfter
Definition: mem.hh:78
gem5::ArmISA::MemoryPreIndex::MemoryPreIndex
MemoryPreIndex(const char *mnem, ExtMachInst _machInst, OpClass __opClass, IntRegIndex _dest, IntRegIndex _dest2, IntRegIndex _base, bool _add, int32_t _shiftAmt, ArmShiftType _shiftType, IntRegIndex _index)
Definition: mem.hh:422
gem5::ArmISA::MemoryOffset::MemoryOffset
MemoryOffset(const char *mnem, ExtMachInst _machInst, OpClass __opClass, IntRegIndex _dest, IntRegIndex _base, bool _add, int32_t _shiftAmt, ArmShiftType _shiftType, IntRegIndex _index)
Definition: mem.hh:349
gem5::ArmISA::MemoryDImm::dest2
IntRegIndex dest2
Definition: mem.hh:257
gem5::ArmISA::PredOp
Base class for predicated integer operations.
Definition: pred_inst.hh:214
gem5::ArmISA::MightBeMicro::MightBeMicro
MightBeMicro(const char *mnem, ExtMachInst _machInst, OpClass __opClass)
Definition: mem.hh:55
gem5::ArmISA::SrsOp::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: mem.cc:105
gem5::ArmISA::MemoryPostIndex::MemoryPostIndex
MemoryPostIndex(const char *mnem, ExtMachInst _machInst, OpClass __opClass, IntRegIndex _dest, IntRegIndex _dest2, IntRegIndex _base, bool _add, int32_t _shiftAmt, ArmShiftType _shiftType, IntRegIndex _index)
Definition: mem.hh:473
gem5::ArmISA::MemoryOffset::MemoryOffset
MemoryOffset(const char *mnem, ExtMachInst _machInst, OpClass __opClass, IntRegIndex _result, IntRegIndex _dest, IntRegIndex _dest2, IntRegIndex _base, bool _add, int32_t _imm)
Definition: mem.hh:363
gem5::ArmISA::MemoryPostIndex::MemoryPostIndex
MemoryPostIndex(const char *mnem, ExtMachInst _machInst, OpClass __opClass, IntRegIndex _dest, IntRegIndex _dest2, IntRegIndex _base, bool _add, int32_t _imm)
Definition: mem.hh:459
gem5::ArmISA::MemoryExDImm
Definition: mem.hh:275
gem5::ArmISA::ArmStaticInst::printIntReg
void printIntReg(std::ostream &os, RegIndex reg_idx, uint8_t opWidth=0) const
Print a register name for disassembly given the unique dependence tag number (FP or int).
Definition: static_inst.cc:299
gem5::ArmISA::MemoryReg::MemoryReg
MemoryReg(const char *mnem, ExtMachInst _machInst, OpClass __opClass, IntRegIndex _dest, IntRegIndex _base, bool _add, int32_t _shiftAmt, ArmShiftType _shiftType, IntRegIndex _index)
Definition: mem.hh:304
gem5::ArmISA::MemoryPostIndex
Definition: mem.hh:442
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40
gem5::ArmISA::MemoryExImm::result
IntRegIndex result
Definition: mem.hh:235
gem5::ArmISA::SrsOp::mode
AddrMode mode
Definition: mem.hh:131
gem5::ArmISA::RfeOp::RfeOp
RfeOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass, IntRegIndex _base, AddrMode _mode, bool _wb)
Definition: mem.hh:92
gem5::ArmISA::MemoryPreIndex::MemoryPreIndex
MemoryPreIndex(const char *mnem, ExtMachInst _machInst, OpClass __opClass, IntRegIndex _dest, IntRegIndex _dest2, IntRegIndex _base, bool _add, int32_t _imm)
Definition: mem.hh:408
gem5::ArmISA::RfeOp::mode
AddrMode mode
Definition: mem.hh:85
gem5::ArmISA::MemoryExImm
Definition: mem.hh:232

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