gem5  v21.2.1.1
mem.hh
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40 
41 #ifndef __ARCH_ARM_MEM_HH__
42 #define __ARCH_ARM_MEM_HH__
43 
45 #include "arch/arm/pcstate.hh"
46 #include "cpu/thread_context.hh"
47 
48 namespace gem5
49 {
50 
51 namespace ArmISA
52 {
53 
54 class MightBeMicro : public PredOp
55 {
56  protected:
57  MightBeMicro(const char *mnem, ExtMachInst _machInst, OpClass __opClass)
58  : PredOp(mnem, _machInst, __opClass)
59  {}
60 
61  void
62  advancePC(PCStateBase &pcState) const override
63  {
64  auto &apc = pcState.as<PCState>();
65  if (flags[IsLastMicroop]) {
66  apc.uEnd();
67  } else if (flags[IsMicroop]) {
68  apc.uAdvance();
69  } else {
70  apc.advance();
71  }
72  }
73 
74  void
75  advancePC(ThreadContext *tc) const override
76  {
77  PCState pc = tc->pcState().as<PCState>();
78  if (flags[IsLastMicroop]) {
79  pc.uEnd();
80  } else if (flags[IsMicroop]) {
81  pc.uAdvance();
82  } else {
83  pc.advance();
84  }
85  tc->pcState(pc);
86  }
87 };
88 
89 // The address is a base register plus an immediate.
90 class RfeOp : public MightBeMicro
91 {
92  public:
93  enum AddrMode
94  {
99  };
100  protected:
101  IntRegIndex base;
103  bool wb;
104  IntRegIndex ura, urb, urc;
105  static const unsigned numMicroops = 3;
106 
108 
109  RfeOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
110  IntRegIndex _base, AddrMode _mode, bool _wb)
111  : MightBeMicro(mnem, _machInst, __opClass),
112  base(_base), mode(_mode), wb(_wb),
113  ura(INTREG_UREG0), urb(INTREG_UREG1),
114  urc(INTREG_UREG2),
115  uops(NULL)
116  {}
117 
118  virtual
120  {
121  delete [] uops;
122  }
123 
125  fetchMicroop(MicroPC microPC) const override
126  {
127  assert(uops != NULL && microPC < numMicroops);
128  return uops[microPC];
129  }
130 
131  std::string generateDisassembly(
132  Addr pc, const loader::SymbolTable *symtab) const override;
133 };
134 
135 // The address is a base register plus an immediate.
136 class SrsOp : public MightBeMicro
137 {
138  public:
139  enum AddrMode
140  {
145  };
146  protected:
147  uint32_t regMode;
149  bool wb;
150  static const unsigned numMicroops = 2;
151 
153 
154  SrsOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
155  uint32_t _regMode, AddrMode _mode, bool _wb)
156  : MightBeMicro(mnem, _machInst, __opClass),
157  regMode(_regMode), mode(_mode), wb(_wb), uops(NULL)
158  {}
159 
160  virtual
162  {
163  delete [] uops;
164  }
165 
167  fetchMicroop(MicroPC microPC) const override
168  {
169  assert(uops != NULL && microPC < numMicroops);
170  return uops[microPC];
171  }
172 
173  std::string generateDisassembly(
174  Addr pc, const loader::SymbolTable *symtab) const override;
175 };
176 
177 class Memory : public MightBeMicro
178 {
179  public:
180  enum AddrMode
181  {
185  };
186 
187  protected:
188 
189  IntRegIndex dest;
190  IntRegIndex base;
191  bool add;
192  static const unsigned numMicroops = 3;
193 
195 
196  Memory(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
197  IntRegIndex _dest, IntRegIndex _base, bool _add)
198  : MightBeMicro(mnem, _machInst, __opClass),
199  dest(_dest), base(_base), add(_add), uops(NULL)
200  {}
201 
202  virtual
204  {
205  delete [] uops;
206  }
207 
209  fetchMicroop(MicroPC microPC) const override
210  {
211  assert(uops != NULL && microPC < numMicroops);
212  return uops[microPC];
213  }
214 
215  virtual void
216  printOffset(std::ostream &os) const
217  {}
218 
219  virtual void
220  printDest(std::ostream &os) const
221  {
222  printIntReg(os, dest);
223  }
224 
225  void printInst(std::ostream &os, AddrMode addrMode) const;
226 };
227 
228 // The address is a base register plus an immediate.
229 class MemoryImm : public Memory
230 {
231  protected:
232  int32_t imm;
233 
234  MemoryImm(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
235  IntRegIndex _dest, IntRegIndex _base, bool _add, int32_t _imm)
236  : Memory(mnem, _machInst, __opClass, _dest, _base, _add), imm(_imm)
237  {}
238 
239  void
240  printOffset(std::ostream &os) const
241  {
242  int32_t pImm = imm;
243  if (!add)
244  pImm = -pImm;
245  ccprintf(os, "#%d", pImm);
246  }
247 };
248 
249 class MemoryExImm : public MemoryImm
250 {
251  protected:
252  IntRegIndex result;
253 
254  MemoryExImm(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
255  IntRegIndex _result, IntRegIndex _dest, IntRegIndex _base,
256  bool _add, int32_t _imm)
257  : MemoryImm(mnem, _machInst, __opClass, _dest, _base, _add, _imm),
258  result(_result)
259  {}
260 
261  void
262  printDest(std::ostream &os) const
263  {
265  os << ", ";
267  }
268 };
269 
270 // The address is a base register plus an immediate.
271 class MemoryDImm : public MemoryImm
272 {
273  protected:
274  IntRegIndex dest2;
275 
276  MemoryDImm(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
277  IntRegIndex _dest, IntRegIndex _dest2,
278  IntRegIndex _base, bool _add, int32_t _imm)
279  : MemoryImm(mnem, _machInst, __opClass, _dest, _base, _add, _imm),
280  dest2(_dest2)
281  {}
282 
283  void
284  printDest(std::ostream &os) const
285  {
287  os << ", ";
288  printIntReg(os, dest2);
289  }
290 };
291 
292 class MemoryExDImm : public MemoryDImm
293 {
294  protected:
295  IntRegIndex result;
296 
297  MemoryExDImm(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
298  IntRegIndex _result, IntRegIndex _dest, IntRegIndex _dest2,
299  IntRegIndex _base, bool _add, int32_t _imm)
300  : MemoryDImm(mnem, _machInst, __opClass, _dest, _dest2,
301  _base, _add, _imm), result(_result)
302  {}
303 
304  void
305  printDest(std::ostream &os) const
306  {
308  os << ", ";
310  }
311 };
312 
313 // The address is a shifted register plus an immediate
314 class MemoryReg : public Memory
315 {
316  protected:
317  int32_t shiftAmt;
318  ArmShiftType shiftType;
319  IntRegIndex index;
320 
321  MemoryReg(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
322  IntRegIndex _dest, IntRegIndex _base, bool _add,
323  int32_t _shiftAmt, ArmShiftType _shiftType,
324  IntRegIndex _index)
325  : Memory(mnem, _machInst, __opClass, _dest, _base, _add),
326  shiftAmt(_shiftAmt), shiftType(_shiftType), index(_index)
327  {}
328 
329  void printOffset(std::ostream &os) const;
330 };
331 
332 class MemoryDReg : public MemoryReg
333 {
334  protected:
335  IntRegIndex dest2;
336 
337  MemoryDReg(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
338  IntRegIndex _dest, IntRegIndex _dest2,
339  IntRegIndex _base, bool _add,
340  int32_t _shiftAmt, ArmShiftType _shiftType,
341  IntRegIndex _index)
342  : MemoryReg(mnem, _machInst, __opClass, _dest, _base, _add,
343  _shiftAmt, _shiftType, _index),
344  dest2(_dest2)
345  {}
346 
347  void
348  printDest(std::ostream &os) const
349  {
351  os << ", ";
352  printIntReg(os, dest2);
353  }
354 };
355 
356 template<class Base>
357 class MemoryOffset : public Base
358 {
359  protected:
360  MemoryOffset(const char *mnem, ExtMachInst _machInst,
361  OpClass __opClass, IntRegIndex _dest, IntRegIndex _base,
362  bool _add, int32_t _imm)
363  : Base(mnem, _machInst, __opClass, _dest, _base, _add, _imm)
364  {}
365 
366  MemoryOffset(const char *mnem, ExtMachInst _machInst,
367  OpClass __opClass, IntRegIndex _dest, IntRegIndex _base,
368  bool _add, int32_t _shiftAmt, ArmShiftType _shiftType,
369  IntRegIndex _index)
370  : Base(mnem, _machInst, __opClass, _dest, _base, _add,
371  _shiftAmt, _shiftType, _index)
372  {}
373 
374  MemoryOffset(const char *mnem, ExtMachInst _machInst,
375  OpClass __opClass, IntRegIndex _dest, IntRegIndex _dest2,
376  IntRegIndex _base, bool _add, int32_t _imm)
377  : Base(mnem, _machInst, __opClass, _dest, _dest2, _base, _add, _imm)
378  {}
379 
380  MemoryOffset(const char *mnem, ExtMachInst _machInst,
381  OpClass __opClass, IntRegIndex _result,
382  IntRegIndex _dest, IntRegIndex _dest2,
383  IntRegIndex _base, bool _add, int32_t _imm)
384  : Base(mnem, _machInst, __opClass, _result,
385  _dest, _dest2, _base, _add, _imm)
386  {}
387 
388  MemoryOffset(const char *mnem, ExtMachInst _machInst,
389  OpClass __opClass, IntRegIndex _dest, IntRegIndex _dest2,
390  IntRegIndex _base, bool _add,
391  int32_t _shiftAmt, ArmShiftType _shiftType,
392  IntRegIndex _index)
393  : Base(mnem, _machInst, __opClass, _dest, _dest2, _base, _add,
394  _shiftAmt, _shiftType, _index)
395  {}
396 
397  std::string
399  const loader::SymbolTable *symtab) const override
400  {
401  std::stringstream ss;
402  this->printInst(ss, Memory::AddrMd_Offset);
403  return ss.str();
404  }
405 };
406 
407 template<class Base>
408 class MemoryPreIndex : public Base
409 {
410  protected:
411  MemoryPreIndex(const char *mnem, ExtMachInst _machInst,
412  OpClass __opClass, IntRegIndex _dest, IntRegIndex _base,
413  bool _add, int32_t _imm)
414  : Base(mnem, _machInst, __opClass, _dest, _base, _add, _imm)
415  {}
416 
417  MemoryPreIndex(const char *mnem, ExtMachInst _machInst,
418  OpClass __opClass, IntRegIndex _dest, IntRegIndex _base,
419  bool _add, int32_t _shiftAmt, ArmShiftType _shiftType,
420  IntRegIndex _index)
421  : Base(mnem, _machInst, __opClass, _dest, _base, _add,
422  _shiftAmt, _shiftType, _index)
423  {}
424 
425  MemoryPreIndex(const char *mnem, ExtMachInst _machInst,
426  OpClass __opClass, IntRegIndex _dest, IntRegIndex _dest2,
427  IntRegIndex _base, bool _add, int32_t _imm)
428  : Base(mnem, _machInst, __opClass, _dest, _dest2, _base, _add, _imm)
429  {}
430 
431  MemoryPreIndex(const char *mnem, ExtMachInst _machInst,
432  OpClass __opClass, IntRegIndex _result,
433  IntRegIndex _dest, IntRegIndex _dest2,
434  IntRegIndex _base, bool _add, int32_t _imm)
435  : Base(mnem, _machInst, __opClass, _result,
436  _dest, _dest2, _base, _add, _imm)
437  {}
438 
439  MemoryPreIndex(const char *mnem, ExtMachInst _machInst,
440  OpClass __opClass, IntRegIndex _dest, IntRegIndex _dest2,
441  IntRegIndex _base, bool _add,
442  int32_t _shiftAmt, ArmShiftType _shiftType,
443  IntRegIndex _index)
444  : Base(mnem, _machInst, __opClass, _dest, _dest2, _base, _add,
445  _shiftAmt, _shiftType, _index)
446  {}
447 
448  std::string
450  const loader::SymbolTable *symtab) const override
451  {
452  std::stringstream ss;
453  this->printInst(ss, Memory::AddrMd_PreIndex);
454  return ss.str();
455  }
456 };
457 
458 template<class Base>
459 class MemoryPostIndex : public Base
460 {
461  protected:
462  MemoryPostIndex(const char *mnem, ExtMachInst _machInst,
463  OpClass __opClass, IntRegIndex _dest, IntRegIndex _base,
464  bool _add, int32_t _imm)
465  : Base(mnem, _machInst, __opClass, _dest, _base, _add, _imm)
466  {}
467 
468  MemoryPostIndex(const char *mnem, ExtMachInst _machInst,
469  OpClass __opClass, IntRegIndex _dest, IntRegIndex _base,
470  bool _add, int32_t _shiftAmt, ArmShiftType _shiftType,
471  IntRegIndex _index)
472  : Base(mnem, _machInst, __opClass, _dest, _base, _add,
473  _shiftAmt, _shiftType, _index)
474  {}
475 
476  MemoryPostIndex(const char *mnem, ExtMachInst _machInst,
477  OpClass __opClass, IntRegIndex _dest, IntRegIndex _dest2,
478  IntRegIndex _base, bool _add, int32_t _imm)
479  : Base(mnem, _machInst, __opClass, _dest, _dest2, _base, _add, _imm)
480  {}
481 
482  MemoryPostIndex(const char *mnem, ExtMachInst _machInst,
483  OpClass __opClass, IntRegIndex _result,
484  IntRegIndex _dest, IntRegIndex _dest2,
485  IntRegIndex _base, bool _add, int32_t _imm)
486  : Base(mnem, _machInst, __opClass, _result,
487  _dest, _dest2, _base, _add, _imm)
488  {}
489 
490  MemoryPostIndex(const char *mnem, ExtMachInst _machInst,
491  OpClass __opClass, IntRegIndex _dest, IntRegIndex _dest2,
492  IntRegIndex _base, bool _add,
493  int32_t _shiftAmt, ArmShiftType _shiftType,
494  IntRegIndex _index)
495  : Base(mnem, _machInst, __opClass, _dest, _dest2, _base, _add,
496  _shiftAmt, _shiftType, _index)
497  {}
498 
499  std::string
501  const loader::SymbolTable *symtab) const override
502  {
503  std::stringstream ss;
504  this->printInst(ss, Memory::AddrMd_PostIndex);
505  return ss.str();
506  }
507 };
508 
509 } // namespace ArmISA
510 } // namespace gem5
511 
512 #endif //__ARCH_ARM_INSTS_MEM_HH__
gem5::ArmISA::MemoryPreIndex::MemoryPreIndex
MemoryPreIndex(const char *mnem, ExtMachInst _machInst, OpClass __opClass, IntRegIndex _dest, IntRegIndex _base, bool _add, int32_t _imm)
Definition: mem.hh:411
gem5::ArmISA::RfeOp::urb
IntRegIndex urb
Definition: mem.hh:104
gem5::ArmISA::SrsOp
Definition: mem.hh:136
gem5::ArmISA::RfeOp::wb
bool wb
Definition: mem.hh:103
gem5::ArmISA::RfeOp::AddrMode
AddrMode
Definition: mem.hh:93
gem5::ArmISA::SrsOp::IncrementBefore
@ IncrementBefore
Definition: mem.hh:144
gem5::ArmISA::MemoryPostIndex::MemoryPostIndex
MemoryPostIndex(const char *mnem, ExtMachInst _machInst, OpClass __opClass, IntRegIndex _dest, IntRegIndex _base, bool _add, int32_t _imm)
Definition: mem.hh:462
gem5::ArmISA::Memory::~Memory
virtual ~Memory()
Definition: mem.hh:203
gem5::ArmISA::MemoryDReg::MemoryDReg
MemoryDReg(const char *mnem, ExtMachInst _machInst, OpClass __opClass, IntRegIndex _dest, IntRegIndex _dest2, IntRegIndex _base, bool _add, int32_t _shiftAmt, ArmShiftType _shiftType, IntRegIndex _index)
Definition: mem.hh:337
gem5::ArmISA::RfeOp::~RfeOp
virtual ~RfeOp()
Definition: mem.hh:119
gem5::ArmISA::MemoryPreIndex::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Definition: mem.hh:449
gem5::ArmISA::SrsOp::regMode
uint32_t regMode
Definition: mem.hh:147
gem5::ArmISA::MemoryReg::shiftType
ArmShiftType shiftType
Definition: mem.hh:318
gem5::ArmISA::MemoryDImm::MemoryDImm
MemoryDImm(const char *mnem, ExtMachInst _machInst, OpClass __opClass, IntRegIndex _dest, IntRegIndex _dest2, IntRegIndex _base, bool _add, int32_t _imm)
Definition: mem.hh:276
gem5::ArmISA::MightBeMicro::advancePC
void advancePC(PCStateBase &pcState) const override
Definition: mem.hh:62
gem5::ArmISA::Memory::numMicroops
static const unsigned numMicroops
Definition: mem.hh:192
gem5::ArmISA::MemoryImm
Definition: mem.hh:229
gem5::ArmISA::MemoryDReg::dest2
IntRegIndex dest2
Definition: mem.hh:335
gem5::ArmISA::RfeOp
Definition: mem.hh:90
gem5::ArmISA::Memory::uops
StaticInstPtr * uops
Definition: mem.hh:194
gem5::ArmISA::MemoryPostIndex::MemoryPostIndex
MemoryPostIndex(const char *mnem, ExtMachInst _machInst, OpClass __opClass, IntRegIndex _result, IntRegIndex _dest, IntRegIndex _dest2, IntRegIndex _base, bool _add, int32_t _imm)
Definition: mem.hh:482
gem5::PCStateBase::as
Target & as()
Definition: pcstate.hh:72
gem5::ThreadContext::pcState
virtual const PCStateBase & pcState() const =0
gem5::ArmISA::MemoryExDImm::result
IntRegIndex result
Definition: mem.hh:295
gem5::ArmISA::RfeOp::IncrementBefore
@ IncrementBefore
Definition: mem.hh:98
gem5::ArmISA::Memory::AddrMd_Offset
@ AddrMd_Offset
Definition: mem.hh:182
gem5::ArmISA::SrsOp::~SrsOp
virtual ~SrsOp()
Definition: mem.hh:161
gem5::ArmISA::RfeOp::DecrementBefore
@ DecrementBefore
Definition: mem.hh:96
gem5::ArmISA::MemoryPostIndex::MemoryPostIndex
MemoryPostIndex(const char *mnem, ExtMachInst _machInst, OpClass __opClass, IntRegIndex _dest, IntRegIndex _base, bool _add, int32_t _shiftAmt, ArmShiftType _shiftType, IntRegIndex _index)
Definition: mem.hh:468
gem5::ArmISA::MemoryExImm::printDest
void printDest(std::ostream &os) const
Definition: mem.hh:262
gem5::ArmISA::MemoryOffset::MemoryOffset
MemoryOffset(const char *mnem, ExtMachInst _machInst, OpClass __opClass, IntRegIndex _dest, IntRegIndex _dest2, IntRegIndex _base, bool _add, int32_t _imm)
Definition: mem.hh:374
gem5::ArmISA::MemoryReg
Definition: mem.hh:314
gem5::ArmISA::Memory::printInst
void printInst(std::ostream &os, AddrMode addrMode) const
Definition: mem.cc:163
gem5::ArmISA::SrsOp::AddrMode
AddrMode
Definition: mem.hh:139
gem5::loader::SymbolTable
Definition: symtab.hh:65
gem5::ArmISA::RfeOp::ura
IntRegIndex ura
Definition: mem.hh:104
gem5::ArmISA::RfeOp::fetchMicroop
StaticInstPtr fetchMicroop(MicroPC microPC) const override
Return the microop that goes with a particular micropc.
Definition: mem.hh:125
gem5::ArmISA::SrsOp::DecrementBefore
@ DecrementBefore
Definition: mem.hh:142
gem5::ArmISA::MemoryPostIndex::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Definition: mem.hh:500
gem5::ArmISA::RfeOp::numMicroops
static const unsigned numMicroops
Definition: mem.hh:105
gem5::ArmISA::Memory::dest
IntRegIndex dest
Definition: mem.hh:189
gem5::PowerISA::PCState
Definition: pcstate.hh:42
gem5::ArmISA::MemoryPreIndex::MemoryPreIndex
MemoryPreIndex(const char *mnem, ExtMachInst _machInst, OpClass __opClass, IntRegIndex _dest, IntRegIndex _base, bool _add, int32_t _shiftAmt, ArmShiftType _shiftType, IntRegIndex _index)
Definition: mem.hh:417
gem5::ccprintf
void ccprintf(cp::Print &print)
Definition: cprintf.hh:130
gem5::ArmISA::MemoryReg::printOffset
void printOffset(std::ostream &os) const
Definition: mem.cc:52
gem5::ArmISA::RfeOp::urc
IntRegIndex urc
Definition: mem.hh:104
gem5::ArmISA::MemoryExImm::MemoryExImm
MemoryExImm(const char *mnem, ExtMachInst _machInst, OpClass __opClass, IntRegIndex _result, IntRegIndex _dest, IntRegIndex _base, bool _add, int32_t _imm)
Definition: mem.hh:254
gem5::ArmISA::RfeOp::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: mem.cc:80
gem5::RefCountingPtr< StaticInst >
gem5::ArmISA::MemoryReg::index
IntRegIndex index
Definition: mem.hh:319
gem5::ArmISA::MemoryOffset::MemoryOffset
MemoryOffset(const char *mnem, ExtMachInst _machInst, OpClass __opClass, IntRegIndex _dest, IntRegIndex _base, bool _add, int32_t _imm)
Definition: mem.hh:360
gem5::ArmISA::MemoryExDImm::printDest
void printDest(std::ostream &os) const
Definition: mem.hh:305
gem5::SparcISA::INTREG_UREG0
@ INTREG_UREG0
Definition: int.hh:57
gem5::MicroPC
uint16_t MicroPC
Definition: types.hh:149
gem5::auxv::Base
@ Base
Definition: aux_vector.hh:74
gem5::ArmISA::Memory::Memory
Memory(const char *mnem, ExtMachInst _machInst, OpClass __opClass, IntRegIndex _dest, IntRegIndex _base, bool _add)
Definition: mem.hh:196
gem5::ArmISA::MemoryImm::MemoryImm
MemoryImm(const char *mnem, ExtMachInst _machInst, OpClass __opClass, IntRegIndex _dest, IntRegIndex _base, bool _add, int32_t _imm)
Definition: mem.hh:234
gem5::ArmISA::MemoryOffset::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Definition: mem.hh:398
gem5::ArmISA::SrsOp::numMicroops
static const unsigned numMicroops
Definition: mem.hh:150
gem5::ThreadContext
ThreadContext is the external interface to all thread state for anything outside of the CPU.
Definition: thread_context.hh:94
gem5::ArmISA::MightBeMicro
Definition: mem.hh:54
gem5::ArmISA::MightBeMicro::advancePC
void advancePC(ThreadContext *tc) const override
Definition: mem.hh:75
gem5::ArmISA::RfeOp::IncrementAfter
@ IncrementAfter
Definition: mem.hh:97
gem5::ArmISA::Memory
Definition: mem.hh:177
gem5::ArmISA::SrsOp::wb
bool wb
Definition: mem.hh:149
gem5::ArmISA::MemoryExDImm::MemoryExDImm
MemoryExDImm(const char *mnem, ExtMachInst _machInst, OpClass __opClass, IntRegIndex _result, IntRegIndex _dest, IntRegIndex _dest2, IntRegIndex _base, bool _add, int32_t _imm)
Definition: mem.hh:297
gem5::ArmISA::Memory::add
bool add
Definition: mem.hh:191
gem5::ArmISA::Memory::AddrMd_PostIndex
@ AddrMd_PostIndex
Definition: mem.hh:184
gem5::ArmISA::Memory::base
IntRegIndex base
Definition: mem.hh:190
gem5::ArmISA::MemoryDReg::printDest
void printDest(std::ostream &os) const
Definition: mem.hh:348
gem5::ArmISA::RfeOp::uops
StaticInstPtr * uops
Definition: mem.hh:107
gem5::StaticInst::flags
std::bitset< Num_Flags > flags
Flag values for this instruction.
Definition: static_inst.hh:102
gem5::ArmISA::RfeOp::base
IntRegIndex base
Definition: mem.hh:101
gem5::ArmISA::MemoryImm::imm
int32_t imm
Definition: mem.hh:232
gem5::ArmISA::SrsOp::DecrementAfter
@ DecrementAfter
Definition: mem.hh:141
gem5::ArmISA::MemoryOffset::MemoryOffset
MemoryOffset(const char *mnem, ExtMachInst _machInst, OpClass __opClass, IntRegIndex _dest, IntRegIndex _dest2, IntRegIndex _base, bool _add, int32_t _shiftAmt, ArmShiftType _shiftType, IntRegIndex _index)
Definition: mem.hh:388
gem5::ArmISA::Memory::fetchMicroop
StaticInstPtr fetchMicroop(MicroPC microPC) const override
Return the microop that goes with a particular micropc.
Definition: mem.hh:209
gem5::ArmISA::Memory::printOffset
virtual void printOffset(std::ostream &os) const
Definition: mem.hh:216
gem5::ArmISA::MemoryDImm::printDest
void printDest(std::ostream &os) const
Definition: mem.hh:284
gem5::ArmISA::Memory::printDest
virtual void printDest(std::ostream &os) const
Definition: mem.hh:220
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::ArmISA::SrsOp::uops
StaticInstPtr * uops
Definition: mem.hh:152
pred_inst.hh
gem5::ArmISA::MemoryPreIndex
Definition: mem.hh:408
pcstate.hh
gem5::ArmISA::SrsOp::SrsOp
SrsOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass, uint32_t _regMode, AddrMode _mode, bool _wb)
Definition: mem.hh:154
gem5::ArmISA::MemoryOffset
Definition: mem.hh:357
gem5::ArmISA::MemoryDReg
Definition: mem.hh:332
gem5::ArmISA::Memory::AddrMode
AddrMode
Definition: mem.hh:180
gem5::ArmISA::SrsOp::fetchMicroop
StaticInstPtr fetchMicroop(MicroPC microPC) const override
Return the microop that goes with a particular micropc.
Definition: mem.hh:167
gem5::X86ISA::ExtMachInst
Definition: types.hh:206
gem5::ArmISA::MemoryImm::printOffset
void printOffset(std::ostream &os) const
Definition: mem.hh:240
gem5::ArmISA::Memory::AddrMd_PreIndex
@ AddrMd_PreIndex
Definition: mem.hh:183
gem5::ArmISA::SrsOp::IncrementAfter
@ IncrementAfter
Definition: mem.hh:143
gem5::ArmISA::MemoryPreIndex::MemoryPreIndex
MemoryPreIndex(const char *mnem, ExtMachInst _machInst, OpClass __opClass, IntRegIndex _result, IntRegIndex _dest, IntRegIndex _dest2, IntRegIndex _base, bool _add, int32_t _imm)
Definition: mem.hh:431
gem5::X86ISA::os
Bitfield< 17 > os
Definition: misc.hh:809
gem5::ArmISA::ss
Bitfield< 21 > ss
Definition: misc_types.hh:60
gem5::ArmISA::MemoryReg::shiftAmt
int32_t shiftAmt
Definition: mem.hh:317
gem5::ArmISA::MemoryDImm
Definition: mem.hh:271
gem5::MipsISA::pc
Bitfield< 4 > pc
Definition: pra_constants.hh:243
gem5::ArmISA::RfeOp::DecrementAfter
@ DecrementAfter
Definition: mem.hh:95
gem5::ArmISA::MemoryPreIndex::MemoryPreIndex
MemoryPreIndex(const char *mnem, ExtMachInst _machInst, OpClass __opClass, IntRegIndex _dest, IntRegIndex _dest2, IntRegIndex _base, bool _add, int32_t _shiftAmt, ArmShiftType _shiftType, IntRegIndex _index)
Definition: mem.hh:439
gem5::ArmISA::MemoryOffset::MemoryOffset
MemoryOffset(const char *mnem, ExtMachInst _machInst, OpClass __opClass, IntRegIndex _dest, IntRegIndex _base, bool _add, int32_t _shiftAmt, ArmShiftType _shiftType, IntRegIndex _index)
Definition: mem.hh:366
gem5::ArmISA::MemoryDImm::dest2
IntRegIndex dest2
Definition: mem.hh:274
gem5::ArmISA::PredOp
Base class for predicated integer operations.
Definition: pred_inst.hh:216
gem5::ArmISA::MightBeMicro::MightBeMicro
MightBeMicro(const char *mnem, ExtMachInst _machInst, OpClass __opClass)
Definition: mem.hh:57
gem5::ArmISA::SrsOp::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: mem.cc:105
gem5::ArmISA::MemoryPostIndex::MemoryPostIndex
MemoryPostIndex(const char *mnem, ExtMachInst _machInst, OpClass __opClass, IntRegIndex _dest, IntRegIndex _dest2, IntRegIndex _base, bool _add, int32_t _shiftAmt, ArmShiftType _shiftType, IntRegIndex _index)
Definition: mem.hh:490
gem5::ArmISA::MemoryOffset::MemoryOffset
MemoryOffset(const char *mnem, ExtMachInst _machInst, OpClass __opClass, IntRegIndex _result, IntRegIndex _dest, IntRegIndex _dest2, IntRegIndex _base, bool _add, int32_t _imm)
Definition: mem.hh:380
gem5::PCStateBase
Definition: pcstate.hh:57
gem5::ArmISA::MemoryPostIndex::MemoryPostIndex
MemoryPostIndex(const char *mnem, ExtMachInst _machInst, OpClass __opClass, IntRegIndex _dest, IntRegIndex _dest2, IntRegIndex _base, bool _add, int32_t _imm)
Definition: mem.hh:476
gem5::ArmISA::MemoryExDImm
Definition: mem.hh:292
gem5::ArmISA::ArmStaticInst::printIntReg
void printIntReg(std::ostream &os, RegIndex reg_idx, uint8_t opWidth=0) const
Print a register name for disassembly given the unique dependence tag number (FP or int).
Definition: static_inst.cc:299
gem5::ArmISA::MemoryReg::MemoryReg
MemoryReg(const char *mnem, ExtMachInst _machInst, OpClass __opClass, IntRegIndex _dest, IntRegIndex _base, bool _add, int32_t _shiftAmt, ArmShiftType _shiftType, IntRegIndex _index)
Definition: mem.hh:321
gem5::ArmISA::MemoryPostIndex
Definition: mem.hh:459
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: tlb.cc:60
gem5::ArmISA::MemoryExImm::result
IntRegIndex result
Definition: mem.hh:252
gem5::ArmISA::SrsOp::mode
AddrMode mode
Definition: mem.hh:148
gem5::ArmISA::RfeOp::RfeOp
RfeOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass, IntRegIndex _base, AddrMode _mode, bool _wb)
Definition: mem.hh:109
thread_context.hh
gem5::ArmISA::MemoryPreIndex::MemoryPreIndex
MemoryPreIndex(const char *mnem, ExtMachInst _machInst, OpClass __opClass, IntRegIndex _dest, IntRegIndex _dest2, IntRegIndex _base, bool _add, int32_t _imm)
Definition: mem.hh:425
gem5::ArmISA::RfeOp::mode
AddrMode mode
Definition: mem.hh:102
gem5::ArmISA::MemoryExImm
Definition: mem.hh:249
gem5::GenericISA::SimplePCState::advance
void advance() override
Definition: pcstate.hh:376

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