gem5  v21.1.0.2
static_inst.cc
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28 
29 #include "cpu/static_inst.hh"
30 
31 #include <iostream>
32 
33 namespace gem5
34 {
35 
36 bool
38  TheISA::PCState &tgt) const
39 {
40  if (isDirectCtrl()) {
41  tgt = branchTarget(pc);
42  return true;
43  }
44 
45  if (isIndirectCtrl()) {
46  tgt = branchTarget(tc);
47  return true;
48  }
49 
50  return false;
51 }
52 
55 {
56  panic("StaticInst::fetchMicroop() called on instruction "
57  "that is not microcoded.");
58 }
59 
62 {
63  panic("StaticInst::branchTarget() called on instruction "
64  "that is not a PC-relative branch.");
65 }
66 
69 {
70  panic("StaticInst::branchTarget() called on instruction "
71  "that is not an indirect branch.");
72 }
73 
74 const std::string &
76 {
77  if (!cachedDisassembly) {
79  std::make_unique<std::string>(generateDisassembly(pc, symtab));
80  }
81 
82  return *cachedDisassembly;
83 }
84 
85 void
86 StaticInst::printFlags(std::ostream &outs,
87  const std::string &separator) const
88 {
89  bool printed_a_flag = false;
90 
91  for (unsigned int flag = IsNop; flag < Num_Flags; flag++) {
92  if (flags[flag]) {
93  if (printed_a_flag)
94  outs << separator;
95 
96  outs << FlagsStrings[flag];
97  printed_a_flag = true;
98  }
99  }
100 }
101 
102 } // namespace gem5
gem5::StaticInst::isIndirectCtrl
bool isIndirectCtrl() const
Definition: static_inst.hh:186
gem5::loader::SymbolTable
Definition: symtab.hh:65
gem5::RefCountingPtr< StaticInst >
gem5::StaticInst::fetchMicroop
virtual StaticInstPtr fetchMicroop(MicroPC upc) const
Return the microop that goes with a particular micropc.
Definition: static_inst.cc:54
gem5::MicroPC
uint16_t MicroPC
Definition: types.hh:149
gem5::StaticInst::branchTarget
virtual TheISA::PCState branchTarget(const TheISA::PCState &pc) const
Return the target address for a PC-relative branch.
Definition: static_inst.cc:61
gem5::ThreadContext
ThreadContext is the external interface to all thread state for anything outside of the CPU.
Definition: thread_context.hh:93
gem5::MipsISA::PCState
GenericISA::DelaySlotPCState< 4 > PCState
Definition: pcstate.hh:40
gem5::StaticInst::flags
std::bitset< Num_Flags > flags
Flag values for this instruction.
Definition: static_inst.hh:103
gem5::StaticInst::hasBranchTarget
bool hasBranchTarget(const TheISA::PCState &pc, ThreadContext *tc, TheISA::PCState &tgt) const
Return true if the instruction is a control transfer, and if so, return the target address as well.
Definition: static_inst.cc:37
static_inst.hh
gem5::StaticInst::isDirectCtrl
bool isDirectCtrl() const
Definition: static_inst.hh:185
gem5::StaticInst::generateDisassembly
virtual std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const =0
Internal function to generate disassembly string.
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::StaticInst::disassemble
virtual const std::string & disassemble(Addr pc, const loader::SymbolTable *symtab=nullptr) const
Return string representation of disassembled instruction.
Definition: static_inst.cc:75
gem5::MipsISA::pc
Bitfield< 4 > pc
Definition: pra_constants.hh:243
gem5::StaticInst::cachedDisassembly
std::unique_ptr< std::string > cachedDisassembly
String representation of disassembly (lazily evaluated via disassemble()).
Definition: static_inst.hh:287
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40
gem5::StaticInst::printFlags
void printFlags(std::ostream &outs, const std::string &separator) const
Print a separator separated list of this instruction's set flag names on the given stream.
Definition: static_inst.cc:86
panic
#define panic(...)
This implements a cprintf based panic() function.
Definition: logging.hh:177

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