gem5 v24.0.0.0
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#include <evs.hh>
Classes | |
struct | CorePins |
Public Member Functions | |
ScxEvsCortexR52 (const Params &p) | |
ScxEvsCortexR52 (const sc_core::sc_module_name &mod_name, const Params &p) | |
void | raiseInterruptPin (int num) |
void | lowerInterruptPin (int num) |
Port & | gem5_getPort (const std::string &if_name, int idx) override |
void | end_of_elaboration () override |
void | start_of_simulation () override |
void | setClkPeriod (Tick clk_period) override |
void | setSysCounterFrq (uint64_t sys_counter_frq) override |
void | setCluster (SimObject *cluster) override |
void | setResetAddr (int core, Addr addr, bool secure) override |
Private Types | |
using | Base = typename Types::Base |
using | Params = typename Types::Params |
using | Evs = ScxEvsCortexR52<Types> |
using | ClstrInt = IntSinkPin<ScxEvsCortexR52> |
Private Member Functions | |
SC_HAS_PROCESS (ScxEvsCortexR52) | |
Private Attributes | |
ClockRateControlInitiatorSocket | clockRateControl |
SignalInterruptInitiatorSocket | signalInterrupt |
std::vector< std::unique_ptr< CorePins > > | corePins |
std::vector< std::unique_ptr< ClstrInt > > | spis |
AmbaTarget | ext_slave |
SignalSender | top_reset |
SignalSender | dbg_reset |
SignalSinkPort< bool > | model_reset |
CortexR52Cluster * | gem5CpuCluster |
const Params & | params |
Static Private Attributes | |
static const int | CoreCount = Types::CoreCount |
static const int | PpiCount = 9 |
static const int | SpiCount = 960 |
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gem5::fastmodel::ScxEvsCortexR52< Types >::ScxEvsCortexR52 | ( | const sc_core::sc_module_name & | mod_name, |
const Params & | p ) |
Definition at line 97 of file evs.cc.
References tlm::tlm_base_initiator_socket< BUSWIDTH, FW_IF, BW_IF, N, POL >::bind(), gem5::fastmodel::ScxEvsCortexR52< Types >::clockRateControl, gem5::fastmodel::ScxEvsCortexR52< Types >::CoreCount, gem5::fastmodel::ScxEvsCortexR52< Types >::corePins, gem5::csprintf(), gem5::fastmodel::ScxEvsCortexR52< Types >::dbg_reset, gem5::ArmISA::i, gem5::fastmodel::ScxEvsCortexR52< Types >::model_reset, name(), gem5::SignalSinkPort< State >::onChange(), gem5::fastmodel::SignalSender::signal_out, gem5::fastmodel::ScxEvsCortexR52< Types >::signalInterrupt, gem5::fastmodel::ScxEvsCortexR52< Types >::SpiCount, gem5::fastmodel::ScxEvsCortexR52< Types >::spis, and gem5::fastmodel::ScxEvsCortexR52< Types >::top_reset.
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override |
Definition at line 133 of file evs.cc.
References gem5::ArmISA::a, and panic.
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overridevirtual |
Implements gem5::Iris::BaseCpuEvs.
Definition at line 44 of file evs.cc.
References gem5::sim_clock::as_int::s.
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overridevirtual |
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overridevirtual |
Implements gem5::Iris::BaseCpuEvs.
Definition at line 66 of file evs.cc.
References gem5::X86ISA::addr.
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overridevirtual |
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inlineoverride |
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Definition at line 75 of file evs.hh.
Referenced by gem5::fastmodel::ScxEvsCortexR52< Types >::ScxEvsCortexR52().
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Definition at line 66 of file evs.hh.
Referenced by gem5::fastmodel::ScxEvsCortexR52< Types >::ScxEvsCortexR52().
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Definition at line 117 of file evs.hh.
Referenced by gem5::fastmodel::ScxEvsCortexR52< Types >::ScxEvsCortexR52().
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Definition at line 127 of file evs.hh.
Referenced by gem5::fastmodel::ScxEvsCortexR52< Types >::ScxEvsCortexR52().
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Definition at line 129 of file evs.hh.
Referenced by gem5::fastmodel::ScxEvsCortexR52< Types >::ScxEvsCortexR52().
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Definition at line 67 of file evs.hh.
Referenced by gem5::fastmodel::ScxEvsCortexR52< Types >::CorePins::CorePins().
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Definition at line 76 of file evs.hh.
Referenced by gem5::fastmodel::ScxEvsCortexR52< Types >::CorePins::lowerInterruptPin(), gem5::fastmodel::ScxEvsCortexR52< Types >::CorePins::raiseInterruptPin(), and gem5::fastmodel::ScxEvsCortexR52< Types >::ScxEvsCortexR52().
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Definition at line 68 of file evs.hh.
Referenced by gem5::fastmodel::ScxEvsCortexR52< Types >::ScxEvsCortexR52().
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Definition at line 121 of file evs.hh.
Referenced by gem5::fastmodel::ScxEvsCortexR52< Types >::ScxEvsCortexR52().
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Definition at line 125 of file evs.hh.
Referenced by gem5::fastmodel::ScxEvsCortexR52< Types >::ScxEvsCortexR52().