gem5  v21.2.0.0
evs.hh
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27 
28 #ifndef __ARCH_ARM_FASTMODEL_CORTEXR52_EVS_HH__
29 #define __ARCH_ARM_FASTMODEL_CORTEXR52_EVS_HH__
30 
31 #include <memory>
32 
39 #include "dev/intpin.hh"
40 #include "mem/port_proxy.hh"
41 #include "params/FastModelScxEvsCortexR52x1.hh"
42 #include "params/FastModelScxEvsCortexR52x2.hh"
43 #include "params/FastModelScxEvsCortexR52x3.hh"
44 #include "params/FastModelScxEvsCortexR52x4.hh"
45 #include "scx_evs_CortexR52x1.h"
46 #include "scx_evs_CortexR52x2.h"
47 #include "scx_evs_CortexR52x3.h"
48 #include "scx_evs_CortexR52x4.h"
52 
53 namespace gem5
54 {
55 
56 GEM5_DEPRECATED_NAMESPACE(FastModel, fastmodel);
57 namespace fastmodel
58 {
59 
60 class CortexR52Cluster;
61 
62 template <class Types>
64 {
65  private:
66  static const int CoreCount = Types::CoreCount;
67  static const int PpiCount = 9;
68  static const int SpiCount = 960;
69  using Base = typename Types::Base;
70  using Params = typename Types::Params;
72 
74 
77 
78  // A structure to collect per-core connections, and also plumb up PPIs.
79  struct CorePins
80  {
82  template <typename T>
83  using SignalInitiator = amba_pv::signal_master_port<T>;
84 
85  std::string name;
86  Evs *evs;
87  int cpu;
88 
89  CorePins(Evs *_evs, int _cpu);
90 
91  void
93  {
94  evs->signalInterrupt->ppi(cpu, num, true);
95  }
96 
97  void
99  {
100  evs->signalInterrupt->ppi(cpu, num, false);
101  }
102 
104 
108 
112 
114  };
115 
117 
119 
121 
123 
124  const Params &params;
125 
127 
129 
130  public:
131  ScxEvsCortexR52(const Params &p) : ScxEvsCortexR52(p.name.c_str(), p) {}
132  ScxEvsCortexR52(const sc_core::sc_module_name &mod_name, const Params &p);
133 
134  void
136  {
137  this->signalInterrupt->spi(num, true);
138  }
139 
140  void
142  {
143  this->signalInterrupt->spi(num, false);
144  }
145 
146  Port &gem5_getPort(const std::string &if_name, int idx) override;
147 
148  void
150  {
151  Base::end_of_elaboration();
152  Base::start_of_simulation();
153  }
154  void start_of_simulation() override {}
155 
156  void sendFunc(PacketPtr pkt) override;
157 
158  void setClkPeriod(Tick clk_period) override;
159 
160  void setSysCounterFrq(uint64_t sys_counter_frq) override;
161 
162  void setCluster(SimObject *cluster) override;
163 
164  void setResetAddr(int core, Addr addr, bool secure) override;
165 };
166 
168 {
169  using Base = scx_evs_CortexR52x1;
170  using Params = FastModelScxEvsCortexR52x1Params;
171  static const int CoreCount = 1;
172 };
174 extern template class ScxEvsCortexR52<ScxEvsCortexR52x1Types>;
175 
177 {
178  using Base = scx_evs_CortexR52x2;
179  using Params = FastModelScxEvsCortexR52x2Params;
180  static const int CoreCount = 2;
181 };
183 extern template class ScxEvsCortexR52<ScxEvsCortexR52x2Types>;
184 
186 {
187  using Base = scx_evs_CortexR52x3;
188  using Params = FastModelScxEvsCortexR52x3Params;
189  static const int CoreCount = 3;
190 };
192 extern template class ScxEvsCortexR52<ScxEvsCortexR52x3Types>;
193 
195 {
196  using Base = scx_evs_CortexR52x4;
197  using Params = FastModelScxEvsCortexR52x4Params;
198  static const int CoreCount = 4;
199 };
201 extern template class ScxEvsCortexR52<ScxEvsCortexR52x4Types>;
202 
203 } // namespace fastmodel
204 } // namespace gem5
205 
206 #endif // __ARCH_ARM_FASTMODEL_CORTEXR52_EVS_HH__
gem5::fastmodel::ScxEvsCortexR52x3Types::Base
scx_evs_CortexR52x3 Base
Definition: evs.hh:187
gem5::fastmodel::ScxEvsCortexR52::CorePins::halt
SignalSender halt
Definition: evs.hh:111
gem5::fastmodel::ScxEvsCortexR52::end_of_elaboration
void end_of_elaboration() override
Definition: evs.hh:149
gem5::fastmodel::ScxEvsCortexR52::setResetAddr
void setResetAddr(int core, Addr addr, bool secure) override
Definition: evs.cc:67
gem5::fastmodel::ScxEvsCortexR52::setSysCounterFrq
void setSysCounterFrq(uint64_t sys_counter_frq) override
Definition: evs.cc:52
gem5::fastmodel::ScxEvsCortexR52::CorePins::lowerInterruptPin
void lowerInterruptPin(int num)
Definition: evs.hh:98
gem5::fastmodel::ScxEvsCortexR52::CorePins::ppis
std::vector< std::unique_ptr< CoreInt > > ppis
Definition: evs.hh:103
gem5::fastmodel::ScxEvsCortexR52::spis
std::vector< std::unique_ptr< ClstrInt > > spis
Definition: evs.hh:120
gem5::fastmodel::ScxEvsCortexR52::SpiCount
static const int SpiCount
Definition: evs.hh:68
gem5::fastmodel::ScxEvsCortexR52::CorePins::name
std::string name
Definition: evs.hh:85
gem5::fastmodel::ScxEvsCortexR52x1Types::CoreCount
static const int CoreCount
Definition: evs.hh:171
gem5::fastmodel::ScxEvsCortexR52::CorePins::amba
AmbaInitiator amba
Definition: evs.hh:107
gem5::fastmodel::ScxEvsCortexR52::CorePins::llpp
AmbaInitiator llpp
Definition: evs.hh:105
gem5::fastmodel::ScxEvsCortexR52::CorePins::cpu
int cpu
Definition: evs.hh:87
gem5::fastmodel::ScxEvsCortexR52::clockRateControl
ClockRateControlInitiatorSocket clockRateControl
Definition: evs.hh:75
gem5::Iris::BaseCpuEvs
Definition: cpu.hh:47
gem5::fastmodel::ScxEvsCortexR52::gem5CpuCluster
CortexR52Cluster * gem5CpuCluster
Definition: evs.hh:122
gem5::fastmodel::ScxEvsCortexR52::CorePins::poweron_reset
SignalSender poweron_reset
Definition: evs.hh:110
gem5::fastmodel::ScxEvsCortexR52::PpiCount
static const int PpiCount
Definition: evs.hh:67
gem5::fastmodel::ScxEvsCortexR52::ext_slave
AmbaTarget ext_slave
Definition: evs.hh:126
std::vector
STL vector class.
Definition: stl.hh:37
signal_sender.hh
gem5::fastmodel::ScxEvsCortexR52::params
const Params & params
Definition: evs.hh:124
gem5::fastmodel::ScxEvsCortexR52x2Types
Definition: evs.hh:176
gem5::fastmodel::ScxEvsCortexR52x4Types::Params
FastModelScxEvsCortexR52x4Params Params
Definition: evs.hh:197
gem5::fastmodel::ScxEvsCortexR52x3Types
Definition: evs.hh:185
cpu.hh
gem5::fastmodel::ScxEvsCortexR52x2Types::Params
FastModelScxEvsCortexR52x2Params Params
Definition: evs.hh:179
gem5::fastmodel::ScxEvsCortexR52::sendFunc
void sendFunc(PacketPtr pkt) override
Definition: evs.cc:119
gem5::fastmodel::ScxEvsCortexR52::Base
typename Types::Base Base
Definition: evs.hh:69
gem5::fastmodel::ScxEvsCortexR52::CorePins::raiseInterruptPin
void raiseInterruptPin(int num)
Definition: evs.hh:92
gem5::ClockRateControlInitiatorSocket
Definition: exported_clock_rate_control.hh:63
gem5::fastmodel::ScxEvsCortexR52::CoreCount
static const int CoreCount
Definition: evs.hh:66
gem5::fastmodel::ScxEvsCortexR52::raiseInterruptPin
void raiseInterruptPin(int num)
Definition: evs.hh:135
gem5::fastmodel::ScxEvsCortexR52::CorePins
Definition: evs.hh:79
sc_event.hh
gem5::auxv::Base
@ Base
Definition: aux_vector.hh:74
gem5::fastmodel::SignalSender
Definition: signal_sender.hh:45
gem5::fastmodel::ScxEvsCortexR52::CorePins::evs
Evs * evs
Definition: evs.hh:86
gem5::Packet
A Packet is used to encapsulate a transfer between two objects in the memory system (e....
Definition: packet.hh:283
gem5::MipsISA::p
Bitfield< 0 > p
Definition: pra_constants.hh:326
gem5::Tick
uint64_t Tick
Tick count type.
Definition: types.hh:58
gem5::fastmodel::ScxEvsCortexR52::CorePins::cfgvectable
SignalInitiator< uint64_t > cfgvectable
Definition: evs.hh:113
port_proxy.hh
gem5::fastmodel::ScxEvsCortexR52x2Types::Base
scx_evs_CortexR52x2 Base
Definition: evs.hh:178
gem5::fastmodel::ScxEvsCortexR52::setCluster
void setCluster(SimObject *cluster) override
Definition: evs.cc:59
gem5::fastmodel::ScxEvsCortexR52::ScxEvsCortexR52
ScxEvsCortexR52(const Params &p)
Definition: evs.hh:131
sc_core::sc_module_name
Definition: sc_module_name.hh:41
gem5::fastmodel::ScxEvsCortexR52::Params
typename Types::Params Params
Definition: evs.hh:70
gem5::SimObject
Abstract superclass for simulation objects.
Definition: sim_object.hh:146
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::GEM5_DEPRECATED_NAMESPACE
GEM5_DEPRECATED_NAMESPACE(GuestABI, guest_abi)
signal_interrupt.hh
gem5::fastmodel::CortexR52Cluster
Definition: cortex_r52.hh:81
name
const std::string & name()
Definition: trace.cc:49
sc_module.hh
amba_ports.hh
gem5::fastmodel::ScxEvsCortexR52::lowerInterruptPin
void lowerInterruptPin(int num)
Definition: evs.hh:141
gem5::fastmodel::ScxEvsCortexR52x1Types::Params
FastModelScxEvsCortexR52x1Params Params
Definition: evs.hh:170
gem5::fastmodel::ScxEvsCortexR52::SC_HAS_PROCESS
SC_HAS_PROCESS(ScxEvsCortexR52)
gem5::fastmodel::ScxEvsCortexR52::signalInterrupt
SignalInterruptInitiatorSocket signalInterrupt
Definition: evs.hh:76
gem5::fastmodel::ScxEvsCortexR52::start_of_simulation
void start_of_simulation() override
Definition: evs.hh:154
gem5::fastmodel::ScxEvsCortexR52::CorePins::core_reset
SignalSender core_reset
Definition: evs.hh:109
gem5::Port
Ports are used to interface objects to each other.
Definition: port.hh:61
gem5::fastmodel::ScxEvsCortexR52x4Types
Definition: evs.hh:194
sc_gem5::TlmInitiatorBaseWrapper
Definition: tlm_port_wrapper.hh:40
gem5::fastmodel::ScxEvsCortexR52::top_reset
SignalSender top_reset
Definition: evs.hh:128
gem5::fastmodel::ScxEvsCortexR52x4Types::Base
scx_evs_CortexR52x4 Base
Definition: evs.hh:196
gem5::IntSinkPin
Definition: intpin.hh:78
gem5::fastmodel::ScxEvsCortexR52::corePins
std::vector< std::unique_ptr< CorePins > > corePins
Definition: evs.hh:116
gem5::fastmodel::ScxEvsCortexR52x1Types::Base
scx_evs_CortexR52x1 Base
Definition: evs.hh:169
gem5::fastmodel::ScxEvsCortexR52::CorePins::CorePins
CorePins(Evs *_evs, int _cpu)
Definition: evs.cc:73
exported_clock_rate_control.hh
gem5::fastmodel::ScxEvsCortexR52x1Types
Definition: evs.hh:167
tlm_port_wrapper.hh
gem5::fastmodel::ScxEvsCortexR52::CorePins::flash
AmbaInitiator flash
Definition: evs.hh:106
intpin.hh
gem5::SignalInterruptInitiatorSocket
Definition: signal_interrupt.hh:60
gem5::fastmodel::ScxEvsCortexR52::gem5_getPort
Port & gem5_getPort(const std::string &if_name, int idx) override
Definition: evs.cc:129
signal_receiver.hh
gem5::fastmodel::ScxEvsCortexR52::CorePins::SignalInitiator
amba_pv::signal_master_port< T > SignalInitiator
Definition: evs.hh:83
sc_gem5::TlmTargetBaseWrapper
Definition: tlm_port_wrapper.hh:44
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: tlb.cc:60
gem5::fastmodel::ScxEvsCortexR52x3Types::Params
FastModelScxEvsCortexR52x3Params Params
Definition: evs.hh:188
gem5::fastmodel::ScxEvsCortexR52::setClkPeriod
void setClkPeriod(Tick clk_period) override
Definition: evs.cc:45
gem5::fastmodel::ScxEvsCortexR52
Definition: evs.hh:63
gem5::X86ISA::addr
Bitfield< 3 > addr
Definition: types.hh:84

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