28 #ifndef __ARCH_ARM_FASTMODEL_CORTEXR52_EVS_HH__
29 #define __ARCH_ARM_FASTMODEL_CORTEXR52_EVS_HH__
42 #include "params/FastModelScxEvsCortexR52x1.hh"
43 #include "params/FastModelScxEvsCortexR52x2.hh"
44 #include "params/FastModelScxEvsCortexR52x3.hh"
45 #include "params/FastModelScxEvsCortexR52x4.hh"
46 #include "scx_evs_CortexR52x1.h"
47 #include "scx_evs_CortexR52x2.h"
48 #include "scx_evs_CortexR52x3.h"
49 #include "scx_evs_CortexR52x4.h"
61 class CortexR52Cluster;
63 template <
class Types>
71 using Params =
typename Types::Params;
142 this->signalInterrupt->spi(num,
true);
148 this->signalInterrupt->spi(num,
false);
156 core_pin->poweron_reset.signal_out.set_state(0,
true);
157 core_pin->poweron_reset.signal_out.set_state(0,
false);
160 this->top_reset.
signal_out.set_state(0,
true);
161 this->top_reset.
signal_out.set_state(0,
false);
163 this->dbg_reset.
signal_out.set_state(0,
true);
164 this->dbg_reset.
signal_out.set_state(0,
false);
172 Base::end_of_elaboration();
173 Base::start_of_simulation();
190 using Base = scx_evs_CortexR52x1;
191 using Params = FastModelScxEvsCortexR52x1Params;
199 using Base = scx_evs_CortexR52x2;
200 using Params = FastModelScxEvsCortexR52x2Params;
201 static const int CoreCount = 2;
208 using Base = scx_evs_CortexR52x3;
209 using Params = FastModelScxEvsCortexR52x3Params;
210 static const int CoreCount = 3;
217 using Base = scx_evs_CortexR52x4;
218 using Params = FastModelScxEvsCortexR52x4Params;
219 static const int CoreCount = 4;
A Packet is used to encapsulate a transfer between two objects in the memory system (e....
Ports are used to interface objects to each other.
Abstract superclass for simulation objects.
void raiseInterruptPin(int num)
static const int SpiCount
void setSysCounterFrq(uint64_t sys_counter_frq) override
static const int PpiCount
std::vector< std::unique_ptr< ClstrInt > > spis
void lowerInterruptPin(int num)
CortexR52Cluster * gem5CpuCluster
typename Types::Base Base
void end_of_elaboration() override
Port & gem5_getPort(const std::string &if_name, int idx) override
SC_HAS_PROCESS(ScxEvsCortexR52)
void setCluster(SimObject *cluster) override
void setClkPeriod(Tick clk_period) override
std::vector< std::unique_ptr< CorePins > > corePins
void sendFunc(PacketPtr pkt) override
SignalInterruptInitiatorSocket signalInterrupt
typename Types::Params Params
ResetResponsePort< ScxEvsCortexR52 > model_reset
void setResetAddr(int core, Addr addr, bool secure) override
static const int CoreCount
ScxEvsCortexR52(const Params &p)
void start_of_simulation() override
ClockRateControlInitiatorSocket clockRateControl
amba_pv::signal_master_port< bool > signal_out
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
uint64_t Tick
Tick count type.
GEM5_DEPRECATED_NAMESPACE(GuestABI, guest_abi)
PortProxy Object Declaration.
amba_pv::signal_master_port< T > SignalInitiator
std::vector< std::unique_ptr< CoreInt > > ppis
SignalSender poweron_reset
SignalInitiator< uint64_t > cfgvectable
void lowerInterruptPin(int num)
CorePins(Evs *_evs, int _cpu)
void raiseInterruptPin(int num)
static const int CoreCount
FastModelScxEvsCortexR52x1Params Params
FastModelScxEvsCortexR52x2Params Params
FastModelScxEvsCortexR52x3Params Params
FastModelScxEvsCortexR52x4Params Params
const std::string & name()