gem5  v22.0.0.1
evs.hh
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27 
28 #ifndef __ARCH_ARM_FASTMODEL_CORTEXR52_EVS_HH__
29 #define __ARCH_ARM_FASTMODEL_CORTEXR52_EVS_HH__
30 
31 #include <memory>
32 
39 #include "dev/intpin.hh"
40 #include "dev/reset_port.hh"
41 #include "mem/port_proxy.hh"
42 #include "params/FastModelScxEvsCortexR52x1.hh"
43 #include "params/FastModelScxEvsCortexR52x2.hh"
44 #include "params/FastModelScxEvsCortexR52x3.hh"
45 #include "params/FastModelScxEvsCortexR52x4.hh"
46 #include "scx_evs_CortexR52x1.h"
47 #include "scx_evs_CortexR52x2.h"
48 #include "scx_evs_CortexR52x3.h"
49 #include "scx_evs_CortexR52x4.h"
53 
54 namespace gem5
55 {
56 
57 GEM5_DEPRECATED_NAMESPACE(FastModel, fastmodel);
58 namespace fastmodel
59 {
60 
61 class CortexR52Cluster;
62 
63 template <class Types>
65 {
66  private:
67  static const int CoreCount = Types::CoreCount;
68  static const int PpiCount = 9;
69  static const int SpiCount = 960;
70  using Base = typename Types::Base;
71  using Params = typename Types::Params;
73 
75 
78 
79  // A structure to collect per-core connections, and also plumb up PPIs.
80  struct CorePins
81  {
83  template <typename T>
84  using SignalInitiator = amba_pv::signal_master_port<T>;
85 
86  std::string name;
87  Evs *evs;
88  int cpu;
89 
90  CorePins(Evs *_evs, int _cpu);
91 
92  void
94  {
95  evs->signalInterrupt->ppi(cpu, num, true);
96  }
97 
98  void
100  {
101  evs->signalInterrupt->ppi(cpu, num, false);
102  }
103 
105 
109 
113 
115  };
116 
118 
120 
122 
124 
126 
128 
130 
132 
133  const Params &params;
134 
135  public:
136  ScxEvsCortexR52(const Params &p) : ScxEvsCortexR52(p.name.c_str(), p) {}
137  ScxEvsCortexR52(const sc_core::sc_module_name &mod_name, const Params &p);
138 
139  void
141  {
142  this->signalInterrupt->spi(num, true);
143  }
144 
145  void
147  {
148  this->signalInterrupt->spi(num, false);
149  }
150 
151  void
153  {
154  // Reset all cores.
155  for (auto &core_pin : corePins) {
156  core_pin->poweron_reset.signal_out.set_state(0, true);
157  core_pin->poweron_reset.signal_out.set_state(0, false);
158  }
159  // Reset L2 system.
160  this->top_reset.signal_out.set_state(0, true);
161  this->top_reset.signal_out.set_state(0, false);
162  // Reset debug APB.
163  this->dbg_reset.signal_out.set_state(0, true);
164  this->dbg_reset.signal_out.set_state(0, false);
165  }
166 
167  Port &gem5_getPort(const std::string &if_name, int idx) override;
168 
169  void
171  {
172  Base::end_of_elaboration();
173  Base::start_of_simulation();
174  }
175  void start_of_simulation() override {}
176 
177  void sendFunc(PacketPtr pkt) override;
178 
179  void setClkPeriod(Tick clk_period) override;
180 
181  void setSysCounterFrq(uint64_t sys_counter_frq) override;
182 
183  void setCluster(SimObject *cluster) override;
184 
185  void setResetAddr(int core, Addr addr, bool secure) override;
186 };
187 
189 {
190  using Base = scx_evs_CortexR52x1;
191  using Params = FastModelScxEvsCortexR52x1Params;
192  static const int CoreCount = 1;
193 };
195 extern template class ScxEvsCortexR52<ScxEvsCortexR52x1Types>;
196 
198 {
199  using Base = scx_evs_CortexR52x2;
200  using Params = FastModelScxEvsCortexR52x2Params;
201  static const int CoreCount = 2;
202 };
204 extern template class ScxEvsCortexR52<ScxEvsCortexR52x2Types>;
205 
207 {
208  using Base = scx_evs_CortexR52x3;
209  using Params = FastModelScxEvsCortexR52x3Params;
210  static const int CoreCount = 3;
211 };
213 extern template class ScxEvsCortexR52<ScxEvsCortexR52x3Types>;
214 
216 {
217  using Base = scx_evs_CortexR52x4;
218  using Params = FastModelScxEvsCortexR52x4Params;
219  static const int CoreCount = 4;
220 };
222 extern template class ScxEvsCortexR52<ScxEvsCortexR52x4Types>;
223 
224 } // namespace fastmodel
225 } // namespace gem5
226 
227 #endif // __ARCH_ARM_FASTMODEL_CORTEXR52_EVS_HH__
gem5::fastmodel::ScxEvsCortexR52x3Types::Base
scx_evs_CortexR52x3 Base
Definition: evs.hh:208
gem5::fastmodel::ScxEvsCortexR52::CorePins::halt
SignalSender halt
Definition: evs.hh:112
gem5::fastmodel::ScxEvsCortexR52::end_of_elaboration
void end_of_elaboration() override
Definition: evs.hh:170
gem5::fastmodel::ScxEvsCortexR52::setResetAddr
void setResetAddr(int core, Addr addr, bool secure) override
Definition: evs.cc:67
gem5::fastmodel::ScxEvsCortexR52::setSysCounterFrq
void setSysCounterFrq(uint64_t sys_counter_frq) override
Definition: evs.cc:52
gem5::fastmodel::ScxEvsCortexR52::CorePins::lowerInterruptPin
void lowerInterruptPin(int num)
Definition: evs.hh:99
gem5::fastmodel::ScxEvsCortexR52::CorePins::ppis
std::vector< std::unique_ptr< CoreInt > > ppis
Definition: evs.hh:104
gem5::fastmodel::ScxEvsCortexR52::spis
std::vector< std::unique_ptr< ClstrInt > > spis
Definition: evs.hh:121
gem5::fastmodel::ScxEvsCortexR52::SpiCount
static const int SpiCount
Definition: evs.hh:69
gem5::fastmodel::ScxEvsCortexR52::CorePins::name
std::string name
Definition: evs.hh:86
gem5::fastmodel::ScxEvsCortexR52x1Types::CoreCount
static const int CoreCount
Definition: evs.hh:192
gem5::fastmodel::ScxEvsCortexR52::CorePins::amba
AmbaInitiator amba
Definition: evs.hh:108
gem5::fastmodel::ScxEvsCortexR52::CorePins::llpp
AmbaInitiator llpp
Definition: evs.hh:106
gem5::fastmodel::ScxEvsCortexR52::CorePins::cpu
int cpu
Definition: evs.hh:88
gem5::fastmodel::ScxEvsCortexR52::clockRateControl
ClockRateControlInitiatorSocket clockRateControl
Definition: evs.hh:76
gem5::Iris::BaseCpuEvs
Definition: cpu.hh:47
gem5::fastmodel::ScxEvsCortexR52::gem5CpuCluster
CortexR52Cluster * gem5CpuCluster
Definition: evs.hh:131
gem5::fastmodel::ScxEvsCortexR52::CorePins::poweron_reset
SignalSender poweron_reset
Definition: evs.hh:111
gem5::fastmodel::ScxEvsCortexR52::PpiCount
static const int PpiCount
Definition: evs.hh:68
gem5::fastmodel::ScxEvsCortexR52::ext_slave
AmbaTarget ext_slave
Definition: evs.hh:123
std::vector
STL vector class.
Definition: stl.hh:37
signal_sender.hh
gem5::fastmodel::ScxEvsCortexR52::params
const Params & params
Definition: evs.hh:133
gem5::fastmodel::ScxEvsCortexR52x2Types
Definition: evs.hh:197
gem5::fastmodel::ScxEvsCortexR52::model_reset
ResetResponsePort< ScxEvsCortexR52 > model_reset
Definition: evs.hh:129
gem5::fastmodel::ScxEvsCortexR52x4Types::Params
FastModelScxEvsCortexR52x4Params Params
Definition: evs.hh:218
gem5::fastmodel::ScxEvsCortexR52x3Types
Definition: evs.hh:206
cpu.hh
gem5::fastmodel::ScxEvsCortexR52x2Types::Params
FastModelScxEvsCortexR52x2Params Params
Definition: evs.hh:200
gem5::fastmodel::ScxEvsCortexR52::sendFunc
void sendFunc(PacketPtr pkt) override
Definition: evs.cc:122
gem5::fastmodel::ScxEvsCortexR52::Base
typename Types::Base Base
Definition: evs.hh:70
gem5::fastmodel::ScxEvsCortexR52::CorePins::raiseInterruptPin
void raiseInterruptPin(int num)
Definition: evs.hh:93
gem5::ClockRateControlInitiatorSocket
Definition: exported_clock_rate_control.hh:63
gem5::fastmodel::ScxEvsCortexR52::CoreCount
static const int CoreCount
Definition: evs.hh:67
gem5::fastmodel::ScxEvsCortexR52::raiseInterruptPin
void raiseInterruptPin(int num)
Definition: evs.hh:140
gem5::fastmodel::ScxEvsCortexR52::CorePins
Definition: evs.hh:80
sc_event.hh
gem5::auxv::Base
@ Base
Definition: aux_vector.hh:74
gem5::fastmodel::SignalSender
Definition: signal_sender.hh:45
gem5::fastmodel::ScxEvsCortexR52::CorePins::evs
Evs * evs
Definition: evs.hh:87
gem5::fastmodel::SignalSender::signal_out
amba_pv::signal_master_port< bool > signal_out
Definition: signal_sender.hh:48
gem5::VegaISA::p
Bitfield< 54 > p
Definition: pagetable.hh:70
gem5::Packet
A Packet is used to encapsulate a transfer between two objects in the memory system (e....
Definition: packet.hh:291
gem5::Tick
uint64_t Tick
Tick count type.
Definition: types.hh:58
gem5::fastmodel::ScxEvsCortexR52::CorePins::cfgvectable
SignalInitiator< uint64_t > cfgvectable
Definition: evs.hh:114
port_proxy.hh
gem5::fastmodel::ScxEvsCortexR52x2Types::Base
scx_evs_CortexR52x2 Base
Definition: evs.hh:199
gem5::fastmodel::ScxEvsCortexR52::setCluster
void setCluster(SimObject *cluster) override
Definition: evs.cc:59
gem5::fastmodel::ScxEvsCortexR52::ScxEvsCortexR52
ScxEvsCortexR52(const Params &p)
Definition: evs.hh:136
sc_core::sc_module_name
Definition: sc_module_name.hh:41
gem5::fastmodel::ScxEvsCortexR52::Params
typename Types::Params Params
Definition: evs.hh:71
gem5::SimObject
Abstract superclass for simulation objects.
Definition: sim_object.hh:146
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::fastmodel::ScxEvsCortexR52::dbg_reset
SignalSender dbg_reset
Definition: evs.hh:127
gem5::GEM5_DEPRECATED_NAMESPACE
GEM5_DEPRECATED_NAMESPACE(GuestABI, guest_abi)
signal_interrupt.hh
gem5::fastmodel::CortexR52Cluster
Definition: cortex_r52.hh:81
name
const std::string & name()
Definition: trace.cc:49
sc_module.hh
amba_ports.hh
gem5::fastmodel::ScxEvsCortexR52::lowerInterruptPin
void lowerInterruptPin(int num)
Definition: evs.hh:146
gem5::fastmodel::ScxEvsCortexR52x1Types::Params
FastModelScxEvsCortexR52x1Params Params
Definition: evs.hh:191
gem5::fastmodel::ScxEvsCortexR52::SC_HAS_PROCESS
SC_HAS_PROCESS(ScxEvsCortexR52)
gem5::fastmodel::ScxEvsCortexR52::requestReset
void requestReset()
Definition: evs.hh:152
gem5::fastmodel::ScxEvsCortexR52::signalInterrupt
SignalInterruptInitiatorSocket signalInterrupt
Definition: evs.hh:77
gem5::fastmodel::ScxEvsCortexR52::start_of_simulation
void start_of_simulation() override
Definition: evs.hh:175
gem5::fastmodel::ScxEvsCortexR52::CorePins::core_reset
SignalSender core_reset
Definition: evs.hh:110
gem5::ResetResponsePort
Definition: reset_port.hh:46
gem5::Port
Ports are used to interface objects to each other.
Definition: port.hh:61
gem5::fastmodel::ScxEvsCortexR52x4Types
Definition: evs.hh:215
sc_gem5::TlmInitiatorBaseWrapper
Definition: tlm_port_wrapper.hh:40
gem5::fastmodel::ScxEvsCortexR52::top_reset
SignalSender top_reset
Definition: evs.hh:125
gem5::fastmodel::ScxEvsCortexR52x4Types::Base
scx_evs_CortexR52x4 Base
Definition: evs.hh:217
gem5::IntSinkPin
Definition: intpin.hh:78
gem5::fastmodel::ScxEvsCortexR52::corePins
std::vector< std::unique_ptr< CorePins > > corePins
Definition: evs.hh:117
gem5::fastmodel::ScxEvsCortexR52x1Types::Base
scx_evs_CortexR52x1 Base
Definition: evs.hh:190
gem5::fastmodel::ScxEvsCortexR52::CorePins::CorePins
CorePins(Evs *_evs, int _cpu)
Definition: evs.cc:73
exported_clock_rate_control.hh
gem5::fastmodel::ScxEvsCortexR52x1Types
Definition: evs.hh:188
tlm_port_wrapper.hh
reset_port.hh
gem5::fastmodel::ScxEvsCortexR52::CorePins::flash
AmbaInitiator flash
Definition: evs.hh:107
intpin.hh
gem5::SignalInterruptInitiatorSocket
Definition: signal_interrupt.hh:60
gem5::fastmodel::ScxEvsCortexR52::gem5_getPort
Port & gem5_getPort(const std::string &if_name, int idx) override
Definition: evs.cc:132
signal_receiver.hh
gem5::fastmodel::ScxEvsCortexR52::CorePins::SignalInitiator
amba_pv::signal_master_port< T > SignalInitiator
Definition: evs.hh:84
sc_gem5::TlmTargetBaseWrapper
Definition: tlm_port_wrapper.hh:44
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: gpu_translation_state.hh:37
gem5::fastmodel::ScxEvsCortexR52x3Types::Params
FastModelScxEvsCortexR52x3Params Params
Definition: evs.hh:209
gem5::fastmodel::ScxEvsCortexR52::setClkPeriod
void setClkPeriod(Tick clk_period) override
Definition: evs.cc:45
gem5::fastmodel::ScxEvsCortexR52
Definition: evs.hh:64
gem5::X86ISA::addr
Bitfield< 3 > addr
Definition: types.hh:84

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