gem5  v22.1.0.0
evs.hh
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27 
28 #ifndef __ARCH_ARM_FASTMODEL_CORTEXR52_EVS_HH__
29 #define __ARCH_ARM_FASTMODEL_CORTEXR52_EVS_HH__
30 
31 #include <memory>
32 
39 #include "dev/intpin.hh"
40 #include "dev/reset_port.hh"
41 #include "mem/port_proxy.hh"
42 #include "params/FastModelScxEvsCortexR52x1.hh"
43 #include "params/FastModelScxEvsCortexR52x2.hh"
44 #include "params/FastModelScxEvsCortexR52x3.hh"
45 #include "params/FastModelScxEvsCortexR52x4.hh"
46 #include "scx_evs_CortexR52x1.h"
47 #include "scx_evs_CortexR52x2.h"
48 #include "scx_evs_CortexR52x3.h"
49 #include "scx_evs_CortexR52x4.h"
53 
54 namespace gem5
55 {
56 
57 GEM5_DEPRECATED_NAMESPACE(FastModel, fastmodel);
58 namespace fastmodel
59 {
60 
61 class CortexR52Cluster;
62 
63 template <class Types>
65 {
66  private:
67  static const int CoreCount = Types::CoreCount;
68  static const int PpiCount = 9;
69  static const int SpiCount = 960;
70  using Base = typename Types::Base;
71  using Params = typename Types::Params;
73 
75 
78 
79  // A structure to collect per-core connections, and also plumb up PPIs.
80  struct CorePins
81  {
83  template <typename T>
84  using SignalInitiator = amba_pv::signal_master_port<T>;
85 
86  std::string name;
87  Evs *evs;
88  int cpu;
89 
90  CorePins(Evs *_evs, int _cpu);
91 
92  void
94  {
95  evs->signalInterrupt->ppi(cpu, num, true);
96  }
97 
98  void
100  {
101  evs->signalInterrupt->ppi(cpu, num, false);
102  }
103 
105 
109 
113 
115  };
116 
118 
120 
122 
124 
126 
128 
130 
132 
133  const Params &params;
134 
135  public:
136  ScxEvsCortexR52(const Params &p) : ScxEvsCortexR52(p.name.c_str(), p) {}
137  ScxEvsCortexR52(const sc_core::sc_module_name &mod_name, const Params &p);
138 
139  void
141  {
142  this->signalInterrupt->spi(num, true);
143  }
144 
145  void
147  {
148  this->signalInterrupt->spi(num, false);
149  }
150 
151  void
153  {
154  // Reset all cores.
155  for (auto &core_pin : corePins) {
156  core_pin->poweron_reset.signal_out.set_state(0, true);
157  core_pin->poweron_reset.signal_out.set_state(0, false);
158  }
159  // Reset L2 system.
160  this->top_reset.signal_out.set_state(0, true);
161  this->top_reset.signal_out.set_state(0, false);
162  // Reset debug APB.
163  this->dbg_reset.signal_out.set_state(0, true);
164  this->dbg_reset.signal_out.set_state(0, false);
165  }
166 
167  Port &gem5_getPort(const std::string &if_name, int idx) override;
168 
169  void
171  {
172  Base::end_of_elaboration();
173  Base::start_of_simulation();
174  }
175  void start_of_simulation() override {}
176 
177  void sendFunc(PacketPtr pkt) override;
178 
179  void setClkPeriod(Tick clk_period) override;
180 
181  void setSysCounterFrq(uint64_t sys_counter_frq) override;
182 
183  void setCluster(SimObject *cluster) override;
184 
185  void setResetAddr(int core, Addr addr, bool secure) override;
186 };
187 
189 {
190  using Base = scx_evs_CortexR52x1;
191  using Params = FastModelScxEvsCortexR52x1Params;
192  static const int CoreCount = 1;
193 };
195 extern template class ScxEvsCortexR52<ScxEvsCortexR52x1Types>;
196 
198 {
199  using Base = scx_evs_CortexR52x2;
200  using Params = FastModelScxEvsCortexR52x2Params;
201  static const int CoreCount = 2;
202 };
204 extern template class ScxEvsCortexR52<ScxEvsCortexR52x2Types>;
205 
207 {
208  using Base = scx_evs_CortexR52x3;
209  using Params = FastModelScxEvsCortexR52x3Params;
210  static const int CoreCount = 3;
211 };
213 extern template class ScxEvsCortexR52<ScxEvsCortexR52x3Types>;
214 
216 {
217  using Base = scx_evs_CortexR52x4;
218  using Params = FastModelScxEvsCortexR52x4Params;
219  static const int CoreCount = 4;
220 };
222 extern template class ScxEvsCortexR52<ScxEvsCortexR52x4Types>;
223 
224 } // namespace fastmodel
225 } // namespace gem5
226 
227 #endif // __ARCH_ARM_FASTMODEL_CORTEXR52_EVS_HH__
A Packet is used to encapsulate a transfer between two objects in the memory system (e....
Definition: packet.hh:294
Ports are used to interface objects to each other.
Definition: port.hh:62
Abstract superclass for simulation objects.
Definition: sim_object.hh:148
void raiseInterruptPin(int num)
Definition: evs.hh:140
static const int SpiCount
Definition: evs.hh:69
void setSysCounterFrq(uint64_t sys_counter_frq) override
Definition: evs.cc:52
static const int PpiCount
Definition: evs.hh:68
std::vector< std::unique_ptr< ClstrInt > > spis
Definition: evs.hh:121
void lowerInterruptPin(int num)
Definition: evs.hh:146
CortexR52Cluster * gem5CpuCluster
Definition: evs.hh:131
typename Types::Base Base
Definition: evs.hh:70
void end_of_elaboration() override
Definition: evs.hh:170
Port & gem5_getPort(const std::string &if_name, int idx) override
Definition: evs.cc:132
void setCluster(SimObject *cluster) override
Definition: evs.cc:59
void setClkPeriod(Tick clk_period) override
Definition: evs.cc:45
std::vector< std::unique_ptr< CorePins > > corePins
Definition: evs.hh:117
void sendFunc(PacketPtr pkt) override
Definition: evs.cc:122
SignalInterruptInitiatorSocket signalInterrupt
Definition: evs.hh:77
typename Types::Params Params
Definition: evs.hh:71
ResetResponsePort< ScxEvsCortexR52 > model_reset
Definition: evs.hh:129
void setResetAddr(int core, Addr addr, bool secure) override
Definition: evs.cc:67
static const int CoreCount
Definition: evs.hh:67
ScxEvsCortexR52(const Params &p)
Definition: evs.hh:136
void start_of_simulation() override
Definition: evs.hh:175
ClockRateControlInitiatorSocket clockRateControl
Definition: evs.hh:76
amba_pv::signal_master_port< bool > signal_out
STL vector class.
Definition: stl.hh:37
Bitfield< 54 > p
Definition: pagetable.hh:70
Bitfield< 3 > addr
Definition: types.hh:84
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
uint64_t Tick
Tick count type.
Definition: types.hh:58
GEM5_DEPRECATED_NAMESPACE(GuestABI, guest_abi)
PortProxy Object Declaration.
amba_pv::signal_master_port< T > SignalInitiator
Definition: evs.hh:84
std::vector< std::unique_ptr< CoreInt > > ppis
Definition: evs.hh:104
SignalInitiator< uint64_t > cfgvectable
Definition: evs.hh:114
CorePins(Evs *_evs, int _cpu)
Definition: evs.cc:73
FastModelScxEvsCortexR52x1Params Params
Definition: evs.hh:191
FastModelScxEvsCortexR52x2Params Params
Definition: evs.hh:200
FastModelScxEvsCortexR52x3Params Params
Definition: evs.hh:209
FastModelScxEvsCortexR52x4Params Params
Definition: evs.hh:218
const std::string & name()
Definition: trace.cc:49

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