gem5  v21.2.1.1
evs.cc
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27 
29 
32 #include "base/logging.hh"
33 #include "sim/core.hh"
35 
36 namespace gem5
37 {
38 
39 GEM5_DEPRECATED_NAMESPACE(FastModel, fastmodel);
40 namespace fastmodel
41 {
42 
43 template <class Types>
44 void
46 {
47  clockRateControl->set_mul_div(sim_clock::as_int::s, clk_period);
48 }
49 
50 template <class Types>
51 void
53 {
54  panic("Not implemented for R52.");
55 }
56 
57 template <class Types>
58 void
60 {
61  gem5CpuCluster = dynamic_cast<CortexR52Cluster *>(cluster);
62  panic_if(!gem5CpuCluster, "Cluster should be of type CortexR52Cluster");
63 }
64 
65 template <class Types>
66 void
68 {
69  this->corePins[core]->cfgvectable.set_state(0, addr);
70 }
71 
72 template <class Types>
74  name(csprintf("%s.cpu%s", _evs->name(), _cpu)),
75  evs(_evs), cpu(_cpu),
76  llpp(evs->llpp[cpu], name + ".llpp", -1),
77  flash(evs->flash[cpu], name + ".flash", -1),
78  amba(evs->amba[cpu], name + ".amba", -1),
79  core_reset(name + ".core_reset", 0),
80  poweron_reset(name + ".poweron_reset", 0),
81  halt(name + ".halt", 0),
82  cfgvectable((name + "cfgvectable").c_str())
83 {
84  for (int i = 0; i < Evs::PpiCount; i++) {
85  ppis.emplace_back(
86  new CoreInt(csprintf("%s.ppi[%d]", name, i), i, this));
87  }
88  core_reset.signal_out.bind(evs->core_reset[cpu]);
89  poweron_reset.signal_out.bind(evs->poweron_reset[cpu]);
90  halt.signal_out.bind(evs->halt[cpu]);
91  cfgvectable.bind(evs->cfgvectable[cpu]);
92 }
93 
94 
95 template <class Types>
97  const sc_core::sc_module_name &mod_name, const Params &p) :
98  Base(mod_name),
99  params(p),
100  ext_slave(Base::ext_slave, p.name + ".ext_slave", -1),
101  top_reset(p.name + ".top_reset", 0)
102 {
103  for (int i = 0; i < CoreCount; i++)
104  corePins.emplace_back(new CorePins(this, i));
105 
106  for (int i = 0; i < SpiCount; i++) {
107  spis.emplace_back(
108  new ClstrInt(csprintf("%s.spi[%d]", name(), i), i, this));
109  }
110 
111  top_reset.signal_out.bind(Base::top_reset);
112 
113  clockRateControl.bind(this->clock_rate_s);
114  signalInterrupt.bind(this->signal_interrupt);
115 }
116 
117 template <class Types>
118 void
120 {
121  auto *trans = sc_gem5::packet2payload(pkt);
122  panic_if(Base::amba[0]->transport_dbg(*trans) != trans->get_data_length(),
123  "Didn't send entire functional packet!");
124  trans->release();
125 }
126 
127 template <class Types>
128 Port &
129 ScxEvsCortexR52<Types>::gem5_getPort(const std::string &if_name, int idx)
130 {
131  if (if_name == "llpp") {
132  return this->corePins.at(idx)->llpp;
133  } else if (if_name == "flash") {
134  return this->corePins.at(idx)->flash;
135  } else if (if_name == "amba") {
136  return this->corePins.at(idx)->amba;
137  } else if (if_name == "core_reset") {
138  return this->corePins.at(idx)->core_reset;
139  } else if (if_name == "poweron_reset") {
140  return this->corePins.at(idx)->poweron_reset;
141  } else if (if_name == "halt") {
142  return this->corePins.at(idx)->halt;
143  } else if (if_name == "ext_slave") {
144  return this->ext_slave;
145  } else if (if_name == "top_reset") {
146  return this->top_reset;
147  } else if (if_name == "spi") {
148  return *this->spis.at(idx);
149  } else if (if_name.substr(0, 3) == "ppi") {
150  int cpu;
151  try {
152  cpu = std::stoi(if_name.substr(4));
153  } catch (const std::invalid_argument &a) {
154  panic("Couldn't find CPU number in %s.", if_name);
155  }
156  return *this->corePins.at(cpu)->ppis.at(idx);
157  } else {
158  return Base::gem5_getPort(if_name, idx);
159  }
160 }
161 
166 
167 } // namespace fastmodel
168 } // namespace gem5
gem5::fastmodel::ScxEvsCortexR52::CorePins::CoreInt
IntSinkPin< CorePins > CoreInt
Definition: evs.hh:81
gem5::fastmodel::ScxEvsCortexR52::CorePins::halt
SignalSender halt
Definition: evs.hh:111
gem5::fastmodel::ScxEvsCortexR52::setResetAddr
void setResetAddr(int core, Addr addr, bool secure) override
Definition: evs.cc:67
gem5::fastmodel::ScxEvsCortexR52::setSysCounterFrq
void setSysCounterFrq(uint64_t sys_counter_frq) override
Definition: evs.cc:52
gem5::fastmodel::ScxEvsCortexR52::CorePins::ppis
std::vector< std::unique_ptr< CoreInt > > ppis
Definition: evs.hh:103
gem5::fastmodel::ScxEvsCortexR52::spis
std::vector< std::unique_ptr< ClstrInt > > spis
Definition: evs.hh:120
gem5::fastmodel::ScxEvsCortexR52::SpiCount
static const int SpiCount
Definition: evs.hh:68
gem5::fastmodel::ScxEvsCortexR52::CorePins::name
std::string name
Definition: evs.hh:85
gem5_to_tlm.hh
gem5::fastmodel::ScxEvsCortexR52::CorePins::cpu
int cpu
Definition: evs.hh:87
gem5::fastmodel::ScxEvsCortexR52::clockRateControl
ClockRateControlInitiatorSocket clockRateControl
Definition: evs.hh:75
sc_gem5::packet2payload
tlm::tlm_generic_payload * packet2payload(PacketPtr packet)
Convert a gem5 packet to a TLM payload by copying all the relevant information to new tlm payload.
Definition: gem5_to_tlm.cc:128
gem5::fastmodel::ScxEvsCortexR52::CorePins::poweron_reset
SignalSender poweron_reset
Definition: evs.hh:110
gem5::ArmISA::a
Bitfield< 8 > a
Definition: misc_types.hh:66
gem5::fastmodel::ScxEvsCortexR52::PpiCount
static const int PpiCount
Definition: evs.hh:67
gem5::fastmodel::ScxEvsCortexR52::ext_slave
AmbaTarget ext_slave
Definition: evs.hh:126
gem5::fastmodel::ScxEvsCortexR52::params
const Params & params
Definition: evs.hh:124
gem5::csprintf
std::string csprintf(const char *format, const Args &...args)
Definition: cprintf.hh:161
gem5::sim_clock::as_int::s
Tick s
second
Definition: core.cc:68
gem5::ArmISA::i
Bitfield< 7 > i
Definition: misc_types.hh:67
cpu.hh
gem5::fastmodel::ScxEvsCortexR52::sendFunc
void sendFunc(PacketPtr pkt) override
Definition: evs.cc:119
gem5::fastmodel::ScxEvsCortexR52::Base
typename Types::Base Base
Definition: evs.hh:69
gem5::fastmodel::ScxEvsCortexR52::CoreCount
static const int CoreCount
Definition: evs.hh:66
gem5::fastmodel::ScxEvsCortexR52::CorePins
Definition: evs.hh:79
gem5::fastmodel::ScxEvsCortexR52::CorePins::evs
Evs * evs
Definition: evs.hh:86
gem5::fastmodel::SignalSender::signal_out
amba_pv::signal_master_port< bool > signal_out
Definition: signal_sender.hh:48
gem5::Packet
A Packet is used to encapsulate a transfer between two objects in the memory system (e....
Definition: packet.hh:283
gem5::MipsISA::p
Bitfield< 0 > p
Definition: pra_constants.hh:326
gem5::Tick
uint64_t Tick
Tick count type.
Definition: types.hh:58
gem5::fastmodel::ScxEvsCortexR52::CorePins::cfgvectable
SignalInitiator< uint64_t > cfgvectable
Definition: evs.hh:113
gem5::fastmodel::ScxEvsCortexR52::setCluster
void setCluster(SimObject *cluster) override
Definition: evs.cc:59
gem5::fastmodel::ScxEvsCortexR52::ScxEvsCortexR52
ScxEvsCortexR52(const Params &p)
Definition: evs.hh:131
sc_core::sc_module_name
Definition: sc_module_name.hh:41
gem5::MipsISA::halt
Bitfield< 26 > halt
Definition: dt_constants.hh:47
gem5::fastmodel::ScxEvsCortexR52::Params
typename Types::Params Params
Definition: evs.hh:70
gem5::SimObject
Abstract superclass for simulation objects.
Definition: sim_object.hh:146
cortex_r52.hh
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::GEM5_DEPRECATED_NAMESPACE
GEM5_DEPRECATED_NAMESPACE(GuestABI, guest_abi)
gem5::fastmodel::CortexR52Cluster
Definition: cortex_r52.hh:81
name
const std::string & name()
Definition: trace.cc:49
gem5::fastmodel::ScxEvsCortexR52::ClstrInt
IntSinkPin< ScxEvsCortexR52 > ClstrInt
Definition: evs.hh:118
gem5::fastmodel::ScxEvsCortexR52::signalInterrupt
SignalInterruptInitiatorSocket signalInterrupt
Definition: evs.hh:76
panic_if
#define panic_if(cond,...)
Conditional panic macro that checks the supplied condition and only panics if the condition is true a...
Definition: logging.hh:204
tlm::tlm_base_initiator_socket::bind
virtual void bind(base_target_socket_type &s)
Definition: initiator_socket.hh:121
gem5::fastmodel::ScxEvsCortexR52::CorePins::core_reset
SignalSender core_reset
Definition: evs.hh:109
gem5::Port
Ports are used to interface objects to each other.
Definition: port.hh:61
evs.hh
gem5::fastmodel::ScxEvsCortexR52::top_reset
SignalSender top_reset
Definition: evs.hh:128
core.hh
gem5::fastmodel::ScxEvsCortexR52::corePins
std::vector< std::unique_ptr< CorePins > > corePins
Definition: evs.hh:116
gem5::fastmodel::ScxEvsCortexR52::CorePins::CorePins
CorePins(Evs *_evs, int _cpu)
Definition: evs.cc:73
logging.hh
gem5::fastmodel::ScxEvsCortexR52::gem5_getPort
Port & gem5_getPort(const std::string &if_name, int idx) override
Definition: evs.cc:129
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: tlb.cc:60
gem5::fastmodel::ScxEvsCortexR52::setClkPeriod
void setClkPeriod(Tick clk_period) override
Definition: evs.cc:45
gem5::fastmodel::ScxEvsCortexR52
Definition: evs.hh:63
panic
#define panic(...)
This implements a cprintf based panic() function.
Definition: logging.hh:178
gem5::X86ISA::addr
Bitfield< 3 > addr
Definition: types.hh:84

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