gem5  v21.1.0.2
evs.cc
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27 
29 
32 #include "base/logging.hh"
33 #include "sim/core.hh"
35 
36 namespace gem5
37 {
38 
39 GEM5_DEPRECATED_NAMESPACE(FastModel, fastmodel);
40 namespace fastmodel
41 {
42 
43 template <class Types>
44 void
46 {
47  clockRateControl->set_mul_div(sim_clock::as_int::s, clk_period);
48 }
49 
50 template <class Types>
51 void
53 {
54  panic("Not implemented for R52.");
55 }
56 
57 template <class Types>
58 void
60 {
61  gem5CpuCluster = dynamic_cast<CortexR52Cluster *>(cluster);
62  panic_if(!gem5CpuCluster, "Cluster should be of type CortexR52Cluster");
63 }
64 
65 template <class Types>
67  name(csprintf("%s.cpu%s", _evs->name(), _cpu)),
68  evs(_evs), cpu(_cpu),
69  llpp(evs->llpp[cpu], name + ".llpp", -1),
70  flash(evs->flash[cpu], name + ".flash", -1),
71  amba(evs->amba[cpu], name + ".amba", -1)
72 {
73  for (int i = 0; i < Evs::PpiCount; i++) {
74  ppis.emplace_back(
75  new CoreInt(csprintf("%s.ppi[%d]", name, i), i, this));
76  }
77 }
78 
79 
80 template <class Types>
82  const sc_core::sc_module_name &mod_name, const Params &p) :
83  Base(mod_name),
84  params(p)
85 {
86  for (int i = 0; i < CoreCount; i++)
87  corePins.emplace_back(new CorePins(this, i));
88 
89  for (int i = 0; i < SpiCount; i++) {
90  spis.emplace_back(
91  new ClstrInt(csprintf("%s.spi[%d]", name(), i), i, this));
92  }
93 
94  clockRateControl.bind(this->clock_rate_s);
95  signalInterrupt.bind(this->signal_interrupt);
96 }
97 
98 template <class Types>
99 void
101 {
102  auto *trans = sc_gem5::packet2payload(pkt);
103  panic_if(Base::amba[0]->transport_dbg(*trans) != trans->get_data_length(),
104  "Didn't send entire functional packet!");
105  trans->release();
106 }
107 
108 template <class Types>
109 Port &
110 ScxEvsCortexR52<Types>::gem5_getPort(const std::string &if_name, int idx)
111 {
112  if (if_name == "llpp") {
113  return this->corePins.at(idx)->llpp;
114  } else if (if_name == "flash") {
115  return this->corePins.at(idx)->flash;
116  } else if (if_name == "amba") {
117  return this->corePins.at(idx)->amba;
118  } else if (if_name == "spi") {
119  return *this->spis.at(idx);
120  } else if (if_name.substr(0, 3) == "ppi") {
121  int cpu;
122  try {
123  cpu = std::stoi(if_name.substr(4));
124  } catch (const std::invalid_argument &a) {
125  panic("Couldn't find CPU number in %s.", if_name);
126  }
127  return *this->corePins.at(cpu)->ppis.at(idx);
128  } else {
129  return Base::gem5_getPort(if_name, idx);
130  }
131 }
132 
137 
138 } // namespace fastmodel
139 } // namespace gem5
gem5::fastmodel::ScxEvsCortexR52::CorePins::CoreInt
IntSinkPin< CorePins > CoreInt
Definition: evs.hh:80
gem5::fastmodel::ScxEvsCortexR52::setSysCounterFrq
void setSysCounterFrq(uint64_t sys_counter_frq) override
Definition: evs.cc:52
gem5::fastmodel::ScxEvsCortexR52::CorePins::ppis
std::vector< std::unique_ptr< CoreInt > > ppis
Definition: evs.hh:100
gem5::fastmodel::ScxEvsCortexR52::spis
std::vector< std::unique_ptr< ClstrInt > > spis
Definition: evs.hh:111
gem5::fastmodel::ScxEvsCortexR52::SpiCount
static const int SpiCount
Definition: evs.hh:67
gem5::fastmodel::ScxEvsCortexR52::CorePins::name
std::string name
Definition: evs.hh:82
gem5_to_tlm.hh
gem5::fastmodel::ScxEvsCortexR52::clockRateControl
ClockRateControlInitiatorSocket clockRateControl
Definition: evs.hh:74
sc_gem5::packet2payload
tlm::tlm_generic_payload * packet2payload(PacketPtr packet)
Convert a gem5 packet to a TLM payload by copying all the relevant information to new tlm payload.
Definition: gem5_to_tlm.cc:128
gem5::ArmISA::a
Bitfield< 8 > a
Definition: misc_types.hh:65
gem5::fastmodel::ScxEvsCortexR52::PpiCount
static const int PpiCount
Definition: evs.hh:66
gem5::fastmodel::ScxEvsCortexR52::params
const Params & params
Definition: evs.hh:115
gem5::csprintf
std::string csprintf(const char *format, const Args &...args)
Definition: cprintf.hh:161
gem5::sim_clock::as_int::s
Tick s
second
Definition: core.cc:68
gem5::ArmISA::i
Bitfield< 7 > i
Definition: misc_types.hh:66
cpu.hh
gem5::fastmodel::ScxEvsCortexR52::sendFunc
void sendFunc(PacketPtr pkt) override
Definition: evs.cc:100
gem5::fastmodel::ScxEvsCortexR52::Base
typename Types::Base Base
Definition: evs.hh:68
gem5::fastmodel::ScxEvsCortexR52::CoreCount
static const int CoreCount
Definition: evs.hh:65
gem5::fastmodel::ScxEvsCortexR52::CorePins
Definition: evs.hh:78
gem5::Packet
A Packet is used to encapsulate a transfer between two objects in the memory system (e....
Definition: packet.hh:283
gem5::MipsISA::p
Bitfield< 0 > p
Definition: pra_constants.hh:326
gem5::Tick
uint64_t Tick
Tick count type.
Definition: types.hh:58
gem5::fastmodel::ScxEvsCortexR52::setCluster
void setCluster(SimObject *cluster) override
Definition: evs.cc:59
gem5::fastmodel::ScxEvsCortexR52::ScxEvsCortexR52
ScxEvsCortexR52(const Params &p)
Definition: evs.hh:118
sc_core::sc_module_name
Definition: sc_module_name.hh:41
gem5::fastmodel::ScxEvsCortexR52::Params
typename Types::Params Params
Definition: evs.hh:69
gem5::SimObject
Abstract superclass for simulation objects.
Definition: sim_object.hh:146
cortex_r52.hh
core.hh
gem5::GEM5_DEPRECATED_NAMESPACE
GEM5_DEPRECATED_NAMESPACE(GuestABI, guest_abi)
gem5::fastmodel::CortexR52Cluster
Definition: cortex_r52.hh:79
name
const std::string & name()
Definition: trace.cc:49
gem5::fastmodel::ScxEvsCortexR52::ClstrInt
IntSinkPin< ScxEvsCortexR52 > ClstrInt
Definition: evs.hh:109
gem5::fastmodel::ScxEvsCortexR52::signalInterrupt
SignalInterruptInitiatorSocket signalInterrupt
Definition: evs.hh:75
panic_if
#define panic_if(cond,...)
Conditional panic macro that checks the supplied condition and only panics if the condition is true a...
Definition: logging.hh:203
tlm::tlm_base_initiator_socket::bind
virtual void bind(base_target_socket_type &s)
Definition: initiator_socket.hh:121
gem5::Port
Ports are used to interface objects to each other.
Definition: port.hh:61
evs.hh
gem5::fastmodel::ScxEvsCortexR52::corePins
std::vector< std::unique_ptr< CorePins > > corePins
Definition: evs.hh:107
gem5::fastmodel::ScxEvsCortexR52::CorePins::CorePins
CorePins(Evs *_evs, int _cpu)
Definition: evs.cc:66
logging.hh
gem5::fastmodel::ScxEvsCortexR52::gem5_getPort
Port & gem5_getPort(const std::string &if_name, int idx) override
Definition: evs.cc:110
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40
gem5::fastmodel::ScxEvsCortexR52::setClkPeriod
void setClkPeriod(Tick clk_period) override
Definition: evs.cc:45
gem5::fastmodel::ScxEvsCortexR52
Definition: evs.hh:62
panic
#define panic(...)
This implements a cprintf based panic() function.
Definition: logging.hh:177

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