gem5  v22.1.0.0
pipeline.hh
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37 
45 #ifndef __CPU_MINOR_PIPELINE_HH__
46 #define __CPU_MINOR_PIPELINE_HH__
47 
48 #include "cpu/minor/activity.hh"
49 #include "cpu/minor/cpu.hh"
50 #include "cpu/minor/decode.hh"
51 #include "cpu/minor/execute.hh"
52 #include "cpu/minor/fetch1.hh"
53 #include "cpu/minor/fetch2.hh"
54 #include "params/BaseMinorCPU.hh"
55 #include "sim/ticked_object.hh"
56 
57 namespace gem5
58 {
59 
61 namespace minor
62 {
63 
73 class Pipeline : public Ticked
74 {
75  protected:
77 
80 
86 
91 
96 
97  public:
99  enum StageId
100  {
101  /* A stage representing wakeup of the whole processor */
103  /* Real pipeline stages */
105  Num_StageId /* Stage count */
106  };
107 
110 
111  public:
112  Pipeline(MinorCPU &cpu_, const BaseMinorCPUParams &params);
113 
114  public:
117  void wakeupFetch(ThreadID tid);
118 
120  bool drain();
121 
122  void drainResume();
123 
125  bool isDrained();
126 
129  void evaluate() override;
130 
131  void minorTrace() const;
132 
140 
143 };
144 
145 } // namespace minor
146 } // namespace gem5
147 
148 #endif /* __CPU_MINOR_PIPELINE_HH__ */
Provide a non-protected base class for Minor's Ports as derived classes are created by Fetch1 and Exe...
Definition: cpu.hh:107
MinorCPU is an in-order CPU model with four fixed pipeline stages:
Definition: cpu.hh:86
Ticked attaches gem5's event queue/scheduler to evaluate calls and provides a start/stop interface to...
Execute stage.
Definition: execute.hh:69
A stage responsible for fetching "lines" from memory and passing them to Fetch2.
Definition: fetch1.hh:68
This stage receives lines of data from Fetch1, separates them into instructions and passes them to De...
Definition: fetch2.hh:67
Wraps a MinorBuffer with Input/Output interfaces to ensure that units within the model can only see t...
Definition: buffers.hh:223
ActivityRecorder with a Ticked interface.
Definition: activity.hh:59
The constructed pipeline.
Definition: pipeline.hh:74
Latch< BranchData > f2ToF1
Definition: pipeline.hh:82
Pipeline(MinorCPU &cpu_, const BaseMinorCPUParams &params)
Definition: pipeline.cc:58
Latch< ForwardLineData > f1ToF2
Definition: pipeline.hh:81
void minorTrace() const
Definition: pipeline.cc:111
MinorCPU::MinorCPUPort & getDataPort()
Return the DcachePort belonging to Execute for the CPU.
Definition: pipeline.cc:190
MinorActivityRecorder * getActivityRecorder()
To give the activity recorder to the CPU.
Definition: pipeline.hh:142
bool allow_idling
Allow cycles to be skipped when the pipeline is idle.
Definition: pipeline.hh:79
bool needToSignalDrained
True after drain is called but draining isn't complete.
Definition: pipeline.hh:109
MinorActivityRecorder activityRecorder
Activity recording for the pipeline.
Definition: pipeline.hh:95
void evaluate() override
A custom evaluate allows report in the right place (between stages and pipeline advance)
Definition: pipeline.cc:126
MinorCPU::MinorCPUPort & getInstPort()
Functions below here are BaseCPU operations passed on to pipeline stages.
Definition: pipeline.cc:184
void wakeupFetch(ThreadID tid)
Wake up the Fetch unit.
Definition: pipeline.cc:196
StageId
Enumerated ids of the 'stages' for the activity recorder.
Definition: pipeline.hh:100
Latch< BranchData > eToF1
Definition: pipeline.hh:85
Latch< ForwardInstData > dToE
Definition: pipeline.hh:84
bool drain()
Try to drain the CPU.
Definition: pipeline.cc:202
Latch< ForwardInstData > f2ToD
Definition: pipeline.hh:83
bool isDrained()
Test to see if the CPU is drained.
Definition: pipeline.cc:230
Top level definition of the Minor in-order CPU model.
All the fun of executing instructions from Decode and sending branch/new instruction stream info.
Fetch1 is responsible for fetching "lines" from memory and passing them to Fetch2.
Fetch2 receives lines of data from Fetch1, separates them into instructions and passes them to Decode...
ActivityRecoder from cpu/activity.h wrapped to provide evaluate and minorTrace.
Decode collects macro-ops from Fetch2 and splits them into micro-ops passed to Execute.
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
int16_t ThreadID
Thread index/ID type.
Definition: types.hh:235
GEM5_DEPRECATED_NAMESPACE(GuestABI, guest_abi)
Minor contains all the definitions within the MinorCPU apart from the CPU class itself.
Base classes for ClockedObjects which have evaluate functions to look like clock ticking operations.

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