gem5  v21.1.0.2
fetch1.cc
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37 
38 #include "cpu/minor/fetch1.hh"
39 
40 #include <cstring>
41 #include <iomanip>
42 #include <sstream>
43 
44 #include "base/cast.hh"
45 #include "base/compiler.hh"
46 #include "base/logging.hh"
47 #include "base/trace.hh"
48 #include "cpu/minor/pipeline.hh"
49 #include "debug/Drain.hh"
50 #include "debug/Fetch.hh"
51 #include "debug/MinorTrace.hh"
52 
53 namespace gem5
54 {
55 
57 namespace minor
58 {
59 
60 Fetch1::Fetch1(const std::string &name_,
61  MinorCPU &cpu_,
62  const MinorCPUParams &params,
65  Latch<BranchData>::Output prediction_,
66  std::vector<InputBuffer<ForwardLineData>> &next_stage_input_buffer) :
67  Named(name_),
68  cpu(cpu_),
69  inp(inp_),
70  out(out_),
71  prediction(prediction_),
72  nextStageReserve(next_stage_input_buffer),
73  icachePort(name_ + ".icache_port", *this, cpu_),
74  lineSnap(params.fetch1LineSnapWidth),
75  maxLineWidth(params.fetch1LineWidth),
76  fetchLimit(params.fetch1FetchLimit),
77  fetchInfo(params.numThreads),
78  threadPriority(0),
79  requests(name_ + ".requests", "lines", params.fetch1FetchLimit),
80  transfers(name_ + ".transfers", "lines", params.fetch1FetchLimit),
81  icacheState(IcacheRunning),
82  lineSeqNum(InstId::firstLineSeqNum),
83  numFetchesInMemorySystem(0),
84  numFetchesInITLB(0)
85 {
86  if (lineSnap == 0) {
88  DPRINTF(Fetch, "lineSnap set to cache line size of: %d\n",
89  lineSnap);
90  }
91 
92  if (maxLineWidth == 0) {
94  DPRINTF(Fetch, "maxLineWidth set to cache line size of: %d\n",
95  maxLineWidth);
96  }
97 
98  size_t inst_size = cpu.threads[0]->decoder.moreBytesSize();
99 
100  /* These assertions should be copied to the Python config. as well */
101  if ((lineSnap % inst_size) != 0) {
102  fatal("%s: fetch1LineSnapWidth must be a multiple "
103  "of the inst width (%d)\n", name_,
104  inst_size);
105  }
106 
107  if ((maxLineWidth >= lineSnap && (maxLineWidth % inst_size)) != 0) {
108  fatal("%s: fetch1LineWidth must be a multiple of"
109  " the inst width (%d), and >= fetch1LineSnapWidth (%d)\n",
110  name_, inst_size, lineSnap);
111  }
112 
113  if (fetchLimit < 1) {
114  fatal("%s: fetch1FetchLimit must be >= 1 (%d)\n", name_,
115  fetchLimit);
116  }
117 }
118 
119 inline ThreadID
121 {
122  /* Select thread via policy. */
123  std::vector<ThreadID> priority_list;
124 
125  switch (cpu.threadPolicy) {
126  case enums::SingleThreaded:
127  priority_list.push_back(0);
128  break;
129  case enums::RoundRobin:
130  priority_list = cpu.roundRobinPriority(threadPriority);
131  break;
132  case enums::Random:
133  priority_list = cpu.randomPriority();
134  break;
135  default:
136  panic("Unknown fetch policy");
137  }
138 
139  for (auto tid : priority_list) {
140  if (cpu.getContext(tid)->status() == ThreadContext::Active &&
141  !fetchInfo[tid].blocked &&
142  fetchInfo[tid].state == FetchRunning) {
143  threadPriority = tid;
144  return tid;
145  }
146  }
147 
148  return InvalidThreadID;
149 }
150 
151 void
153 {
154  /* Reference the currently used thread state. */
155  Fetch1ThreadInfo &thread = fetchInfo[tid];
156 
157  /* If line_offset != 0, a request is pushed for the remainder of the
158  * line. */
159  /* Use a lower, sizeof(MachInst) aligned address for the fetch */
160  Addr aligned_pc = thread.pc.instAddr() & ~((Addr) lineSnap - 1);
161  unsigned int line_offset = aligned_pc % lineSnap;
162  unsigned int request_size = maxLineWidth - line_offset;
163 
164  /* Fill in the line's id */
165  InstId request_id(tid,
166  thread.streamSeqNum, thread.predictionSeqNum,
167  lineSeqNum);
168 
169  FetchRequestPtr request = new FetchRequest(*this, request_id, thread.pc);
170 
171  DPRINTF(Fetch, "Inserting fetch into the fetch queue "
172  "%s addr: 0x%x pc: %s line_offset: %d request_size: %d\n",
173  request_id, aligned_pc, thread.pc, line_offset, request_size);
174 
175  request->request->setContext(cpu.threads[tid]->getTC()->contextId());
176  request->request->setVirt(
177  aligned_pc, request_size, Request::INST_FETCH, cpu.instRequestorId(),
178  /* I've no idea why we need the PC, but give it */
179  thread.pc.instAddr());
180 
181  DPRINTF(Fetch, "Submitting ITLB request\n");
183 
185 
186  /* Reserve space in the queues upstream of requests for results */
187  transfers.reserve();
188  requests.push(request);
189 
190  /* Submit the translation request. The response will come
191  * through finish/markDelayed on this request as it bears
192  * the Translation interface */
193  cpu.threads[request->id.threadId]->mmu->translateTiming(
194  request->request,
195  cpu.getContext(request->id.threadId),
196  request, BaseMMU::Execute);
197 
198  lineSeqNum++;
199 
200  /* Step the PC for the next line onto the line aligned next address.
201  * Note that as instructions can span lines, this PC is only a
202  * reliable 'new' PC if the next line has a new stream sequence number. */
203  thread.pc.set(aligned_pc + request_size);
204 }
205 
206 std::ostream &
207 operator <<(std::ostream &os, Fetch1::IcacheState state)
208 {
209  switch (state) {
211  os << "IcacheRunning";
212  break;
214  os << "IcacheNeedsRetry";
215  break;
216  default:
217  os << "IcacheState-" << static_cast<int>(state);
218  break;
219  }
220  return os;
221 }
222 
223 void
225 {
226  /* Make the necessary packet for a memory transaction */
228  packet->allocate();
229 
230  /* This FetchRequest becomes SenderState to allow the response to be
231  * identified */
232  packet->pushSenderState(this);
233 }
234 
235 void
236 Fetch1::FetchRequest::finish(const Fault &fault_, const RequestPtr &request_,
238 {
239  fault = fault_;
240 
241  state = Translated;
242  fetch.handleTLBResponse(this);
243 
244  /* Let's try and wake up the processor for the next cycle */
245  fetch.cpu.wakeupOnEvent(Pipeline::Fetch1StageId);
246 }
247 
248 void
250 {
252 
253  if (response->fault != NoFault) {
254  DPRINTF(Fetch, "Fault in address ITLB translation: %s, "
255  "paddr: 0x%x, vaddr: 0x%x\n",
256  response->fault->name(),
257  (response->request->hasPaddr() ?
258  response->request->getPaddr() : 0),
259  response->request->getVaddr());
260 
261  if (debug::MinorTrace)
262  minorTraceResponseLine(name(), response);
263  } else {
264  DPRINTF(Fetch, "Got ITLB response\n");
265  }
266 
267  response->state = FetchRequest::Translated;
268 
269  tryToSendToTransfers(response);
270 }
271 
273 {
274  if (packet)
275  delete packet;
276 }
277 
278 void
280 {
281  if (!requests.empty() && requests.front() != request) {
282  DPRINTF(Fetch, "Fetch not at front of requests queue, can't"
283  " issue to memory\n");
284  return;
285  }
286 
287  if (request->state == FetchRequest::InTranslation) {
288  DPRINTF(Fetch, "Fetch still in translation, not issuing to"
289  " memory\n");
290  return;
291  }
292 
293  if (request->isDiscardable() || request->fault != NoFault) {
294  /* Discarded and faulting requests carry on through transfers
295  * as Complete/packet == NULL */
296 
297  request->state = FetchRequest::Complete;
299 
300  /* Wake up the pipeline next cycle as there will be no event
301  * for this queue->queue transfer */
303  } else if (request->state == FetchRequest::Translated) {
304  if (!request->packet)
305  request->makePacket();
306 
307  /* Ensure that the packet won't delete the request */
308  assert(request->packet->needsResponse());
309 
310  if (tryToSend(request))
312  } else {
313  DPRINTF(Fetch, "Not advancing line fetch\n");
314  }
315 }
316 
317 void
319 {
320  assert(!requests.empty() && requests.front() == request);
321 
322  requests.pop();
323  transfers.push(request);
324 }
325 
326 bool
328 {
329  bool ret = false;
330 
331  if (icachePort.sendTimingReq(request->packet)) {
332  /* Invalidate the fetch_requests packet so we don't
333  * accidentally fail to deallocate it (or use it!)
334  * later by overwriting it */
335  request->packet = NULL;
338 
339  ret = true;
340 
341  DPRINTF(Fetch, "Issued fetch request to memory: %s\n",
342  request->id);
343  } else {
344  /* Needs to be resent, wait for that */
346 
347  DPRINTF(Fetch, "Line fetch needs to retry: %s\n",
348  request->id);
349  }
350 
351  return ret;
352 }
353 
354 void
356 {
357  IcacheState old_icache_state = icacheState;
358 
359  switch (icacheState) {
360  case IcacheRunning:
361  /* Move ITLB results on to the memory system */
362  if (!requests.empty()) {
364  }
365  break;
366  case IcacheNeedsRetry:
367  break;
368  }
369 
370  if (icacheState != old_icache_state) {
371  DPRINTF(Fetch, "Step in state %s moving to state %s\n",
372  old_icache_state, icacheState);
373  }
374 }
375 
376 void
378 {
379  if (!queue.empty()) {
380  delete queue.front();
381  queue.pop();
382  }
383 }
384 
385 unsigned int
387 {
388  return requests.occupiedSpace() +
390 }
391 
393 void
395  Fetch1::FetchRequestPtr response) const
396 {
397  const RequestPtr &request = response->request;
398 
399  if (response->packet && response->packet->isError()) {
400  minorLine(*this, "id=F;%s vaddr=0x%x fault=\"error packet\"\n",
401  response->id, request->getVaddr());
402  } else if (response->fault != NoFault) {
403  minorLine(*this, "id=F;%s vaddr=0x%x fault=\"%s\"\n",
404  response->id, request->getVaddr(), response->fault->name());
405  } else {
406  minorLine(*this, "id=%s size=%d vaddr=0x%x paddr=0x%x\n",
407  response->id, request->getSize(),
408  request->getVaddr(), request->getPaddr());
409  }
410 }
411 
412 bool
414 {
415  DPRINTF(Fetch, "recvTimingResp %d\n", numFetchesInMemorySystem);
416 
417  /* Only push the response if we didn't change stream? No, all responses
418  * should hit the responses queue. It's the job of 'step' to throw them
419  * away. */
420  FetchRequestPtr fetch_request = safe_cast<FetchRequestPtr>
421  (response->popSenderState());
422 
423  /* Fixup packet in fetch_request as this may have changed */
424  assert(!fetch_request->packet);
425  fetch_request->packet = response;
426 
428  fetch_request->state = FetchRequest::Complete;
429 
430  if (debug::MinorTrace)
431  minorTraceResponseLine(name(), fetch_request);
432 
433  if (response->isError()) {
434  DPRINTF(Fetch, "Received error response packet: %s\n",
435  fetch_request->id);
436  }
437 
438  /* We go to idle even if there are more things to do on the queues as
439  * it's the job of step to actually step us on to the next transaction */
440 
441  /* Let's try and wake up the processor for the next cycle to move on
442  * queues */
444 
445  /* Never busy */
446  return true;
447 }
448 
449 void
451 {
452  DPRINTF(Fetch, "recvRetry\n");
453  assert(icacheState == IcacheNeedsRetry);
454  assert(!requests.empty());
455 
456  FetchRequestPtr retryRequest = requests.front();
457 
459 
460  if (tryToSend(retryRequest))
461  moveFromRequestsToTransfers(retryRequest);
462 }
463 
464 std::ostream &
465 operator <<(std::ostream &os, Fetch1::FetchState state)
466 {
467  switch (state) {
468  case Fetch1::FetchHalted:
469  os << "FetchHalted";
470  break;
472  os << "FetchWaitingForPC";
473  break;
475  os << "FetchRunning";
476  break;
477  default:
478  os << "FetchState-" << static_cast<int>(state);
479  break;
480  }
481  return os;
482 }
483 
484 void
486 {
487  Fetch1ThreadInfo &thread = fetchInfo[branch.threadId];
488 
489  updateExpectedSeqNums(branch);
490 
491  /* Start fetching again if we were stopped */
492  switch (branch.reason) {
494  {
495  if (thread.wakeupGuard) {
496  DPRINTF(Fetch, "Not suspending fetch due to guard: %s\n",
497  branch);
498  } else {
499  DPRINTF(Fetch, "Suspending fetch: %s\n", branch);
500  thread.state = FetchWaitingForPC;
501  }
502  }
503  break;
505  DPRINTF(Fetch, "Halting fetch\n");
506  thread.state = FetchHalted;
507  break;
508  default:
509  DPRINTF(Fetch, "Changing stream on branch: %s\n", branch);
510  thread.state = FetchRunning;
511  break;
512  }
513  thread.pc = branch.target;
514 }
515 
516 void
518 {
519  Fetch1ThreadInfo &thread = fetchInfo[branch.threadId];
520 
521  DPRINTF(Fetch, "Updating streamSeqNum from: %d to %d,"
522  " predictionSeqNum from: %d to %d\n",
523  thread.streamSeqNum, branch.newStreamSeqNum,
524  thread.predictionSeqNum, branch.newPredictionSeqNum);
525 
526  /* Change the stream */
527  thread.streamSeqNum = branch.newStreamSeqNum;
528  /* Update the prediction. Note that it's possible for this to
529  * actually set the prediction to an *older* value if new
530  * predictions have been discarded by execute */
531  thread.predictionSeqNum = branch.newPredictionSeqNum;
532 }
533 
534 void
536  ForwardLineData &line)
537 {
538  Fetch1ThreadInfo &thread = fetchInfo[response->id.threadId];
539  PacketPtr packet = response->packet;
540 
541  /* Pass the prefetch abort (if any) on to Fetch2 in a ForwardLineData
542  * structure */
543  line.setFault(response->fault);
544  /* Make sequence numbers valid in return */
545  line.id = response->id;
546  /* Set PC to virtual address */
547  line.pc = response->pc;
548  /* Set the lineBase, which is a sizeof(MachInst) aligned address <=
549  * pc.instAddr() */
550  line.lineBaseAddr = response->request->getVaddr();
551 
552  if (response->fault != NoFault) {
553  /* Stop fetching if there was a fault */
554  /* Should probably try to flush the queues as well, but we
555  * can't be sure that this fault will actually reach Execute, and we
556  * can't (currently) selectively remove this stream from the queues */
557  DPRINTF(Fetch, "Stopping line fetch because of fault: %s\n",
558  response->fault->name());
560  } else {
561  line.adoptPacketData(packet);
562  /* Null the response's packet to prevent the response from trying to
563  * deallocate the packet */
564  response->packet = NULL;
565  }
566 }
567 
568 void
570 {
571  const BranchData &execute_branch = *inp.outputWire;
572  const BranchData &fetch2_branch = *prediction.outputWire;
573  ForwardLineData &line_out = *out.inputWire;
574 
575  assert(line_out.isBubble());
576 
577  for (ThreadID tid = 0; tid < cpu.numThreads; tid++)
578  fetchInfo[tid].blocked = !nextStageReserve[tid].canReserve();
579 
581  if (execute_branch.threadId != InvalidThreadID &&
582  execute_branch.threadId == fetch2_branch.threadId) {
583 
584  Fetch1ThreadInfo &thread = fetchInfo[execute_branch.threadId];
585 
586  /* Are we changing stream? Look to the Execute branches first, then
587  * to predicted changes of stream from Fetch2 */
588  if (execute_branch.isStreamChange()) {
589  if (thread.state == FetchHalted) {
590  DPRINTF(Fetch, "Halted, ignoring branch: %s\n", execute_branch);
591  } else {
592  changeStream(execute_branch);
593  }
594 
595  if (!fetch2_branch.isBubble()) {
596  DPRINTF(Fetch, "Ignoring simultaneous prediction: %s\n",
597  fetch2_branch);
598  }
599 
600  /* The streamSeqNum tagging in request/response ->req should handle
601  * discarding those requests when we get to them. */
602  } else if (thread.state != FetchHalted && fetch2_branch.isStreamChange()) {
603  /* Handle branch predictions by changing the instruction source
604  * if we're still processing the same stream (as set by streamSeqNum)
605  * as the one of the prediction.
606  */
607  if (fetch2_branch.newStreamSeqNum != thread.streamSeqNum) {
608  DPRINTF(Fetch, "Not changing stream on prediction: %s,"
609  " streamSeqNum mismatch\n",
610  fetch2_branch);
611  } else {
612  changeStream(fetch2_branch);
613  }
614  }
615  } else {
616  /* Fetch2 and Execute branches are for different threads */
617  if (execute_branch.threadId != InvalidThreadID &&
618  execute_branch.isStreamChange()) {
619 
620  if (fetchInfo[execute_branch.threadId].state == FetchHalted) {
621  DPRINTF(Fetch, "Halted, ignoring branch: %s\n", execute_branch);
622  } else {
623  changeStream(execute_branch);
624  }
625  }
626 
627  if (fetch2_branch.threadId != InvalidThreadID &&
628  fetch2_branch.isStreamChange()) {
629 
630  if (fetchInfo[fetch2_branch.threadId].state == FetchHalted) {
631  DPRINTF(Fetch, "Halted, ignoring branch: %s\n", fetch2_branch);
632  } else if (fetch2_branch.newStreamSeqNum != fetchInfo[fetch2_branch.threadId].streamSeqNum) {
633  DPRINTF(Fetch, "Not changing stream on prediction: %s,"
634  " streamSeqNum mismatch\n", fetch2_branch);
635  } else {
636  changeStream(fetch2_branch);
637  }
638  }
639  }
640 
641  if (numInFlightFetches() < fetchLimit) {
642  ThreadID fetch_tid = getScheduledThread();
643 
644  if (fetch_tid != InvalidThreadID) {
645  DPRINTF(Fetch, "Fetching from thread %d\n", fetch_tid);
646 
647  /* Generate fetch to selected thread */
648  fetchLine(fetch_tid);
649  /* Take up a slot in the fetch queue */
650  nextStageReserve[fetch_tid].reserve();
651  } else {
652  DPRINTF(Fetch, "No active threads available to fetch from\n");
653  }
654  }
655 
656 
657  /* Halting shouldn't prevent fetches in flight from being processed */
658  /* Step fetches through the icachePort queues and memory system */
659  stepQueues();
660 
661  /* As we've thrown away early lines, if there is a line, it must
662  * be from the right stream */
663  if (!transfers.empty() &&
665  {
667 
668  if (response->isDiscardable()) {
669  nextStageReserve[response->id.threadId].freeReservation();
670 
671  DPRINTF(Fetch, "Discarding translated fetch as it's for"
672  " an old stream\n");
673 
674  /* Wake up next cycle just in case there was some other
675  * action to do */
677  } else {
678  DPRINTF(Fetch, "Processing fetched line: %s\n",
679  response->id);
680 
681  processResponse(response, line_out);
682  }
683 
685  }
686 
687  /* If we generated output, and mark the stage as being active
688  * to encourage that output on to the next stage */
689  if (!line_out.isBubble())
691 
692  /* Fetch1 has no inputBuffer so the only activity we can have is to
693  * generate a line output (tested just above) or to initiate a memory
694  * fetch which will signal activity when it returns/needs stepping
695  * between queues */
696 
697 
698  /* This looks hackish. And it is, but there doesn't seem to be a better
699  * way to do this. The signal from commit to suspend fetch takes 1
700  * clock cycle to propagate to fetch. However, a legitimate wakeup
701  * may occur between cycles from the memory system. Thus wakeup guard
702  * prevents us from suspending in that case. */
703 
704  for (auto& thread : fetchInfo) {
705  thread.wakeupGuard = false;
706  }
707 }
708 
709 void
711 {
712  ThreadContext *thread_ctx = cpu.getContext(tid);
713  Fetch1ThreadInfo &thread = fetchInfo[tid];
714  thread.pc = thread_ctx->pcState();
715  thread.state = FetchRunning;
716  thread.wakeupGuard = true;
717  DPRINTF(Fetch, "[tid:%d]: Changing stream wakeup %s\n",
718  tid, thread_ctx->pcState());
719 
721 }
722 
723 bool
725 {
726  bool drained = numInFlightFetches() == 0 && (*out.inputWire).isBubble();
727  for (ThreadID tid = 0; tid < cpu.numThreads; tid++) {
728  Fetch1ThreadInfo &thread = fetchInfo[tid];
729  DPRINTF(Drain, "isDrained[tid:%d]: %s %s%s\n",
730  tid,
731  thread.state == FetchHalted,
732  (numInFlightFetches() == 0 ? "" : "inFlightFetches "),
733  ((*out.inputWire).isBubble() ? "" : "outputtingLine"));
734 
735  drained = drained && (thread.state != FetchRunning);
736  }
737 
738  return drained;
739 }
740 
741 void
743 {
744  os << id;
745 }
746 
748 {
749  Fetch1ThreadInfo &thread = fetch.fetchInfo[id.threadId];
750 
751  /* Can't discard lines in TLB/memory */
752  return state != InTranslation && state != RequestIssuing &&
753  (id.streamSeqNum != thread.streamSeqNum ||
754  id.predictionSeqNum != thread.predictionSeqNum);
755 }
756 
757 void
759 {
760  // TODO: Un-bork minorTrace for THREADS
761  // bork bork bork
762  const Fetch1ThreadInfo &thread = fetchInfo[0];
763 
764  std::ostringstream data;
765 
766  if (thread.blocked)
767  data << 'B';
768  else
769  (*out.inputWire).reportData(data);
770 
771  minor::minorTrace("state=%s icacheState=%s in_tlb_mem=%s/%s"
772  " streamSeqNum=%d lines=%s\n", thread.state, icacheState,
774  thread.streamSeqNum, data.str());
777 }
778 
779 } // namespace minor
780 } // namespace gem5
gem5::minor::ForwardLineData
Line fetch data in the forward direction.
Definition: pipe_data.hh:175
fatal
#define fatal(...)
This implements a cprintf based fatal() function.
Definition: logging.hh:189
gem5::minor::Queue::front
ElemType & front()
Head value.
Definition: buffers.hh:501
gem5::minor::Fetch1::FetchRequest::pc
TheISA::PCState pc
PC to fixup with line address.
Definition: fetch1.hh:142
gem5::MinorCPU::randomPriority
std::vector< ThreadID > randomPriority()
Definition: cpu.hh:182
gem5::minor::Fetch1::numFetchesInITLB
unsigned int numFetchesInITLB
Number of requests inside the ITLB rather than in the queues.
Definition: fetch1.hh:325
gem5::NoFault
constexpr decltype(nullptr) NoFault
Definition: types.hh:260
gem5::ThreadContext::Active
@ Active
Running.
Definition: thread_context.hh:108
gem5::RequestPort::sendTimingReq
bool sendTimingReq(PacketPtr pkt)
Attempt to send a timing request to the responder port by calling its corresponding receive function.
Definition: port.hh:495
gem5::minor::Fetch1::fetchLine
void fetchLine(ThreadID tid)
Insert a line fetch into the requests.
Definition: fetch1.cc:152
gem5::minor::Fetch1::out
Latch< ForwardLineData >::Input out
Output port carrying read lines to Fetch2.
Definition: fetch1.hh:203
gem5::minor::Fetch1::operator<<
friend std::ostream & operator<<(std::ostream &os, Fetch1::FetchState state)
Definition: fetch1.cc:465
gem5::minor::Fetch1::threadPriority
ThreadID threadPriority
Definition: fetch1.hh:291
gem5::minor::ForwardLineData::id
InstId id
Thread, stream, prediction ...
Definition: pipe_data.hh:199
data
const char data[]
Definition: circlebuf.test.cc:48
gem5::minor::Fetch1::Fetch1
Fetch1(const std::string &name_, MinorCPU &cpu_, const MinorCPUParams &params, Latch< BranchData >::Output inp_, Latch< ForwardLineData >::Input out_, Latch< BranchData >::Output prediction_, std::vector< InputBuffer< ForwardLineData >> &next_stage_input_buffer)
Definition: fetch1.cc:60
gem5::minor::InstId
Id for lines and instructions.
Definition: dyn_inst.hh:76
gem5::minor::Fetch1::FetchRequest::reportData
void reportData(std::ostream &os) const
Report interface.
Definition: fetch1.cc:742
gem5::minor::Fetch1::FetchRequest::id
InstId id
Identity of the line that this request will generate.
Definition: fetch1.hh:130
gem5::auxv::Random
@ Random
Definition: aux_vector.hh:89
gem5::minor::Fetch1::minorTraceResponseLine
void minorTraceResponseLine(const std::string &name, FetchRequestPtr response) const
Print the appropriate MinorLine line for a fetch response.
Definition: fetch1.cc:394
gem5::minor::ForwardLineData::isBubble
bool isBubble() const
Definition: pipe_data.hh:245
gem5::minor::Fetch1::lineSeqNum
InstSeqNum lineSeqNum
Sequence number for line fetch used for ordering lines to flush.
Definition: fetch1.hh:315
gem5::Packet::pushSenderState
void pushSenderState(SenderState *sender_state)
Push a new sender state to the packet and make the current sender state the predecessor of the new on...
Definition: packet.cc:316
gem5::BaseMMU::Mode
Mode
Definition: mmu.hh:53
gem5::minor::Fetch1::FetchState
FetchState
Cycle-by-cycle state.
Definition: fetch1.hh:232
gem5::minor::Fetch1::Fetch1ThreadInfo::predictionSeqNum
InstSeqNum predictionSeqNum
Prediction sequence number.
Definition: fetch1.hh:281
gem5::BaseCPU::cacheLineSize
unsigned int cacheLineSize() const
Get the cache line size of the system.
Definition: base.hh:381
gem5::minor::BranchData::reason
Reason reason
Explanation for this branch.
Definition: pipe_data.hh:113
gem5::minor::Fetch1::FetchRequest
Memory access queuing.
Definition: fetch1.hh:107
gem5::minor::Fetch1::popAndDiscard
void popAndDiscard(FetchQueue &queue)
Pop a request from the given queue and correctly deallocate and discard it.
Definition: fetch1.cc:377
gem5::minor::Queue< FetchRequestPtr, ReportTraitsPtrAdaptor< FetchRequestPtr >, NoBubbleTraits< FetchRequestPtr > >
gem5::minor::Fetch1::numFetchesInMemorySystem
unsigned int numFetchesInMemorySystem
Count of the number fetches which have left the transfers queue and are in the 'wild' in the memory s...
Definition: fetch1.hh:321
minor
gem5::minor::Fetch1::updateExpectedSeqNums
void updateExpectedSeqNums(const BranchData &branch)
Update streamSeqNum and predictionSeqNum from the given branch (and assume these have changed and dis...
Definition: fetch1.cc:517
gem5::MinorCPU
MinorCPU is an in-order CPU model with four fixed pipeline stages:
Definition: cpu.hh:85
cast.hh
gem5::minor::Fetch1::FetchRequest::InTranslation
@ InTranslation
Definition: fetch1.hh:121
std::vector
STL vector class.
Definition: stl.hh:37
gem5::minor::Fetch1::prediction
Latch< BranchData >::Output prediction
Input port carrying branch predictions from Fetch2.
Definition: fetch1.hh:205
gem5::minor::Fetch1::Fetch1ThreadInfo::pc
TheISA::PCState pc
Fetch PC value.
Definition: fetch1.hh:270
gem5::minor::Queue::minorTrace
void minorTrace() const
Definition: buffers.hh:512
gem5::minor::Fetch1::transfers
FetchQueue transfers
Queue of in-memory system requests and responses.
Definition: fetch1.hh:309
gem5::minor::Queue::empty
bool empty() const
Is the queue empty?
Definition: buffers.hh:509
gem5::minor::Fetch1::lineSnap
unsigned int lineSnap
Line snap size in bytes.
Definition: fetch1.hh:217
gem5::minor::BranchData::isStreamChange
static bool isStreamChange(const BranchData::Reason reason)
Is a request with this reason actually a request to change the PC rather than a bubble or branch pred...
Definition: pipe_data.cc:85
gem5::MinorCPU::wakeupOnEvent
void wakeupOnEvent(unsigned int stage_id)
Interface for stages to signal that they have become active after a callback or eventq event where th...
Definition: cpu.cc:302
gem5::BaseMMU::Execute
@ Execute
Definition: mmu.hh:53
gem5::ThreadContext::status
virtual Status status() const =0
gem5::MinorCPU::threads
std::vector< minor::MinorThread * > threads
These are thread state-representing objects for this CPU.
Definition: cpu.hh:101
gem5::minor::InputBuffer
Like a Queue but with a restricted interface and a setTail function which, when the queue is empty,...
Definition: buffers.hh:572
gem5::Named
Interface for things with names.
Definition: named.hh:38
gem5::minor::Pipeline::Fetch1StageId
@ Fetch1StageId
Definition: pipeline.hh:104
gem5::BaseCPU::numThreads
ThreadID numThreads
Number of threads we're actually simulating (<= SMT_MAX_THREADS).
Definition: base.hh:368
gem5::minor::Fetch1::icachePort
IcachePort icachePort
IcachePort to pass to the CPU.
Definition: fetch1.hh:212
gem5::minor::Fetch1::handleTLBResponse
void handleTLBResponse(FetchRequestPtr response)
Handle pushing a TLB response onto the right queue.
Definition: fetch1.cc:249
gem5::minor::ForwardLineData::setFault
void setFault(Fault fault_)
Set fault and possible clear the bubble flag.
Definition: pipe_data.cc:167
gem5::minor::Fetch1::FetchRequest::isDiscardable
bool isDiscardable() const
Is this line out of date with the current stream/prediction sequence and can it be discarded without ...
Definition: fetch1.cc:747
gem5::minor::Latch::Output
Definition: buffers.hh:263
gem5::minor::Fetch1::getScheduledThread
ThreadID getScheduledThread()
Use the current threading policy to determine the next thread to fetch from.
Definition: fetch1.cc:120
gem5::minor::Fetch1::nextStageReserve
std::vector< InputBuffer< ForwardLineData > > & nextStageReserve
Interface to reserve space in the next stage.
Definition: fetch1.hh:208
gem5::ThreadContext
ThreadContext is the external interface to all thread state for anything outside of the CPU.
Definition: thread_context.hh:93
gem5::minor::Fetch1::maxLineWidth
unsigned int maxLineWidth
Maximum fetch width in bytes.
Definition: fetch1.hh:223
gem5::Named::name
virtual std::string name() const
Definition: named.hh:47
gem5::Fault
std::shared_ptr< FaultBase > Fault
Definition: types.hh:255
DPRINTF
#define DPRINTF(x,...)
Definition: trace.hh:186
gem5::minor::Fetch1::FetchRequest::fault
Fault fault
Fill in a fault if one happens during fetch, check this by picking apart the response packet.
Definition: fetch1.hh:146
gem5::Packet
A Packet is used to encapsulate a transfer between two objects in the memory system (e....
Definition: packet.hh:283
gem5::minor::Latch::Input
Encapsulate wires on either input or output of the latch.
Definition: buffers.hh:252
gem5::minor::Fetch1::FetchRequest::isComplete
bool isComplete() const
Is this a complete read line or fault.
Definition: fetch1.hh:160
gem5::minor::Fetch1::FetchRequest::~FetchRequest
~FetchRequest()
Definition: fetch1.cc:272
gem5::minor::Fetch1::FetchWaitingForPC
@ FetchWaitingForPC
Definition: fetch1.hh:236
gem5::probing::Packet
ProbePointArg< PacketInfo > Packet
Packet probe point.
Definition: mem.hh:109
gem5::minor::Fetch1::Fetch1ThreadInfo::state
FetchState state
Definition: fetch1.hh:265
gem5::minor::minorLine
void minorLine(const Named &named, const char *fmt, Args ...args)
DPRINTFN for MinorTrace MinorLine line reporting.
Definition: trace.hh:84
gem5::minor::Fetch1::moveFromRequestsToTransfers
void moveFromRequestsToTransfers(FetchRequestPtr request)
Move a request between queues.
Definition: fetch1.cc:318
gem5::minor::Fetch1::tryToSendToTransfers
void tryToSendToTransfers(FetchRequestPtr request)
Try and issue a fetch for a translated request at the head of the requests queue.
Definition: fetch1.cc:279
gem5::BaseCPU::instRequestorId
RequestorID instRequestorId() const
Reads this CPU's unique instruction requestor ID.
Definition: base.hh:196
pipeline.hh
gem5::RequestPtr
std::shared_ptr< Request > RequestPtr
Definition: request.hh:92
gem5::Request::INST_FETCH
@ INST_FETCH
The request was an instruction fetch.
Definition: request.hh:115
gem5::MemCmd::ReadReq
@ ReadReq
Definition: packet.hh:86
gem5::minor::Queue::push
void push(ElemType &data)
Push an element into the buffer if it isn't a bubble.
Definition: buffers.hh:433
gem5::minor::Fetch1::Fetch1ThreadInfo::blocked
bool blocked
Blocked indication for report.
Definition: fetch1.hh:284
gem5::InvalidThreadID
const ThreadID InvalidThreadID
Definition: types.hh:243
gem5::minor::Fetch1::FetchRequest::Complete
@ Complete
Definition: fetch1.hh:124
gem5::minor::Fetch1::FetchRequest::RequestIssuing
@ RequestIssuing
Definition: fetch1.hh:123
compiler.hh
gem5::minor::BranchData
Forward data betwen Execute and Fetch1 carrying change-of-address/stream information.
Definition: pipe_data.hh:66
gem5::ThreadContext::pcState
virtual TheISA::PCState pcState() const =0
gem5::minor::Queue::occupiedSpace
unsigned int occupiedSpace() const
Number of slots already occupied in this buffer.
Definition: buffers.hh:476
gem5::minor::BranchData::target
TheISA::PCState target
Starting PC of that stream.
Definition: pipe_data.hh:123
gem5::BaseCPU::getContext
virtual ThreadContext * getContext(int tn)
Given a thread num get tho thread context for it.
Definition: base.hh:290
gem5::minor::Fetch1::processResponse
void processResponse(FetchRequestPtr response, ForwardLineData &line)
Convert a response to a ForwardLineData.
Definition: fetch1.cc:535
gem5::Packet::needsResponse
bool needsResponse() const
Definition: packet.hh:597
gem5::minor::Fetch1::IcacheState
IcacheState
State of memory access for head instruction fetch.
Definition: fetch1.hh:294
gem5::minor::Fetch1::fetchLimit
unsigned int fetchLimit
Maximum number of fetches allowed in flight (in queues or memory)
Definition: fetch1.hh:226
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::minor::Fetch1::FetchHalted
@ FetchHalted
Definition: fetch1.hh:234
gem5::Packet::isError
bool isError() const
Definition: packet.hh:610
gem5::GEM5_DEPRECATED_NAMESPACE
GEM5_DEPRECATED_NAMESPACE(GuestABI, guest_abi)
gem5::minor::BranchData::isBubble
bool isBubble() const
Definition: pipe_data.hh:152
gem5::minor::Fetch1::changeStream
void changeStream(const BranchData &branch)
Start fetching from a new address.
Definition: fetch1.cc:485
gem5::minor::Fetch1::FetchRequest::state
FetchRequestState state
Definition: fetch1.hh:127
gem5::minor::minorTrace
void minorTrace(const char *fmt, Args ...args)
DPRINTFN for MinorTrace reporting.
Definition: trace.hh:67
gem5::minor::Fetch1::FetchRequest::Translated
@ Translated
Definition: fetch1.hh:122
gem5::minor::Fetch1::FetchRunning
@ FetchRunning
Definition: fetch1.hh:239
gem5::minor::Fetch1::FetchRequest::makePacket
void makePacket()
Make a packet to use with the memory transaction.
Definition: fetch1.cc:224
gem5::Packet::popSenderState
SenderState * popSenderState()
Pop the top of the state stack and return a pointer to it.
Definition: packet.cc:324
gem5::ActivityRecorder::activity
void activity()
Records that there is activity this cycle.
Definition: activity.cc:55
gem5::minor::Fetch1::recvReqRetry
virtual void recvReqRetry()
Definition: fetch1.cc:450
gem5::minor::ForwardLineData::adoptPacketData
void adoptPacketData(Packet *packet)
Use the data from a packet as line instead of allocating new space.
Definition: pipe_data.cc:187
gem5::minor::Fetch1::IcacheRunning
@ IcacheRunning
Definition: fetch1.hh:296
gem5::minor::Fetch1::inp
Latch< BranchData >::Output inp
Input port carrying branch requests from Execute.
Definition: fetch1.hh:201
gem5::minor::Fetch1::wakeupFetch
void wakeupFetch(ThreadID tid)
Initiate fetch1 fetching.
Definition: fetch1.cc:710
gem5::Packet::allocate
void allocate()
Allocate memory for the packet.
Definition: packet.hh:1326
gem5::minor::BranchData::threadId
ThreadID threadId
ThreadID associated with branch.
Definition: pipe_data.hh:116
gem5::X86ISA::os
Bitfield< 17 > os
Definition: misc.hh:809
gem5::minor::Fetch1::recvTimingResp
virtual bool recvTimingResp(PacketPtr pkt)
Memory interface.
Definition: fetch1.cc:413
gem5::minor::Fetch1::Fetch1ThreadInfo
Stage cycle-by-cycle state.
Definition: fetch1.hh:244
gem5::minor::operator<<
std::ostream & operator<<(std::ostream &os, const InstId &id)
Print this id in the usual slash-separated format expected by MinorTrace.
Definition: dyn_inst.cc:65
gem5::minor::Fetch1::cpu
MinorCPU & cpu
Construction-assigned data members.
Definition: fetch1.hh:198
gem5::minor::BranchData::HaltFetch
@ HaltFetch
Definition: pipe_data.hh:99
gem5::minor::Fetch1::numInFlightFetches
unsigned int numInFlightFetches()
Returns the total number of queue occupancy, in-ITLB and in-memory system fetches.
Definition: fetch1.cc:386
gem5::minor::Fetch1::minorTrace
void minorTrace() const
Definition: fetch1.cc:758
logging.hh
gem5::minor::ForwardLineData::lineBaseAddr
Addr lineBaseAddr
First byte address in the line.
Definition: pipe_data.hh:185
gem5::ArmISA::id
Bitfield< 33 > id
Definition: misc_types.hh:250
gem5::minor::Fetch1::FetchRequest::finish
void finish(const Fault &fault_, const RequestPtr &request_, ThreadContext *tc, BaseMMU::Mode mode)
Interface for ITLB responses.
Definition: fetch1.cc:236
gem5::minor::Fetch1::requests
FetchQueue requests
Queue of address translated requests from Fetch1.
Definition: fetch1.hh:306
gem5::minor::Fetch1::stepQueues
void stepQueues()
Step requests along between requests and transfers queues.
Definition: fetch1.cc:355
gem5::minor::Fetch1::tryToSend
bool tryToSend(FetchRequestPtr request)
Try to send (or resend) a memory request's next/only packet to the memory system.
Definition: fetch1.cc:327
gem5::MinorCPU::threadPolicy
enums::ThreadPolicy threadPolicy
Thread Scheduling Policy (RoundRobin, Random, etc)
Definition: cpu.hh:120
trace.hh
gem5::MinorCPU::activityRecorder
minor::MinorActivityRecorder * activityRecorder
Activity recording for pipeline.
Definition: cpu.hh:96
gem5::minor::Fetch1::IcacheNeedsRetry
@ IcacheNeedsRetry
Definition: fetch1.hh:297
gem5::minor::BranchData::SuspendThread
@ SuspendThread
Definition: pipe_data.hh:95
gem5::minor::ForwardLineData::pc
TheISA::PCState pc
PC of the first requested inst within this line.
Definition: pipe_data.hh:188
gem5::minor::Queue::pop
void pop()
Pop the head item.
Definition: buffers.hh:506
gem5::minor::Fetch1::fetchInfo
std::vector< Fetch1ThreadInfo > fetchInfo
Definition: fetch1.hh:290
gem5::minor::Fetch1::evaluate
void evaluate()
Pass on input/buffer data to the output if you can.
Definition: fetch1.cc:569
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40
gem5::minor::Fetch1::FetchRequest::packet
PacketPtr packet
FetchRequests carry packets while they're in the requests and transfers responses queues.
Definition: fetch1.hh:136
gem5::minor::Fetch1::Fetch1ThreadInfo::wakeupGuard
bool wakeupGuard
Signal to guard against sleeping first cycle of wakeup.
Definition: fetch1.hh:287
gem5::minor::Fetch1::FetchRequest::request
RequestPtr request
The underlying request that this fetch represents.
Definition: fetch1.hh:139
gem5::minor::Fetch1::isDrained
bool isDrained()
Is this stage drained? For Fetch1, draining is initiated by Execute signalling a branch with the reas...
Definition: fetch1.cc:724
gem5::minor::BranchData::newPredictionSeqNum
InstSeqNum newPredictionSeqNum
Definition: pipe_data.hh:120
gem5::minor::Fetch1::icacheState
IcacheState icacheState
Retry state of icache_port.
Definition: fetch1.hh:312
gem5::minor::BranchData::newStreamSeqNum
InstSeqNum newStreamSeqNum
Sequence number of new stream/prediction to be adopted.
Definition: pipe_data.hh:119
fetch1.hh
gem5::MinorCPU::roundRobinPriority
std::vector< ThreadID > roundRobinPriority(ThreadID priority)
Thread scheduling utility functions.
Definition: cpu.hh:173
gem5::minor::Fetch1::Fetch1ThreadInfo::streamSeqNum
InstSeqNum streamSeqNum
Stream sequence number.
Definition: fetch1.hh:275
gem5::ThreadID
int16_t ThreadID
Thread index/ID type.
Definition: types.hh:242
gem5::minor::InstId::threadId
ThreadID threadId
The thread to which this line/instruction belongs.
Definition: dyn_inst.hh:89
panic
#define panic(...)
This implements a cprintf based panic() function.
Definition: logging.hh:177
gem5::ArmISA::mode
Bitfield< 4, 0 > mode
Definition: misc_types.hh:73
gem5::minor::Queue::reserve
void reserve()
Reserve space in the queue for future pushes.
Definition: buffers.hh:461

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