clint.hh

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#ifndef __DEV_RISCV_CLINT_HH__
#define __DEV_RISCV_CLINT_HH__
 
#include "arch/riscv/interrupts.hh"
#include "dev/intpin.hh"
#include "dev/io_device.hh"
#include "dev/mc146818.hh"
#include "dev/reg_bank.hh"
#include "mem/packet.hh"
#include "mem/packet_access.hh"
#include "params/Clint.hh"
#include "sim/system.hh"
 
namespace gem5
{
 
using namespace RiscvISA;
 
class Clint : public BasicPioDevice
{
  // Params
  protected:
    System *system;
    int nThread;
    IntSinkPin<Clint> signal;
 
  public:
    typedef ClintParams Params;
    Clint(const Params &params);
 
  // RTC Signal
  public:
    void raiseInterruptPin(int id);
    void lowerInterruptPin(int id) {}
 
  // Register bank
  public:
 
    class ClintRegisters: public RegisterBankLE
    {
      public:
        const Addr mtimecmpStart = 0x4000;
        const Addr mtimeStart = 0xBFF8;
        const Addr maxBankSize = 0xC000;
 
        std::vector<Register32> msip;
        std::vector<Register64> mtimecmp;
        Register64 mtime = {"mtime", 0};
        std::vector<RegisterRaz> reserved;
 
        ClintRegisters(const std::string &name, Addr base, Clint* clint) :
          RegisterBankLE(name, base),
          clint(clint) {}
 
        Clint *clint;
 
        void init();
 
    } registers;
 
    using Register32 = ClintRegisters::Register32;
 
    uint32_t readMSIP(Register32& reg, const int thread_id);
    void writeMSIP(Register32& reg, const uint32_t& data, const int thread_id);
 
  // External API
  public:
    Tick read(PacketPtr pkt) override;
    Tick write(PacketPtr pkt) override;
 
    void init() override;
    Port & getPort(const std::string &if_name,
                   PortID idx=InvalidPortID) override;
    void serialize(CheckpointOut &cp) const override;
    void unserialize(CheckpointIn &cp) override;
 
};
 
} // namespace gem5
 
#endif // __DEV_RISCV_CLINT_HH__