gem5  v22.1.0.0
clint.cc
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37 
38 #include "dev/riscv/clint.hh"
39 
40 #include "cpu/base.hh"
41 #include "debug/Clint.hh"
42 #include "mem/packet.hh"
43 #include "mem/packet_access.hh"
44 #include "params/Clint.hh"
45 #include "sim/system.hh"
46 
47 namespace gem5
48 {
49 
50 using namespace RiscvISA;
51 
52 Clint::Clint(const Params &params) :
53  BasicPioDevice(params, params.pio_size),
54  system(params.system),
55  nThread(params.num_threads),
56  signal(params.name + ".signal", 0, this),
57  registers(params.name + ".registers", params.pio_addr, this)
58 {
59 }
60 
61 void
63 {
64  // Increment mtime
65  uint64_t& mtime = registers.mtime.get();
66  mtime++;
67 
68  for (int context_id = 0; context_id < nThread; context_id++) {
69 
70  auto tc = system->threads[context_id];
71 
72  // Update misc reg file
73  ISA* isa = dynamic_cast<ISA*>(tc->getIsaPtr());
74  isa->setMiscRegNoEffect(MISCREG_TIME, mtime);
75 
76  // Post timer interrupt
77  uint64_t mtimecmp = registers.mtimecmp[context_id].get();
78  if (mtime >= mtimecmp) {
79  if (mtime == mtimecmp) {
80  DPRINTF(Clint,
81  "MTIP posted - thread: %d, mtime: %d, mtimecmp: %d\n",
82  context_id, mtime, mtimecmp);
83  }
84  tc->getCpuPtr()->postInterrupt(tc->threadId(),
86  } else {
87  tc->getCpuPtr()->clearInterrupt(tc->threadId(),
89  }
90  }
91 }
92 
93 void
95 {
96  using namespace std::placeholders;
97 
98  // Calculate reserved space size
99  const size_t reserved0_size = mtimecmpStart - clint->nThread * 4;
100  reserved.emplace_back("reserved0", reserved0_size);
101  const size_t reserved1_size = mtimeStart
102  - mtimecmpStart - clint->nThread * 8;
103  reserved.emplace_back("reserved1", reserved1_size);
104 
105  // Sanity check
106  assert((int) clint->pioSize <= maxBankSize);
107 
108  // Initialize registers
109  for (int i = 0; i < clint->nThread; i++) {
110  msip.emplace_back(std::string("msip") + std::to_string(i), 0);
111  mtimecmp.emplace_back(std::string("mtimecmp") + std::to_string(i), 0);
112  }
113 
114  // Add registers to bank
115  for (int i = 0; i < clint->nThread; i++) {
116  auto read_cb = std::bind(&Clint::readMSIP, clint, _1, i);
117  msip[i].reader(read_cb);
118  auto write_cb = std::bind(&Clint::writeMSIP, clint, _1, _2, i);
119  msip[i].writer(write_cb);
120  addRegister(msip[i]);
121  }
122  addRegister(reserved[0]);
123  for (int i = 0; i < clint->nThread; i++) {
125  }
126  addRegister(reserved[1]);
127  mtime.readonly();
129 }
130 
131 uint32_t
132 Clint::readMSIP(Register32& reg, const int thread_id)
133 {
134  // To avoid discrepancies if mip is externally set using remote_gdb etc.
135  auto tc = system->threads[thread_id];
136  RegVal mip = tc->readMiscReg(MISCREG_IP);
137  uint32_t msip = bits<uint32_t>(mip, ExceptionCode::INT_SOFTWARE_MACHINE);
138  reg.update(msip);
139  return reg.get();
140 };
141 
142 void
143 Clint::writeMSIP(Register32& reg, const uint32_t& data, const int thread_id)
144 {
145  reg.update(data);
146  assert(data <= 1);
147  auto tc = system->threads[thread_id];
148  if (data > 0) {
149  DPRINTF(Clint, "MSIP posted - thread: %d\n", thread_id);
150  tc->getCpuPtr()->postInterrupt(tc->threadId(),
152  } else {
153  DPRINTF(Clint, "MSIP cleared - thread: %d\n", thread_id);
154  tc->getCpuPtr()->clearInterrupt(tc->threadId(),
156  }
157 };
158 
159 Tick
161 {
162  // Check for atomic operation
163  bool is_atomic = pkt->isAtomicOp() && pkt->cmd == MemCmd::SwapReq;
164  DPRINTF(Clint,
165  "Read request - addr: %#x, size: %#x, atomic:%d\n",
166  pkt->getAddr(), pkt->getSize(), is_atomic);
167 
168  // Perform register read
169  registers.read(pkt->getAddr(), pkt->getPtr<void>(), pkt->getSize());
170 
171  if (is_atomic) {
172  // Perform atomic operation
173  (*(pkt->getAtomicOp()))(pkt->getPtr<uint8_t>());
174  return write(pkt);
175  } else {
176  pkt->makeResponse();
177  return pioDelay;
178  }
179 }
180 
181 Tick
183 {
184  DPRINTF(Clint,
185  "Write request - addr: %#x, size: %#x\n",
186  pkt->getAddr(), pkt->getSize());
187 
188  // Perform register write
189  registers.write(pkt->getAddr(), pkt->getPtr<void>(), pkt->getSize());
190 
191  pkt->makeResponse();
192  return pioDelay;
193 }
194 
195 void
197 {
198  registers.init();
200 }
201 
202 Port &
203 Clint::getPort(const std::string &if_name, PortID idx)
204 {
205  if (if_name == "int_pin")
206  return signal;
207  else
208  return BasicPioDevice::getPort(if_name, idx);
209 }
210 
211 void
213 {
214  for (auto const &reg: registers.msip) {
215  paramOut(cp, reg.name(), reg);
216  }
217  for (auto const &reg: registers.mtimecmp) {
218  paramOut(cp, reg.name(), reg);
219  }
220  paramOut(cp, "mtime", registers.mtime);
221 }
222 
223 void
225 {
226  for (auto &reg: registers.msip) {
227  paramIn(cp, reg.name(), reg);
228  }
229  for (auto &reg: registers.mtimecmp) {
230  paramIn(cp, reg.name(), reg);
231  }
232  paramIn(cp, "mtime", registers.mtime);
233 }
234 
235 } // namespace gem5
#define DPRINTF(x,...)
Definition: trace.hh:186
const char data[]
void setMiscRegNoEffect(RegIndex idx, RegVal val) override
Definition: isa.cc:1052
Tick pioDelay
Delay that the device experinces on an access.
Definition: io_device.hh:157
Addr pioSize
Size that the device's address range.
Definition: io_device.hh:154
const Addr mtimecmpStart
Definition: clint.hh:106
std::vector< Register64 > mtimecmp
Definition: clint.hh:111
std::vector< RegisterRaz > reserved
Definition: clint.hh:113
std::vector< Register32 > msip
Definition: clint.hh:110
NOTE: This implementation of CLINT is based on the SiFive U54MC datasheet: https://sifive....
Definition: clint.hh:71
void raiseInterruptPin(int id)
Timer tick callback.
Definition: clint.cc:62
Clint(const Params &params)
Definition: clint.cc:52
Port & getPort(const std::string &if_name, PortID idx=InvalidPortID) override
Get a port with a given name and index.
Definition: clint.cc:203
System * system
Definition: clint.hh:74
void init() override
SimObject functions.
Definition: clint.cc:196
int nThread
Definition: clint.hh:75
Tick write(PacketPtr pkt) override
Pure virtual function that the device must implement.
Definition: clint.cc:182
ClintRegisters::Register32 Register32
Definition: clint.hh:125
IntSinkPin< Clint > signal
Definition: clint.hh:76
void writeMSIP(Register32 &reg, const uint32_t &data, const int thread_id)
Definition: clint.cc:143
gem5::Clint::ClintRegisters registers
void unserialize(CheckpointIn &cp) override
Unserialize an object.
Definition: clint.cc:224
Tick read(PacketPtr pkt) override
PioDevice interface functions.
Definition: clint.cc:160
void serialize(CheckpointOut &cp) const override
Serialize an object.
Definition: clint.cc:212
uint32_t readMSIP(Register32 &reg, const int thread_id)
Definition: clint.cc:132
A Packet is used to encapsulate a transfer between two objects in the memory system (e....
Definition: packet.hh:294
T * getPtr()
get a pointer to the data ptr.
Definition: packet.hh:1212
Addr getAddr() const
Definition: packet.hh:805
AtomicOpFunctor * getAtomicOp() const
Accessor function to atomic op.
Definition: packet.hh:843
bool isAtomicOp() const
Definition: packet.hh:844
void makeResponse()
Take a request packet and modify it in place to be suitable for returning as a response to that reque...
Definition: packet.hh:1059
unsigned getSize() const
Definition: packet.hh:815
MemCmd cmd
The command field of the packet.
Definition: packet.hh:371
Port & getPort(const std::string &if_name, PortID idx=InvalidPortID) override
Get a port with a given name and index.
Definition: io_device.cc:67
PioDeviceParams Params
Definition: io_device.hh:134
void init() override
init() is called after all C++ SimObjects have been created and all ports are connected.
Definition: io_device.cc:59
Ports are used to interface objects to each other.
Definition: port.hh:62
void addRegister(RegisterBase &reg)
Definition: reg_bank.hh:820
virtual void read(Addr addr, void *buf, Addr bytes)
Definition: reg_bank.hh:827
virtual void write(Addr addr, const void *buf, Addr bytes)
Definition: reg_bank.hh:884
Threads threads
Definition: system.hh:313
Bitfield< 7 > i
Definition: misc_types.hh:67
@ MISCREG_IP
Definition: misc.hh:74
@ MISCREG_TIME
Definition: misc.hh:77
@ INT_TIMER_MACHINE
Definition: faults.hh:92
@ INT_SOFTWARE_MACHINE
Definition: faults.hh:89
Bitfield< 5, 3 > reg
Definition: types.hh:92
Bitfield< 15 > system
Definition: misc.hh:1004
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
std::ostream CheckpointOut
Definition: serialize.hh:66
void paramOut(CheckpointOut &cp, const std::string &name, ExtMachInst const &machInst)
Definition: types.cc:40
void paramIn(CheckpointIn &cp, const std::string &name, ExtMachInst &machInst)
Definition: types.cc:72
int16_t PortID
Port index/ID type, and a symbolic name for an invalid port id.
Definition: types.hh:245
uint64_t Tick
Tick count type.
Definition: types.hh:58
uint64_t RegVal
Definition: types.hh:173
const std::string to_string(sc_enc enc)
Definition: sc_fxdefs.cc:60
Declaration of the Packet class.
const std::string & name()
Definition: trace.cc:49

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