base.hh

Go to the documentation of this file.

/*
 * Copyright (c) 2012-2013, 2016-2020 ARM Limited
 * All rights reserved
 *
 * The license below extends only to copyright in the software and shall
 * not be construed as granting a license to any other intellectual
 * property including but not limited to intellectual property relating
 * to a hardware implementation of the functionality of the software
 * licensed hereunder.  You may use the software subject to the license
 * terms below provided that you ensure that this notice is replicated
 * unmodified and in its entirety in all distributions of the software,
 * modified or unmodified, in source code or in binary form.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions are
 * met: redistributions of source code must retain the above copyright
 * notice, this list of conditions and the following disclaimer;
 * redistributions in binary form must reproduce the above copyright
 * notice, this list of conditions and the following disclaimer in the
 * documentation and/or other materials provided with the distribution;
 * neither the name of the copyright holders nor the names of its
 * contributors may be used to endorse or promote products derived from
 * this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */
 
#ifndef __CPU_TRAFFIC_GEN_BASE_HH__
#define __CPU_TRAFFIC_GEN_BASE_HH__
 
#include <memory>
#include <tuple>
#include <unordered_map>
 
#include "base/statistics.hh"
#include "enums/AddrMap.hh"
#include "mem/qport.hh"
#include "sim/clocked_object.hh"
 
namespace gem5
{
 
class BaseGen;
class StreamGen;
class System;
struct BaseTrafficGenParams;
 
class BaseTrafficGen : public ClockedObject
{
    friend class BaseGen;
 
  protected: // Params
    System *const system;
 
    const bool elasticReq;
 
    const Tick progressCheck;
 
  private:
    void recvReqRetry();
 
    void retryReq();
 
    bool recvTimingResp(PacketPtr pkt);
 
    void transition();
 
    void scheduleUpdate();
 
    void noProgress();
 
    EventFunctionWrapper noProgressEvent;
 
    Tick nextTransitionTick;
 
    Tick nextPacketTick;
 
    const int maxOutstandingReqs;
 
 
    class TrafficGenPort : public RequestPort
    {
      public:
 
        TrafficGenPort(const std::string& name, BaseTrafficGen& traffic_gen)
            : RequestPort(name, &traffic_gen), trafficGen(traffic_gen)
        { }
 
      protected:
 
        void recvReqRetry() { trafficGen.recvReqRetry(); }
 
        bool recvTimingResp(PacketPtr pkt)
        { return trafficGen.recvTimingResp(pkt); }
 
        void recvTimingSnoopReq(PacketPtr pkt) { }
 
        void recvFunctionalSnoop(PacketPtr pkt) { }
 
        Tick recvAtomicSnoop(PacketPtr pkt) { return 0; }
 
      private:
 
        BaseTrafficGen& trafficGen;
 
    };
 
    void update();
 
    TrafficGenPort port;
 
    PacketPtr retryPkt;
 
    Tick retryPktTick;
 
    bool blockedWaitingResp;
 
    bool allocateWaitingRespSlot(PacketPtr pkt)
    {
        assert(waitingResp.find(pkt->req) == waitingResp.end());
        assert(pkt->needsResponse());
 
        waitingResp[pkt->req] = curTick();
 
        return (maxOutstandingReqs > 0) &&
               (waitingResp.size() > maxOutstandingReqs);
    }
 
    EventFunctionWrapper updateEvent;
 
  protected: // Stats
    std::unordered_map<RequestPtr,Tick> waitingResp;
 
    struct StatGroup : public statistics::Group
    {
        StatGroup(statistics::Group *parent);
 
        statistics::Scalar numSuppressed;
 
        statistics::Scalar numPackets;
 
        statistics::Scalar numRetries;
 
        statistics::Scalar retryTicks;
 
        statistics::Scalar bytesRead;
 
        statistics::Scalar bytesWritten;
 
        statistics::Scalar totalReadLatency;
 
        statistics::Scalar totalWriteLatency;
 
        statistics::Scalar totalReads;
 
        statistics::Scalar totalWrites;
 
        statistics::Formula avgReadLatency;
 
        statistics::Formula avgWriteLatency;
 
        statistics::Formula readBW;
 
        statistics::Formula writeBW;
    } stats;
 
  public:
    BaseTrafficGen(const BaseTrafficGenParams &p);
 
    ~BaseTrafficGen();
 
    Port &getPort(const std::string &if_name,
                  PortID idx=InvalidPortID) override;
 
    void init() override;
 
    DrainState drain() override;
 
    void serialize(CheckpointOut &cp) const override;
    void unserialize(CheckpointIn &cp) override;
 
  public: // Generator factory methods
    std::shared_ptr<BaseGen> createIdle(Tick duration);
    std::shared_ptr<BaseGen> createExit(Tick duration);
 
    std::shared_ptr<BaseGen> createLinear(
        Tick duration,
        Addr start_addr, Addr end_addr, Addr blocksize,
        Tick min_period, Tick max_period,
        uint8_t read_percent, Addr data_limit);
 
    std::shared_ptr<BaseGen> createRandom(
        Tick duration,
        Addr start_addr, Addr end_addr, Addr blocksize,
        Tick min_period, Tick max_period,
        uint8_t read_percent, Addr data_limit);
 
    std::shared_ptr<BaseGen> createDram(
        Tick duration,
        Addr start_addr, Addr end_addr, Addr blocksize,
        Tick min_period, Tick max_period,
        uint8_t read_percent, Addr data_limit,
        unsigned int num_seq_pkts, unsigned int page_size,
        unsigned int nbr_of_banks, unsigned int nbr_of_banks_util,
        enums::AddrMap addr_mapping,
        unsigned int nbr_of_ranks);
 
    std::shared_ptr<BaseGen> createDramRot(
        Tick duration,
        Addr start_addr, Addr end_addr, Addr blocksize,
        Tick min_period, Tick max_period,
        uint8_t read_percent, Addr data_limit,
        unsigned int num_seq_pkts, unsigned int page_size,
        unsigned int nbr_of_banks, unsigned int nbr_of_banks_util,
        enums::AddrMap addr_mapping,
        unsigned int nbr_of_ranks,
        unsigned int max_seq_count_per_rank);
 
    std::shared_ptr<BaseGen> createHybrid(
        Tick duration,
        Addr start_addr_dram, Addr end_addr_dram, Addr blocksize_dram,
        Addr start_addr_nvm, Addr end_addr_nvm, Addr blocksize_nvm,
        Tick min_period, Tick max_period,
        uint8_t read_percent, Addr data_limit,
        unsigned int num_seq_pkts_dram, unsigned int page_size_dram,
        unsigned int nbr_of_banks_dram, unsigned int nbr_of_banks_util_dram,
        unsigned int num_seq_pkts_nvm, unsigned int buffer_size_nvm,
        unsigned int nbr_of_banks_nvm, unsigned int nbr_of_banks_util_nvm,
        enums::AddrMap addr_mapping,
        unsigned int nbr_of_ranks_dram,
        unsigned int nbr_of_ranks_nvm,
        uint8_t nvm_percent);
 
    std::shared_ptr<BaseGen> createNvm(
        Tick duration,
        Addr start_addr, Addr end_addr, Addr blocksize,
        Tick min_period, Tick max_period,
        uint8_t read_percent, Addr data_limit,
        unsigned int num_seq_pkts, unsigned int buffer_size,
        unsigned int nbr_of_banks, unsigned int nbr_of_banks_util,
        enums::AddrMap addr_mapping,
        unsigned int nbr_of_ranks);
 
    std::shared_ptr<BaseGen> createStrided(
        Tick duration,
        Addr start_addr, Addr end_addr, Addr blocksize,
        Addr stride_size, int gen_id,
        Tick min_period, Tick max_period,
        uint8_t read_percent, Addr data_limit);
 
    std::shared_ptr<BaseGen> createTrace(
        Tick duration,
        const std::string& trace_file, Addr addr_offset);
 
  protected:
    void start();
 
    virtual std::shared_ptr<BaseGen> nextGenerator() = 0;
 
    const RequestorID requestorId;
 
    std::shared_ptr<BaseGen> activeGenerator;
 
    std::unique_ptr<StreamGen> streamGenerator;
};
 
} // namespace gem5
 
#endif //__CPU_TRAFFIC_GEN_BASE_HH__