gem5  v21.1.0.2
dramsim2.hh
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37 
42 #ifndef __MEM_DRAMSIM2_HH__
43 #define __MEM_DRAMSIM2_HH__
44 
45 #include <queue>
46 #include <unordered_map>
47 
48 #include "mem/abstract_mem.hh"
49 #include "mem/dramsim2_wrapper.hh"
50 #include "mem/qport.hh"
51 #include "params/DRAMSim2.hh"
52 
53 namespace gem5
54 {
55 
56 namespace memory
57 {
58 
59 class DRAMSim2 : public AbstractMemory
60 {
61  private:
62 
68  class MemoryPort : public ResponsePort
69  {
70 
71  private:
72 
74 
75  public:
76 
77  MemoryPort(const std::string& _name, DRAMSim2& _memory);
78 
79  protected:
80 
82 
83  void recvFunctional(PacketPtr pkt);
84 
85  bool recvTimingReq(PacketPtr pkt);
86 
87  void recvRespRetry();
88 
90 
91  };
92 
94 
99 
103  bool retryReq;
104 
108  bool retryResp;
109 
114 
121  std::unordered_map<Addr, std::queue<PacketPtr> > outstandingReads;
122  std::unordered_map<Addr, std::queue<PacketPtr> > outstandingWrites;
123 
129  unsigned int nbrOutstandingReads;
130  unsigned int nbrOutstandingWrites;
131 
138 
139  unsigned int nbrOutstanding() const;
140 
148  void accessAndRespond(PacketPtr pkt);
149 
150  void sendResponse();
151 
156 
160  void tick();
161 
166 
171  std::unique_ptr<Packet> pendingDelete;
172 
173  public:
174 
175  typedef DRAMSim2Params Params;
176  DRAMSim2(const Params &p);
177 
185  void readComplete(unsigned id, uint64_t addr, uint64_t cycle);
186 
194  void writeComplete(unsigned id, uint64_t addr, uint64_t cycle);
195 
196  DrainState drain() override;
197 
198  Port &getPort(const std::string &if_name,
199  PortID idx=InvalidPortID) override;
200 
201  void init() override;
202  void startup() override;
203 
204  protected:
205 
207  void recvFunctional(PacketPtr pkt);
208  bool recvTimingReq(PacketPtr pkt);
209  void recvRespRetry();
210 
211 };
212 
213 } // namespace memory
214 } // namespace gem5
215 
216 #endif // __MEM_DRAMSIM2_HH__
dramsim2_wrapper.hh
gem5::Clocked::cycle
Cycles cycle
Definition: clocked_object.hh:72
gem5::PortID
int16_t PortID
Port index/ID type, and a symbolic name for an invalid port id.
Definition: types.hh:252
gem5::memory::DRAMSim2::recvFunctional
void recvFunctional(PacketPtr pkt)
Definition: dramsim2.cc:167
gem5::memory::DRAMSim2::MemoryPort::recvFunctional
void recvFunctional(PacketPtr pkt)
Receive a functional request packet from the peer.
Definition: dramsim2.cc:380
gem5::memory::DRAMSim2::startup
void startup() override
startup() is the final initialization call before simulation.
Definition: dramsim2.cc:97
gem5::memory::DRAMSim2::recvRespRetry
void recvRespRetry()
Definition: dramsim2.cc:244
gem5::memory::DRAMSim2::nbrOutstandingReads
unsigned int nbrOutstandingReads
Count the number of outstanding transactions so that we can block any further requests until there is...
Definition: dramsim2.hh:129
memory
Definition: mem.h:38
abstract_mem.hh
gem5::memory::DRAMSim2::retryResp
bool retryResp
Are we waiting for a retry for sending a response.
Definition: dramsim2.hh:108
gem5::memory::DRAMSim2Wrapper
Wrapper class to avoid having DRAMSim2 names like ClockDomain etc clashing with the normal gem5 world...
Definition: dramsim2_wrapper.hh:73
gem5::memory::DRAMSim2::MemoryPort::mem
DRAMSim2 & mem
Definition: dramsim2.hh:73
gem5::memory::DRAMSim2::responseQueue
std::deque< PacketPtr > responseQueue
Queue to hold response packets until we can send them back.
Definition: dramsim2.hh:137
gem5::memory::DRAMSim2::Params
DRAMSim2Params Params
Definition: dramsim2.hh:175
gem5::memory::DRAMSim2::DRAMSim2
DRAMSim2(const Params &p)
Definition: dramsim2.cc:53
gem5::memory::DRAMSim2::nbrOutstanding
unsigned int nbrOutstanding() const
Definition: dramsim2.cc:136
gem5::InvalidPortID
const PortID InvalidPortID
Definition: types.hh:253
gem5::memory::DRAMSim2::nbrOutstandingWrites
unsigned int nbrOutstandingWrites
Definition: dramsim2.hh:130
gem5::memory::DRAMSim2::readComplete
void readComplete(unsigned id, uint64_t addr, uint64_t cycle)
Read completion callback.
Definition: dramsim2.cc:290
gem5::memory::DRAMSim2::getPort
Port & getPort(const std::string &if_name, PortID idx=InvalidPortID) override
Get a port with a given name and index.
Definition: dramsim2.cc:343
gem5::memory::DRAMSim2::tick
void tick()
Progress the controller one clock cycle.
Definition: dramsim2.cc:142
gem5::memory::DRAMSim2::retryReq
bool retryReq
Is the connected port waiting for a retry from us.
Definition: dramsim2.hh:103
gem5::DrainState
DrainState
Object drain/handover states.
Definition: drain.hh:74
gem5::memory::DRAMSim2::tickEvent
EventFunctionWrapper tickEvent
Event to schedule clock ticks.
Definition: dramsim2.hh:165
gem5::memory::DRAMSim2::sendResponseEvent
EventFunctionWrapper sendResponseEvent
Event to schedule sending of responses.
Definition: dramsim2.hh:155
gem5::memory::DRAMSim2::writeComplete
void writeComplete(unsigned id, uint64_t addr, uint64_t cycle)
Write completion callback.
Definition: dramsim2.cc:318
gem5::memory::DRAMSim2::sendResponse
void sendResponse()
Definition: dramsim2.cc:106
gem5::memory::DRAMSim2::outstandingReads
std::unordered_map< Addr, std::queue< PacketPtr > > outstandingReads
Keep track of what packets are outstanding per address, and do so separately for reads and writes.
Definition: dramsim2.hh:121
gem5::Packet
A Packet is used to encapsulate a transfer between two objects in the memory system (e....
Definition: packet.hh:283
gem5::memory::DRAMSim2::MemoryPort::recvAtomic
Tick recvAtomic(PacketPtr pkt)
Receive an atomic request packet from the peer.
Definition: dramsim2.cc:374
gem5::MipsISA::p
Bitfield< 0 > p
Definition: pra_constants.hh:326
gem5::memory::AbstractMemory
An abstract memory represents a contiguous block of physical memory, with an associated address range...
Definition: abstract_mem.hh:110
gem5::Tick
uint64_t Tick
Tick count type.
Definition: types.hh:58
gem5::memory::DRAMSim2::recvAtomic
Tick recvAtomic(PacketPtr pkt)
Definition: dramsim2.cc:158
gem5::memory::DRAMSim2::port
MemoryPort port
Definition: dramsim2.hh:93
gem5::memory::DRAMSim2::MemoryPort
The memory port has to deal with its own flow control to avoid having unbounded storage that is impli...
Definition: dramsim2.hh:68
gem5::memory::DRAMSim2::drain
DrainState drain() override
Draining is the process of clearing out the states of SimObjects.These are the SimObjects that are pa...
Definition: dramsim2.cc:353
gem5::EventFunctionWrapper
Definition: eventq.hh:1115
gem5::ResponsePort
A ResponsePort is a specialization of a port.
Definition: port.hh:268
gem5::memory::DRAMSim2::wrapper
DRAMSim2Wrapper wrapper
The actual DRAMSim2 wrapper.
Definition: dramsim2.hh:98
gem5::Port
Ports are used to interface objects to each other.
Definition: port.hh:61
qport.hh
std::deque
STL deque class.
Definition: stl.hh:44
gem5::memory::DRAMSim2::pendingDelete
std::unique_ptr< Packet > pendingDelete
Upstream caches need this packet until true is returned, so hold it for deletion until a subsequent c...
Definition: dramsim2.hh:171
gem5::memory::DRAMSim2::MemoryPort::getAddrRanges
AddrRangeList getAddrRanges() const
Get a list of the non-overlapping address ranges the owner is responsible for.
Definition: dramsim2.cc:366
gem5::memory::DRAMSim2::init
void init() override
init() is called after all C++ SimObjects have been created and all ports are connected.
Definition: dramsim2.cc:81
gem5::memory::DRAMSim2::recvTimingReq
bool recvTimingReq(PacketPtr pkt)
Definition: dramsim2.cc:181
std::list< AddrRange >
gem5::memory::DRAMSim2::outstandingWrites
std::unordered_map< Addr, std::queue< PacketPtr > > outstandingWrites
Definition: dramsim2.hh:122
gem5::memory::DRAMSim2::MemoryPort::recvRespRetry
void recvRespRetry()
Called by the peer if sendTimingResp was called on this protocol (causing recvTimingResp to be called...
Definition: dramsim2.cc:393
gem5::memory::DRAMSim2::MemoryPort::recvTimingReq
bool recvTimingReq(PacketPtr pkt)
Receive a timing request from the peer.
Definition: dramsim2.cc:386
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40
gem5::memory::DRAMSim2::MemoryPort::MemoryPort
MemoryPort(const std::string &_name, DRAMSim2 &_memory)
Definition: dramsim2.cc:360
gem5::memory::DRAMSim2::startTick
Tick startTick
Keep track of when the wrapper is started.
Definition: dramsim2.hh:113
gem5::Named::_name
const std::string _name
Definition: named.hh:41
gem5::memory::DRAMSim2::accessAndRespond
void accessAndRespond(PacketPtr pkt)
When a packet is ready, use the "access()" method in AbstractMemory to actually create the response p...
Definition: dramsim2.cc:254
gem5::memory::DRAMSim2
Definition: dramsim2.hh:59
gem5::X86ISA::addr
Bitfield< 3 > addr
Definition: types.hh:84

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