gem5  v22.0.0.2
emulenv.cc
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37 
38 #include "arch/x86/emulenv.hh"
39 
40 #include <cassert>
41 
42 #include "base/logging.hh"
43 
44 namespace gem5
45 {
46 
47 using namespace X86ISA;
48 
49 void EmulEnv::doModRM(const ExtMachInst & machInst)
50 {
51  assert(machInst.modRM.mod != 3);
52  //Use the SIB byte for addressing if the modrm byte calls for it.
53  if (machInst.modRM.rm == 4 && machInst.addrSize != 2) {
54  scale = 1 << machInst.sib.scale;
55  index = RegId(IntRegClass, machInst.sib.index | (machInst.rex.x << 3));
56  base = RegId(IntRegClass, machInst.sib.base | (machInst.rex.b << 3));
57  //In this special case, we don't use a base. The displacement also
58  //changes, but that's managed by the decoder.
59  if (machInst.sib.base == (RegIndex)int_reg::Rbp &&
60  machInst.modRM.mod == 0)
61  base = int_reg::T0;
62  //In -this- special case, we don't use an index.
63  if (index == int_reg::Rsp)
64  index = int_reg::T0;
65  } else {
66  if (machInst.addrSize == 2) {
67  unsigned rm = machInst.modRM.rm;
68  if (rm <= 3) {
69  scale = 1;
70  if (rm < 2) {
71  base = int_reg::Rbx;
72  } else {
73  base = int_reg::Rbp;
74  }
76  (rm % 2) ? int_reg::Rdi : int_reg::Rsi);
77  } else {
78  scale = 0;
79  switch (rm) {
80  case 4:
81  base = int_reg::Rsi;
82  break;
83  case 5:
84  base = int_reg::Rdi;
85  break;
86  case 6:
87  // There is a special case when mod is 0 and rm is 6.
88  base = machInst.modRM.mod == 0 ? int_reg::T0 :
89  int_reg::Rbp;
90  break;
91  case 7:
92  base = int_reg::Rbx;
93  break;
94  }
95  }
96  } else {
97  scale = 0;
99  machInst.modRM.rm | (machInst.rex.b << 3));
100  if (machInst.modRM.mod == 0 && machInst.modRM.rm == 5) {
101  //Since we need to use a different encoding of this
102  //instruction anyway, just ignore the base in those cases
103  base = int_reg::T0;
104  }
105  }
106  }
107  //Figure out what segment to use.
108  if (base != int_reg::Rbp && base != int_reg::Rsp) {
110  } else {
112  }
113  //Handle any segment override that might have been in the instruction
114  int segFromInst = machInst.legacy.seg;
115  if (segFromInst)
116  seg = segFromInst - 1;
117 }
118 
119 void EmulEnv::setSeg(const ExtMachInst & machInst)
120 {
122  //Handle any segment override that might have been in the instruction
123  int segFromInst = machInst.legacy.seg;
124  if (segFromInst)
125  seg = segFromInst - 1;
126 }
127 
128 } // namespace gem5
gem5::X86ISA::rm
Bitfield< 2, 0 > rm
Definition: types.hh:93
gem5::X86ISA::segment_idx::Ds
@ Ds
Definition: segment.hh:53
gem5::X86ISA::ExtMachInst::modRM
ModRM modRM
Definition: types.hh:229
gem5::X86ISA::EmulEnv::scale
uint8_t scale
Definition: emulenv.hh:55
gem5::X86ISA::EmulEnv::index
RegId index
Definition: emulenv.hh:56
gem5::X86ISA::EmulEnv::doModRM
void doModRM(const ExtMachInst &machInst)
Definition: emulenv.cc:49
gem5::X86ISA::ExtMachInst::rex
Rex rex
Definition: types.hh:218
gem5::X86ISA::ExtMachInst::legacy
LegacyPrefixVector legacy
Definition: types.hh:217
gem5::X86ISA::ExtMachInst::addrSize
uint8_t addrSize
Definition: types.hh:238
gem5::X86ISA::EmulEnv::base
RegId base
Definition: emulenv.hh:57
gem5::X86ISA::segment_idx::Ss
@ Ss
Definition: segment.hh:52
gem5::X86ISA::ExtMachInst::sib
Sib sib
Definition: types.hh:230
gem5::X86ISA::ExtMachInst
Definition: types.hh:212
gem5::IntRegClass
@ IntRegClass
Integer register.
Definition: reg_class.hh:58
gem5::X86ISA::EmulEnv::seg
int seg
Definition: emulenv.hh:54
emulenv.hh
gem5::X86ISA::EmulEnv::setSeg
void setSeg(const ExtMachInst &machInst)
Definition: emulenv.cc:119
logging.hh
gem5::RegIndex
uint16_t RegIndex
Definition: types.hh:176
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: gpu_translation_state.hh:37
gem5::RegId
Register ID: describe an architectural register with its class and index.
Definition: reg_class.hh:126

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