gem5  v21.1.0.2
emulenv.cc
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37 
38 #include "arch/x86/emulenv.hh"
39 
40 #include <cassert>
41 
42 #include "base/logging.hh"
43 
44 namespace gem5
45 {
46 
47 using namespace X86ISA;
48 
49 void EmulEnv::doModRM(const ExtMachInst & machInst)
50 {
51  assert(machInst.modRM.mod != 3);
52  //Use the SIB byte for addressing if the modrm byte calls for it.
53  if (machInst.modRM.rm == 4 && machInst.addrSize != 2) {
54  scale = 1 << machInst.sib.scale;
55  index = machInst.sib.index | (machInst.rex.x << 3);
56  base = machInst.sib.base | (machInst.rex.b << 3);
57  //In this special case, we don't use a base. The displacement also
58  //changes, but that's managed by the decoder.
59  if (machInst.sib.base == INTREG_RBP && machInst.modRM.mod == 0)
60  base = INTREG_T0;
61  //In -this- special case, we don't use an index.
62  if (index == INTREG_RSP)
63  index = INTREG_T0;
64  } else {
65  if (machInst.addrSize == 2) {
66  unsigned rm = machInst.modRM.rm;
67  if (rm <= 3) {
68  scale = 1;
69  if (rm < 2) {
70  base = INTREG_RBX;
71  } else {
72  base = INTREG_RBP;
73  }
74  index = (rm % 2) ? INTREG_RDI : INTREG_RSI;
75  } else {
76  scale = 0;
77  switch (rm) {
78  case 4:
79  base = INTREG_RSI;
80  break;
81  case 5:
82  base = INTREG_RDI;
83  break;
84  case 6:
85  base = INTREG_RBP;
86  break;
87  case 7:
88  base = INTREG_RBX;
89  break;
90  }
91  }
92  } else {
93  scale = 0;
94  base = machInst.modRM.rm | (machInst.rex.b << 3);
95  if (machInst.modRM.mod == 0 && machInst.modRM.rm == 5) {
96  //Since we need to use a different encoding of this
97  //instruction anyway, just ignore the base in those cases
98  base = INTREG_T0;
99  }
100  }
101  }
102  //Figure out what segment to use. This won't be entirely accurate since
103  //the presence of a displacement is supposed to make the instruction
104  //default to the data segment.
105  if ((base != INTREG_RBP && base != INTREG_RSP) || machInst.dispSize) {
107  //Handle any segment override that might have been in the instruction
108  int segFromInst = machInst.legacy.seg;
109  if (segFromInst)
110  seg = (SegmentRegIndex)(segFromInst - 1);
111  } else {
113  }
114 }
115 
116 void EmulEnv::setSeg(const ExtMachInst & machInst)
117 {
119  //Handle any segment override that might have been in the instruction
120  int segFromInst = machInst.legacy.seg;
121  if (segFromInst)
122  seg = (SegmentRegIndex)(segFromInst - 1);
123 }
124 
125 } // namespace gem5
gem5::X86ISA::rm
Bitfield< 2, 0 > rm
Definition: types.hh:93
gem5::X86ISA::ExtMachInst::modRM
ModRM modRM
Definition: types.hh:223
gem5::X86ISA::SegmentRegIndex
SegmentRegIndex
Definition: segment.hh:46
gem5::X86ISA::EmulEnv::scale
uint8_t scale
Definition: emulenv.hh:55
gem5::X86ISA::EmulEnv::doModRM
void doModRM(const ExtMachInst &machInst)
Definition: emulenv.cc:49
gem5::X86ISA::ExtMachInst::rex
Rex rex
Definition: types.hh:212
gem5::X86ISA::EmulEnv::index
RegIndex index
Definition: emulenv.hh:56
gem5::X86ISA::ExtMachInst::legacy
LegacyPrefixVector legacy
Definition: types.hh:211
gem5::X86ISA::ExtMachInst::addrSize
uint8_t addrSize
Definition: types.hh:232
gem5::X86ISA::SEGMENT_REG_DS
@ SEGMENT_REG_DS
Definition: segment.hh:51
gem5::X86ISA::SEGMENT_REG_SS
@ SEGMENT_REG_SS
Definition: segment.hh:50
gem5::X86ISA::ExtMachInst::dispSize
uint8_t dispSize
Definition: types.hh:236
gem5::X86ISA::ExtMachInst::sib
Sib sib
Definition: types.hh:224
gem5::X86ISA::ExtMachInst
Definition: types.hh:206
emulenv.hh
gem5::X86ISA::EmulEnv::setSeg
void setSeg(const ExtMachInst &machInst)
Definition: emulenv.cc:116
logging.hh
gem5::X86ISA::EmulEnv::base
RegIndex base
Definition: emulenv.hh:57
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40
gem5::X86ISA::EmulEnv::seg
SegmentRegIndex seg
Definition: emulenv.hh:54

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