gem5  v22.1.0.0
Classes | Public Member Functions | Static Public Attributes | Private Attributes | List of all members
gem5::FetchUnit Class Reference

#include <fetch_unit.hh>


class  FetchBufDesc
 fetch buffer descriptor. More...
class  SystemHubEvent

Public Member Functions

 FetchUnit (const ComputeUnitParams &p, ComputeUnit &cu)
 ~FetchUnit ()
void init ()
void exec ()
void bindWaveList (std::vector< Wavefront * > *list)
void initiateFetch (Wavefront *wavefront)
void fetch (PacketPtr pkt, Wavefront *wavefront)
void processFetchReturn (PacketPtr pkt)
void flushBuf (int wfSlotId)

Static Public Attributes

static uint32_t globalFetchUnitID

Private Attributes

bool timingSim
TheGpuISA::Decoder decoder
Scheduler fetchScheduler
std::vector< Wavefront * > fetchQueue
std::vector< std::pair< Wavefront *, bool > > fetchStatusQueue
std::vector< Wavefront * > * waveList
std::vector< FetchBufDescfetchBuf
int fetchDepth
 number of cache lines we can fetch and buffer. More...

Detailed Description

Definition at line 55 of file fetch_unit.hh.

Constructor & Destructor Documentation

◆ FetchUnit()

gem5::FetchUnit::FetchUnit ( const ComputeUnitParams &  p,
ComputeUnit cu 

Definition at line 52 of file

◆ ~FetchUnit()

gem5::FetchUnit::~FetchUnit ( )

Definition at line 58 of file

References fetchQueue, and fetchStatusQueue.

Member Function Documentation

◆ bindWaveList()

void gem5::FetchUnit::bindWaveList ( std::vector< Wavefront * > *  list)

Definition at line 339 of file

References waveList.

◆ exec()

void gem5::FetchUnit::exec ( )

now we check if any of the fetch buffers have buffered instruction data that can be decoded and sent to its wavefront's instruction buffer. then we check if any of the fetch buffer entries can be released. we only check if we can release a buffer

Definition at line 84 of file

References gem5::Scheduler::chooseWave(), computeUnit, fetchBuf, fetchQueue, fetchScheduler, fetchStatusQueue, gem5::Wavefront::getStatus(), initiateFetch(), gem5::ArmISA::j, gem5::Shader::n_wf, gem5::Wavefront::pendingFetch, gem5::Wavefront::S_RUNNING, gem5::Wavefront::S_WAITCNT, gem5::ComputeUnit::shader, gem5::Wavefront::stopFetch(), and gem5::Wavefront::wfSlotId.

◆ fetch()

void gem5::FetchUnit::fetch ( PacketPtr  pkt,
Wavefront wavefront 

this is necessary because the GPU TLB receives packets instead of requests. when the translation is complete, all relevent fields in the request will be populated, but not in the packet. here we create the new packet so we can set the size, addr, and proper flags.

if we have not reserved an entry in the fetch buffer, stop fetching. this can happen due to a branch instruction flushing the fetch buffer while an ITLB or I-cache request is still pending, in the same cycle another instruction is trying to fetch.

For full system, if this is a device request we need to set the requestor ID of the packet to the GPU memory manager so it is routed through Ruby as a memory request and not a PIO request.

we should have reserved an entry in the fetch buffer for this cache line. here we get the pointer to the entry used to buffer this request's line data.

Definition at line 230 of file

References gem5::Packet::cmd, computeUnit, gem5::ComputeUnit::cu_id, gem5::Packet::dataStatic(), DPRINTF, gem5::Wavefront::dropFetch, fetchBuf, gem5::Wavefront::pendingFetch, processFetchReturn(), gem5::Packet::req, gem5::ComputeUnit::SQCPort::retries, gem5::Packet::senderState, gem5::RequestPort::sendFunctional(), gem5::AMDGPUSystemHub::sendRequest(), gem5::RequestPort::sendTimingReq(), gem5::ComputeUnit::shader, gem5::Wavefront::simdId, gem5::ComputeUnit::sqcPort, gem5::Shader::systemHub, timingSim, gem5::ComputeUnit::vramRequestorId(), and gem5::Wavefront::wfSlotId.

Referenced by initiateFetch().

◆ flushBuf()

void gem5::FetchUnit::flushBuf ( int  wfSlotId)

◆ init()

void gem5::FetchUnit::init ( )

◆ initiateFetch()

void gem5::FetchUnit::initiateFetch ( Wavefront wavefront)

calculate the virtual address to fetch from the SQC. the fetch buffer holds a configurable number of cache lines. we start fetching at the address of the cache line immediately following the buffered line(s).

For full system, if this is a device request we need to set the requestor ID of the packet to the GPU memory manager so it is routed through Ruby as a memory request and not a PIO request.

Definition at line 136 of file

References gem5::ComputeUnit::cacheLineSize(), computeUnit, gem5::ComputeUnit::cu_id, DPRINTF, gem5::BaseMMU::Execute, fetch(), fetchBuf, gem5::ComputeUnit::getCacheLineBits(), gem5::Shader::gpuTc, gem5::Request::INST_FETCH, gem5::ComputeUnit::ITLBPort::isStalled(), gem5::ruby::makeLineAddress(), gem5::Wavefront::pc(), gem5::MemCmd::ReadReq, gem5::Packet::req, gem5::ComputeUnit::requestorId(), gem5::ComputeUnit::ITLBPort::retries, gem5::Packet::senderState, gem5::RequestPort::sendFunctional(), gem5::RequestPort::sendTimingReq(), gem5::ComputeUnit::shader, gem5::Wavefront::simdId, gem5::ComputeUnit::sqcTLBPort, gem5::ComputeUnit::ITLBPort::stallPort(), timingSim, gem5::GpuTranslationState::tlbEntry, gem5::MipsISA::vaddr, gem5::ComputeUnit::vramRequestorId(), gem5::Wavefront::wfDynId, and gem5::Wavefront::wfSlotId.

Referenced by exec().

◆ processFetchReturn()

void gem5::FetchUnit::processFetchReturn ( PacketPtr  pkt)

Member Data Documentation

◆ computeUnit

ComputeUnit& gem5::FetchUnit::computeUnit

Definition at line 258 of file fetch_unit.hh.

Referenced by exec(), fetch(), init(), initiateFetch(), and processFetchReturn().

◆ decoder

TheGpuISA::Decoder gem5::FetchUnit::decoder

Definition at line 259 of file fetch_unit.hh.

Referenced by init().

◆ fetchBuf

std::vector<FetchBufDesc> gem5::FetchUnit::fetchBuf

Definition at line 279 of file fetch_unit.hh.

Referenced by exec(), fetch(), flushBuf(), init(), initiateFetch(), and processFetchReturn().

◆ fetchDepth

int gem5::FetchUnit::fetchDepth

number of cache lines we can fetch and buffer.

this includes the currently fetched line (i.e., the line that corresponds to the WF's current PC), as well as any lines that may be prefetched.

Definition at line 286 of file fetch_unit.hh.

Referenced by gem5::FetchUnit::FetchBufDesc::flushBuf(), init(), and gem5::FetchUnit::FetchBufDesc::reserveBuf().

◆ fetchQueue

std::vector<Wavefront*> gem5::FetchUnit::fetchQueue

Definition at line 269 of file fetch_unit.hh.

Referenced by exec(), init(), and ~FetchUnit().

◆ fetchScheduler

Scheduler gem5::FetchUnit::fetchScheduler

Definition at line 265 of file fetch_unit.hh.

Referenced by exec(), and init().

◆ fetchStatusQueue

std::vector<std::pair<Wavefront*, bool> > gem5::FetchUnit::fetchStatusQueue

Definition at line 274 of file fetch_unit.hh.

Referenced by exec(), init(), and ~FetchUnit().

◆ globalFetchUnitID

uint32_t gem5::FetchUnit::globalFetchUnitID

Definition at line 67 of file fetch_unit.hh.

◆ timingSim

bool gem5::FetchUnit::timingSim

Definition at line 257 of file fetch_unit.hh.

Referenced by fetch(), init(), and initiateFetch().

◆ waveList

std::vector<Wavefront*>* gem5::FetchUnit::waveList

Definition at line 277 of file fetch_unit.hh.

Referenced by bindWaveList(), and init().

The documentation for this class was generated from the following files:

Generated on Wed Dec 21 2022 10:23:23 for gem5 by doxygen 1.9.1