gem5  v21.1.0.2
free_list.hh
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41 
42 #ifndef __CPU_O3_FREE_LIST_HH__
43 #define __CPU_O3_FREE_LIST_HH__
44 
45 #include <iostream>
46 #include <queue>
47 
48 #include "base/logging.hh"
49 #include "base/trace.hh"
50 #include "cpu/o3/comm.hh"
51 #include "cpu/o3/regfile.hh"
52 #include "debug/FreeList.hh"
53 
54 namespace gem5
55 {
56 
57 namespace o3
58 {
59 
60 class UnifiedRenameMap;
61 
70 {
71  private:
72 
74  std::queue<PhysRegIdPtr> freeRegs;
75 
76  public:
77 
79 
81  void addReg(PhysRegIdPtr reg) { freeRegs.push(reg); }
82 
84  template<class InputIt>
85  void
86  addRegs(InputIt first, InputIt last) {
87  std::for_each(first, last, [this](typename InputIt::value_type& reg) {
88  this->freeRegs.push(&reg);
89  });
90  }
91 
94  {
95  assert(!freeRegs.empty());
96  PhysRegIdPtr free_reg = freeRegs.front();
97  freeRegs.pop();
98  return free_reg;
99  }
100 
102  unsigned numFreeRegs() const { return freeRegs.size(); }
103 
105  bool hasFreeRegs() const { return !freeRegs.empty(); }
106 };
107 
108 
123 {
124  private:
125 
128  const std::string _name;
129 
132 
135 
140 
147 
150 
156 
157  /*
158  * We give UnifiedRenameMap internal access so it can get at the
159  * internal per-class free lists and associate those with its
160  * per-class rename maps. See UnifiedRenameMap::init().
161  */
162  friend class UnifiedRenameMap;
163 
164  public:
173  UnifiedFreeList(const std::string &_my_name, PhysRegFile *_regFile);
174 
176  std::string name() const { return _name; };
177 
180 
183 
186 
189 
192 
195 
198 
200  void addReg(PhysRegIdPtr freed_reg);
201 
203  template<class InputIt>
204  void addRegs(InputIt first, InputIt last);
205 
207  void addIntReg(PhysRegIdPtr freed_reg) { intList.addReg(freed_reg); }
208 
210  void addFloatReg(PhysRegIdPtr freed_reg) { floatList.addReg(freed_reg); }
211 
213  void addVecReg(PhysRegIdPtr freed_reg) { vecList.addReg(freed_reg); }
214 
216  void addVecElem(PhysRegIdPtr freed_reg) {
217  vecElemList.addReg(freed_reg);
218  }
219 
221  void addVecPredReg(PhysRegIdPtr freed_reg) { predList.addReg(freed_reg); }
222 
224  void addCCReg(PhysRegIdPtr freed_reg) { ccList.addReg(freed_reg); }
225 
227  bool hasFreeIntRegs() const { return intList.hasFreeRegs(); }
228 
230  bool hasFreeFloatRegs() const { return floatList.hasFreeRegs(); }
231 
233  bool hasFreeVecRegs() const { return vecList.hasFreeRegs(); }
234 
236  bool hasFreeVecElems() const { return vecElemList.hasFreeRegs(); }
237 
239  bool hasFreeVecPredRegs() const { return predList.hasFreeRegs(); }
240 
242  bool hasFreeCCRegs() const { return ccList.hasFreeRegs(); }
243 
245  unsigned numFreeIntRegs() const { return intList.numFreeRegs(); }
246 
248  unsigned numFreeFloatRegs() const { return floatList.numFreeRegs(); }
249 
251  unsigned numFreeVecRegs() const { return vecList.numFreeRegs(); }
252 
254  unsigned numFreeVecElems() const { return vecElemList.numFreeRegs(); }
255 
257  unsigned numFreeVecPredRegs() const { return predList.numFreeRegs(); }
258 
260  unsigned numFreeCCRegs() const { return ccList.numFreeRegs(); }
261 };
262 
263 template<class InputIt>
264 inline void
265 UnifiedFreeList::addRegs(InputIt first, InputIt last)
266 {
267  // Are there any registers to add?
268  if (first == last)
269  return;
270 
271  panic_if((first != last) &&
272  first->classValue() != (last-1)->classValue(),
273  "Attempt to add mixed type regs: %s and %s",
274  first->className(),
275  (last-1)->className());
276  switch (first->classValue()) {
277  case IntRegClass:
278  intList.addRegs(first, last);
279  break;
280  case FloatRegClass:
281  floatList.addRegs(first, last);
282  break;
283  case VecRegClass:
284  vecList.addRegs(first, last);
285  break;
286  case VecElemClass:
287  vecElemList.addRegs(first, last);
288  break;
289  case VecPredRegClass:
290  predList.addRegs(first, last);
291  break;
292  case CCRegClass:
293  ccList.addRegs(first, last);
294  break;
295  default:
296  panic("Unexpected RegClass (%s)",
297  first->className());
298  }
299 
300 }
301 
302 inline void
304 {
305  DPRINTF(FreeList,"Freeing register %i (%s).\n", freed_reg->index(),
306  freed_reg->className());
307  //Might want to add in a check for whether or not this register is
308  //already in there. A bit vector or something similar would be useful.
309  switch (freed_reg->classValue()) {
310  case IntRegClass:
311  intList.addReg(freed_reg);
312  break;
313  case FloatRegClass:
314  floatList.addReg(freed_reg);
315  break;
316  case VecRegClass:
317  vecList.addReg(freed_reg);
318  break;
319  case VecElemClass:
320  vecElemList.addReg(freed_reg);
321  break;
322  case VecPredRegClass:
323  predList.addReg(freed_reg);
324  break;
325  case CCRegClass:
326  ccList.addReg(freed_reg);
327  break;
328  default:
329  panic("Unexpected RegClass (%s)",
330  freed_reg->className());
331  }
332 
333  // These assert conditions ensure that the number of free
334  // registers are not more than the # of total Physical Registers.
335  // If this were false, it would mean that registers
336  // have been freed twice, overflowing the free register
337  // pool and potentially crashing SMT workloads.
338  // ----
339  // Comment out for now so as to not potentially break
340  // CMP and single-threaded workloads
341  // ----
342  // assert(freeIntRegs.size() <= numPhysicalIntRegs);
343  // assert(freeFloatRegs.size() <= numPhysicalFloatRegs);
344 }
345 
346 } // namespace o3
347 } // namespace gem5
348 
349 #endif // __CPU_O3_FREE_LIST_HH__
gem5::VecElemClass
@ VecElemClass
Vector Register Native Elem lane.
Definition: reg_class.hh:62
gem5::CCRegClass
@ CCRegClass
Condition-code register.
Definition: reg_class.hh:64
gem5::o3::UnifiedFreeList::numFreeIntRegs
unsigned numFreeIntRegs() const
Returns the number of free integer registers.
Definition: free_list.hh:245
gem5::o3::SimpleFreeList::freeRegs
std::queue< PhysRegIdPtr > freeRegs
The actual free list.
Definition: free_list.hh:74
gem5::o3::UnifiedFreeList::addFloatReg
void addFloatReg(PhysRegIdPtr freed_reg)
Adds a fp register back to the free list.
Definition: free_list.hh:210
gem5::o3::UnifiedFreeList::name
std::string name() const
Gives the name of the freelist.
Definition: free_list.hh:176
gem5::o3::UnifiedFreeList::hasFreeVecRegs
bool hasFreeVecRegs() const
Checks if there are any free vector registers.
Definition: free_list.hh:233
gem5::o3::UnifiedFreeList::getCCList
SimpleFreeList * getCCList()
Returns a pointer to the condition-code free list.
Definition: free_list.hh:179
gem5::o3::UnifiedFreeList::numFreeCCRegs
unsigned numFreeCCRegs() const
Returns the number of free cc registers.
Definition: free_list.hh:260
gem5::o3::SimpleFreeList
Free list for a single class of registers (e.g., integer or floating point).
Definition: free_list.hh:69
gem5::FloatRegClass
@ FloatRegClass
Floating-point register.
Definition: reg_class.hh:58
gem5::o3::UnifiedFreeList::UnifiedFreeList
UnifiedFreeList(const std::string &_my_name, PhysRegFile *_regFile)
Constructs a free list.
Definition: free_list.cc:41
gem5::o3::UnifiedFreeList
FreeList class that simply holds the list of free integer and floating point registers.
Definition: free_list.hh:122
gem5::VecPredRegClass
@ VecPredRegClass
Definition: reg_class.hh:63
gem5::o3::UnifiedFreeList::vecElemList
SimpleFreeList vecElemList
The list of free vector element registers.
Definition: free_list.hh:142
gem5::o3::UnifiedFreeList::addIntReg
void addIntReg(PhysRegIdPtr freed_reg)
Adds an integer register back to the free list.
Definition: free_list.hh:207
gem5::o3::UnifiedFreeList::addCCReg
void addCCReg(PhysRegIdPtr freed_reg)
Adds a cc register back to the free list.
Definition: free_list.hh:224
gem5::o3::UnifiedFreeList::hasFreeVecElems
bool hasFreeVecElems() const
Checks if there are any free vector registers.
Definition: free_list.hh:236
gem5::o3::UnifiedFreeList::numFreeVecElems
unsigned numFreeVecElems() const
Returns the number of free vector registers.
Definition: free_list.hh:254
gem5::o3::SimpleFreeList::numFreeRegs
unsigned numFreeRegs() const
Return the number of free registers on the list.
Definition: free_list.hh:102
gem5::o3::SimpleFreeList::SimpleFreeList
SimpleFreeList()
Definition: free_list.hh:78
gem5::o3::UnifiedFreeList::addVecReg
void addVecReg(PhysRegIdPtr freed_reg)
Adds a vector register back to the free list.
Definition: free_list.hh:213
gem5::o3::UnifiedFreeList::floatList
SimpleFreeList floatList
The list of free floating point registers.
Definition: free_list.hh:134
comm.hh
gem5::o3::SimpleFreeList::addRegs
void addRegs(InputIt first, InputIt last)
Add physical registers to the free list.
Definition: free_list.hh:86
gem5::o3::UnifiedFreeList::numFreeVecPredRegs
unsigned numFreeVecPredRegs() const
Returns the number of free predicate registers.
Definition: free_list.hh:257
gem5::o3::UnifiedFreeList::regFile
PhysRegFile * regFile
The register file object is used only to distinguish integer from floating-point physical register in...
Definition: free_list.hh:155
gem5::o3::UnifiedFreeList::predList
SimpleFreeList predList
The list of free predicate registers.
Definition: free_list.hh:146
DPRINTF
#define DPRINTF(x,...)
Definition: trace.hh:186
gem5::o3::PhysRegFile
Simple physical register file class.
Definition: regfile.hh:66
gem5::o3::UnifiedFreeList::addRegs
void addRegs(InputIt first, InputIt last)
Adds a register back to the free list.
Definition: free_list.hh:265
gem5::o3::UnifiedFreeList::numFreeVecRegs
unsigned numFreeVecRegs() const
Returns the number of free vector registers.
Definition: free_list.hh:251
gem5::PhysRegId::classValue
RegClass classValue() const
Class accessor.
Definition: reg_class.hh:180
gem5::o3::SimpleFreeList::addReg
void addReg(PhysRegIdPtr reg)
Add a physical register to the free list.
Definition: free_list.hh:81
regfile.hh
gem5::o3::UnifiedFreeList::getVecElem
PhysRegIdPtr getVecElem()
Gets a free vector elemenet register.
Definition: free_list.hh:191
gem5::o3::UnifiedFreeList::getCCReg
PhysRegIdPtr getCCReg()
Gets a free cc register.
Definition: free_list.hh:197
gem5::X86ISA::reg
Bitfield< 5, 3 > reg
Definition: types.hh:92
gem5::o3::SimpleFreeList::getReg
PhysRegIdPtr getReg()
Get the next available register from the free list.
Definition: free_list.hh:93
gem5::o3::UnifiedFreeList::getVecReg
PhysRegIdPtr getVecReg()
Gets a free vector register.
Definition: free_list.hh:188
gem5::VecRegClass
@ VecRegClass
Vector Register.
Definition: reg_class.hh:60
panic_if
#define panic_if(cond,...)
Conditional panic macro that checks the supplied condition and only panics if the condition is true a...
Definition: logging.hh:203
gem5::o3::UnifiedFreeList::getFloatReg
PhysRegIdPtr getFloatReg()
Gets a free fp register.
Definition: free_list.hh:185
gem5::o3::UnifiedFreeList::ccList
SimpleFreeList ccList
The list of free condition-code registers.
Definition: free_list.hh:149
gem5::o3::SimpleFreeList::hasFreeRegs
bool hasFreeRegs() const
True iff there are free registers on the list.
Definition: free_list.hh:105
gem5::PhysRegId::className
const char * className() const
Return a const char* with the register class name.
Definition: reg_class.hh:182
gem5::o3::UnifiedFreeList::_name
const std::string _name
The object name, for DPRINTF.
Definition: free_list.hh:128
gem5::o3::UnifiedFreeList::hasFreeFloatRegs
bool hasFreeFloatRegs() const
Checks if there are any free fp registers.
Definition: free_list.hh:230
logging.hh
gem5::o3::UnifiedFreeList::getVecPredReg
PhysRegIdPtr getVecPredReg()
Gets a free predicate register.
Definition: free_list.hh:194
gem5::o3::UnifiedFreeList::hasFreeIntRegs
bool hasFreeIntRegs() const
Checks if there are any free integer registers.
Definition: free_list.hh:227
gem5::PhysRegId
Physical register ID.
Definition: reg_class.hh:198
gem5::o3::UnifiedFreeList::addVecPredReg
void addVecPredReg(PhysRegIdPtr freed_reg)
Adds a predicate register back to the free list.
Definition: free_list.hh:221
gem5::o3::UnifiedFreeList::hasFreeCCRegs
bool hasFreeCCRegs() const
Checks if there are any free cc registers.
Definition: free_list.hh:242
trace.hh
gem5::o3::UnifiedFreeList::hasFreeVecPredRegs
bool hasFreeVecPredRegs() const
Checks if there are any free predicate registers.
Definition: free_list.hh:239
gem5::IntRegClass
@ IntRegClass
Integer register.
Definition: reg_class.hh:57
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40
gem5::o3::UnifiedFreeList::numFreeFloatRegs
unsigned numFreeFloatRegs() const
Returns the number of free fp registers.
Definition: free_list.hh:248
gem5::o3::UnifiedFreeList::getIntReg
PhysRegIdPtr getIntReg()
Gets a free integer register.
Definition: free_list.hh:182
gem5::o3::UnifiedFreeList::intList
SimpleFreeList intList
The list of free integer registers.
Definition: free_list.hh:131
gem5::PhysRegId::index
RegIndex index() const
Visible RegId methods.
Definition: reg_class.hh:154
gem5::o3::UnifiedFreeList::addReg
void addReg(PhysRegIdPtr freed_reg)
Adds a register back to the free list.
Definition: free_list.hh:303
panic
#define panic(...)
This implements a cprintf based panic() function.
Definition: logging.hh:177
gem5::o3::UnifiedRenameMap
Unified register rename map for all classes of registers.
Definition: rename_map.hh:174
gem5::o3::UnifiedFreeList::vecList
SimpleFreeList vecList
The following two are exclusive interfaces.
Definition: free_list.hh:139
gem5::o3::UnifiedFreeList::addVecElem
void addVecElem(PhysRegIdPtr freed_reg)
Adds a vector element register back to the free list.
Definition: free_list.hh:216

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