gem5  v22.0.0.1
rename_map.hh
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41 
42 #ifndef __CPU_O3_RENAME_MAP_HH__
43 #define __CPU_O3_RENAME_MAP_HH__
44 
45 #include <algorithm>
46 #include <array>
47 #include <iostream>
48 #include <limits>
49 #include <utility>
50 #include <vector>
51 
52 #include "arch/generic/isa.hh"
53 #include "cpu/o3/dyn_inst_ptr.hh"
54 #include "cpu/o3/free_list.hh"
55 #include "cpu/o3/regfile.hh"
56 #include "cpu/reg_class.hh"
57 
58 namespace gem5
59 {
60 
61 namespace o3
62 {
63 
72 {
73  private:
77  public:
78  using iterator = Arch2PhysMap::iterator;
79  using const_iterator = Arch2PhysMap::const_iterator;
80  private:
81 
87 
88  public:
89 
91 
97  void init(const RegClass &reg_class, SimpleFreeList *_freeList);
98 
106 
114  RenameInfo rename(const RegId& arch_reg);
115 
122  lookup(const RegId& arch_reg) const
123  {
124  assert(arch_reg.index() <= map.size());
125  return map[arch_reg.index()];
126  }
127 
134  void
135  setEntry(const RegId& arch_reg, PhysRegIdPtr phys_reg)
136  {
137  assert(arch_reg.index() <= map.size());
138  map[arch_reg.index()] = phys_reg;
139  }
140 
142  unsigned numFreeEntries() const { return freeList->numFreeRegs(); }
143 
144  size_t numArchRegs() const { return map.size(); }
145 
148  iterator begin() { return map.begin(); }
149  const_iterator begin() const { return map.begin(); }
150  const_iterator cbegin() const { return map.cbegin(); }
155  iterator end() { return map.end(); }
156  const_iterator end() const { return map.end(); }
157  const_iterator cend() const { return map.cend(); }
159 };
160 
169 {
170  private:
171  std::array<SimpleRenameMap, CCRegClass + 1> renameMaps;
172 
173  static inline PhysRegId invalidPhysRegId{};
174 
180 
181  public:
182 
184 
186  UnifiedRenameMap() : regFile(nullptr) {};
187 
190 
192  void init(const BaseISA::RegClasses &regClasses,
193  PhysRegFile *_regFile, UnifiedFreeList *freeList);
194 
203  RenameInfo
204  rename(const RegId& arch_reg)
205  {
206  if (!arch_reg.isRenameable()) {
207  // misc regs aren't really renamed, just remapped
208  PhysRegIdPtr phys_reg = lookup(arch_reg);
209  // Set the new register to the previous one to keep the same
210  // mapping throughout the execution.
211  return RenameInfo(phys_reg, phys_reg);
212  }
213 
214  return renameMaps[arch_reg.classValue()].rename(arch_reg);
215  }
216 
225  lookup(const RegId& arch_reg) const
226  {
227  auto reg_class = arch_reg.classValue();
228  if (reg_class == InvalidRegClass) {
229  return &invalidPhysRegId;
230  } else if (reg_class == MiscRegClass) {
231  // misc regs aren't really renamed, they keep the same
232  // mapping throughout the execution.
233  return regFile->getMiscRegId(arch_reg.index());
234  }
235  return renameMaps[reg_class].lookup(arch_reg);
236  }
237 
246  void
247  setEntry(const RegId& arch_reg, PhysRegIdPtr phys_reg)
248  {
249  assert(phys_reg->is(arch_reg.classValue()));
250  if (!arch_reg.isRenameable()) {
251  // Misc registers do not actually rename, so don't change
252  // their mappings. We end up here when a commit or squash
253  // tries to update or undo a hardwired misc reg nmapping,
254  // which should always be setting it to what it already is.
255  assert(phys_reg == lookup(arch_reg));
256  return;
257  }
258 
259  return renameMaps[arch_reg.classValue()].setEntry(arch_reg, phys_reg);
260  }
261 
268  unsigned
270  {
271  auto min_free = std::numeric_limits<unsigned>::max();
272  for (auto &map: renameMaps) {
273  // If this map isn't empty (not used)...
274  if (map.numArchRegs())
275  min_free = std::min(min_free, map.numFreeEntries());
276  }
277  return min_free;
278  }
279 
280  unsigned
282  {
283  return renameMaps[type].numFreeEntries();
284  }
285 
289  bool canRename(DynInstPtr inst) const;
290 };
291 
292 } // namespace o3
293 } // namespace gem5
294 
295 #endif //__CPU_O3_RENAME_MAP_HH__
gem5::RegId::isRenameable
constexpr bool isRenameable() const
Return true if this register can be renamed.
Definition: reg_class.hh:174
gem5::o3::UnifiedRenameMap::RenameInfo
SimpleRenameMap::RenameInfo RenameInfo
Definition: rename_map.hh:183
gem5::InvalidRegClass
@ InvalidRegClass
Definition: reg_class.hh:67
gem5::o3::SimpleFreeList
Free list for a single class of registers (e.g., integer or floating point).
Definition: free_list.hh:71
gem5::o3::SimpleRenameMap::begin
const_iterator begin() const
Definition: rename_map.hh:149
gem5::o3::SimpleRenameMap::end
const_iterator end() const
Definition: rename_map.hh:156
gem5::o3::SimpleRenameMap::numFreeEntries
unsigned numFreeEntries() const
Return the number of free entries on the associated free list.
Definition: rename_map.hh:142
gem5::o3::SimpleRenameMap::freeList
SimpleFreeList * freeList
Pointer to the free list from which new physical registers should be allocated in rename()
Definition: rename_map.hh:86
gem5::o3::SimpleRenameMap::end
iterator end()
Forward end/cend to the map.
Definition: rename_map.hh:155
gem5::o3::SimpleRenameMap::iterator
Arch2PhysMap::iterator iterator
Definition: rename_map.hh:78
gem5::o3::UnifiedFreeList
FreeList class that simply holds the list of free integer and floating point registers.
Definition: free_list.hh:124
std::vector< PhysRegIdPtr >
regfile.hh
gem5::o3::SimpleFreeList::numFreeRegs
unsigned numFreeRegs() const
Return the number of free registers on the list.
Definition: free_list.hh:104
gem5::RefCountingPtr< DynInst >
gem5::o3::UnifiedRenameMap::numFreeEntries
unsigned numFreeEntries(RegClassType type) const
Definition: rename_map.hh:281
gem5::o3::SimpleRenameMap::begin
iterator begin()
Forward begin/cbegin to the map.
Definition: rename_map.hh:148
gem5::o3::PhysRegFile
Simple physical register file class.
Definition: regfile.hh:67
gem5::X86ISA::type
type
Definition: misc.hh:727
gem5::o3::SimpleRenameMap::cend
const_iterator cend() const
Definition: rename_map.hh:157
gem5::o3::SimpleRenameMap::SimpleRenameMap
SimpleRenameMap()
Definition: rename_map.cc:57
gem5::o3::SimpleRenameMap::lookup
PhysRegIdPtr lookup(const RegId &arch_reg) const
Look up the physical register mapped to an architectural register.
Definition: rename_map.hh:122
gem5::o3::SimpleRenameMap::numArchRegs
size_t numArchRegs() const
Definition: rename_map.hh:144
gem5::o3::UnifiedRenameMap::UnifiedRenameMap
UnifiedRenameMap()
Default constructor.
Definition: rename_map.hh:186
gem5::o3::UnifiedRenameMap::~UnifiedRenameMap
~UnifiedRenameMap()
Destructor.
Definition: rename_map.hh:189
std::pair
STL pair class.
Definition: stl.hh:58
gem5::PhysRegId::is
constexpr bool is(RegClassType reg_class) const
Definition: reg_class.hh:181
gem5::o3::SimpleRenameMap::rename
RenameInfo rename(const RegId &arch_reg)
Tell rename map to get a new free physical register to remap the specified architectural register.
Definition: rename_map.cc:73
dyn_inst_ptr.hh
gem5::o3::UnifiedRenameMap::renameMaps
std::array< SimpleRenameMap, CCRegClass+1 > renameMaps
Definition: rename_map.hh:171
gem5::RegClass
Definition: reg_class.hh:81
gem5::o3::UnifiedRenameMap::invalidPhysRegId
static PhysRegId invalidPhysRegId
Definition: rename_map.hh:173
gem5::o3::SimpleRenameMap::RenameInfo
std::pair< PhysRegIdPtr, PhysRegIdPtr > RenameInfo
Pair of a physical register and a physical register.
Definition: rename_map.hh:105
isa.hh
gem5::o3::SimpleRenameMap::init
void init(const RegClass &reg_class, SimpleFreeList *_freeList)
Because we have an array of rename maps (one per thread) in the CPU, it's awkward to initialize this ...
Definition: rename_map.cc:63
gem5::o3::UnifiedRenameMap::numFreeEntries
unsigned numFreeEntries() const
Return the minimum number of free entries across all of the register classes.
Definition: rename_map.hh:269
gem5::RegClassType
RegClassType
Enumerate the classes of registers.
Definition: reg_class.hh:56
gem5::MiscRegClass
@ MiscRegClass
Control (misc) register.
Definition: reg_class.hh:66
gem5::o3::PhysRegFile::getMiscRegId
PhysRegIdPtr getMiscRegId(RegIndex reg_idx)
Gets a misc register PhysRegIdPtr.
Definition: regfile.hh:160
gem5::o3::UnifiedRenameMap::canRename
bool canRename(DynInstPtr inst) const
Return whether there are enough registers to serve the request.
Definition: rename_map.cc:121
reg_class.hh
gem5::o3::UnifiedRenameMap::lookup
PhysRegIdPtr lookup(const RegId &arch_reg) const
Look up the physical register mapped to an architectural register.
Definition: rename_map.hh:225
free_list.hh
gem5::o3::SimpleRenameMap::cbegin
const_iterator cbegin() const
Definition: rename_map.hh:150
gem5::PhysRegId
Physical register ID.
Definition: reg_class.hh:245
gem5::o3::SimpleRenameMap::setEntry
void setEntry(const RegId &arch_reg, PhysRegIdPtr phys_reg)
Update rename map with a specific mapping.
Definition: rename_map.hh:135
gem5::RegId::index
constexpr RegIndex index() const
Index accessors.
Definition: reg_class.hh:188
gem5::o3::SimpleRenameMap::const_iterator
Arch2PhysMap::const_iterator const_iterator
Definition: rename_map.hh:79
gem5::o3::SimpleRenameMap
Register rename map for a single class of registers (e.g., integer or floating point).
Definition: rename_map.hh:71
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: gpu_translation_state.hh:37
gem5::RegId::classValue
constexpr RegClassType classValue() const
Class accessor.
Definition: reg_class.hh:191
gem5::o3::UnifiedRenameMap::init
void init(const BaseISA::RegClasses &regClasses, PhysRegFile *_regFile, UnifiedFreeList *freeList)
Initializes rename map with given parameters.
Definition: rename_map.cc:111
gem5::o3::UnifiedRenameMap::rename
RenameInfo rename(const RegId &arch_reg)
Tell rename map to get a new free physical register to remap the specified architectural register.
Definition: rename_map.hh:204
gem5::o3::SimpleRenameMap::map
Arch2PhysMap map
The acutal arch-to-phys register map.
Definition: rename_map.hh:76
gem5::o3::UnifiedRenameMap::regFile
PhysRegFile * regFile
The register file object is used only to get PhysRegIdPtr on MiscRegs, as they are stored in it.
Definition: rename_map.hh:179
gem5::RegId
Register ID: describe an architectural register with its class and index.
Definition: reg_class.hh:126
gem5::o3::UnifiedRenameMap::setEntry
void setEntry(const RegId &arch_reg, PhysRegIdPtr phys_reg)
Update rename map with a specific mapping.
Definition: rename_map.hh:247
gem5::o3::UnifiedRenameMap
Unified register rename map for all classes of registers.
Definition: rename_map.hh:168

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