gem5  v21.1.0.2
rename_map.hh
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41 
42 #ifndef __CPU_O3_RENAME_MAP_HH__
43 #define __CPU_O3_RENAME_MAP_HH__
44 
45 #include <iostream>
46 #include <utility>
47 #include <vector>
48 
49 #include "arch/generic/isa.hh"
50 #include "cpu/o3/free_list.hh"
51 #include "cpu/o3/regfile.hh"
52 #include "cpu/reg_class.hh"
53 #include "enums/VecRegRenameMode.hh"
54 
55 namespace gem5
56 {
57 
58 namespace o3
59 {
60 
69 {
70  private:
74  public:
75  using iterator = Arch2PhysMap::iterator;
76  using const_iterator = Arch2PhysMap::const_iterator;
77  private:
78 
84 
93 
94  public:
95 
97 
103  void init(const RegClassInfo &reg_class_info, SimpleFreeList *_freeList);
104 
112 
120  RenameInfo rename(const RegId& arch_reg);
121 
128  lookup(const RegId& arch_reg) const
129  {
130  assert(arch_reg.flatIndex() <= map.size());
131  return map[arch_reg.flatIndex()];
132  }
133 
140  void
141  setEntry(const RegId& arch_reg, PhysRegIdPtr phys_reg)
142  {
143  assert(arch_reg.flatIndex() <= map.size());
144  map[arch_reg.flatIndex()] = phys_reg;
145  }
146 
148  unsigned numFreeEntries() const { return freeList->numFreeRegs(); }
149 
150  size_t numArchRegs() const { return map.size(); }
151 
154  iterator begin() { return map.begin(); }
155  const_iterator begin() const { return map.begin(); }
156  const_iterator cbegin() const { return map.cbegin(); }
161  iterator end() { return map.end(); }
162  const_iterator end() const { return map.end(); }
163  const_iterator cend() const { return map.cend(); }
165 };
166 
175 {
176  private:
179 
182 
185 
188 
191 
194 
195  using VecMode = enums::VecRegRenameMode;
197 
203 
204  public:
205 
207 
209  UnifiedRenameMap() : regFile(nullptr) {};
210 
213 
215  void init(const BaseISA::RegClasses &regClasses,
216  PhysRegFile *_regFile, UnifiedFreeList *freeList, VecMode _mode);
217 
226  RenameInfo rename(const RegId& arch_reg)
227  {
228  switch (arch_reg.classValue()) {
229  case IntRegClass:
230  return intMap.rename(arch_reg);
231  case FloatRegClass:
232  return floatMap.rename(arch_reg);
233  case VecRegClass:
234  assert(vecMode == enums::Full);
235  return vecMap.rename(arch_reg);
236  case VecElemClass:
237  assert(vecMode == enums::Elem);
238  return vecElemMap.rename(arch_reg);
239  case VecPredRegClass:
240  return predMap.rename(arch_reg);
241  case CCRegClass:
242  return ccMap.rename(arch_reg);
243  case MiscRegClass:
244  {
245  // misc regs aren't really renamed, just remapped
246  PhysRegIdPtr phys_reg = lookup(arch_reg);
247  // Set the new register to the previous one to keep the same
248  // mapping throughout the execution.
249  return RenameInfo(phys_reg, phys_reg);
250  }
251 
252  default:
253  panic("rename rename(): unknown reg class %s\n",
254  arch_reg.className());
255  }
256  }
257 
266  lookup(const RegId& arch_reg) const
267  {
268  switch (arch_reg.classValue()) {
269  case IntRegClass:
270  return intMap.lookup(arch_reg);
271 
272  case FloatRegClass:
273  return floatMap.lookup(arch_reg);
274 
275  case VecRegClass:
276  assert(vecMode == enums::Full);
277  return vecMap.lookup(arch_reg);
278 
279  case VecElemClass:
280  assert(vecMode == enums::Elem);
281  return vecElemMap.lookup(arch_reg);
282 
283  case VecPredRegClass:
284  return predMap.lookup(arch_reg);
285 
286  case CCRegClass:
287  return ccMap.lookup(arch_reg);
288 
289  case MiscRegClass:
290  // misc regs aren't really renamed, they keep the same
291  // mapping throughout the execution.
292  return regFile->getMiscRegId(arch_reg.flatIndex());
293 
294  default:
295  panic("rename lookup(): unknown reg class %s\n",
296  arch_reg.className());
297  }
298  }
299 
308  void
309  setEntry(const RegId& arch_reg, PhysRegIdPtr phys_reg)
310  {
311  assert(phys_reg->is(arch_reg.classValue()));
312  switch (arch_reg.classValue()) {
313  case IntRegClass:
314  return intMap.setEntry(arch_reg, phys_reg);
315 
316  case FloatRegClass:
317  return floatMap.setEntry(arch_reg, phys_reg);
318 
319  case VecRegClass:
320  assert(vecMode == enums::Full);
321  return vecMap.setEntry(arch_reg, phys_reg);
322 
323  case VecElemClass:
324  assert(vecMode == enums::Elem);
325  return vecElemMap.setEntry(arch_reg, phys_reg);
326 
327  case VecPredRegClass:
328  return predMap.setEntry(arch_reg, phys_reg);
329 
330  case CCRegClass:
331  return ccMap.setEntry(arch_reg, phys_reg);
332 
333  case MiscRegClass:
334  // Misc registers do not actually rename, so don't change
335  // their mappings. We end up here when a commit or squash
336  // tries to update or undo a hardwired misc reg nmapping,
337  // which should always be setting it to what it already is.
338  assert(phys_reg == lookup(arch_reg));
339  return;
340 
341  default:
342  panic("rename setEntry(): unknown reg class %s\n",
343  arch_reg.className());
344  }
345  }
346 
353  unsigned
355  {
356  return std::min({intMap.numFreeEntries(),
358  vecMode == enums::Full ? vecMap.numFreeEntries() :
361  }
362 
363  unsigned numFreeIntEntries() const { return intMap.numFreeEntries(); }
364  unsigned numFreeFloatEntries() const { return floatMap.numFreeEntries(); }
365  unsigned
367  {
368  return vecMode == enums::Full
371  }
372  unsigned numFreePredEntries() const { return predMap.numFreeEntries(); }
373  unsigned numFreeCCEntries() const { return ccMap.numFreeEntries(); }
374 
378  bool
379  canRename(uint32_t intRegs, uint32_t floatRegs, uint32_t vectorRegs,
380  uint32_t vecElemRegs, uint32_t vecPredRegs,
381  uint32_t ccRegs) const
382  {
383  return intRegs <= intMap.numFreeEntries() &&
384  floatRegs <= floatMap.numFreeEntries() &&
385  vectorRegs <= vecMap.numFreeEntries() &&
386  vecElemRegs <= vecElemMap.numFreeEntries() &&
387  vecPredRegs <= predMap.numFreeEntries() &&
388  ccRegs <= ccMap.numFreeEntries();
389  }
396  void switchMode(VecMode newVecMode);
397 
402  void switchFreeList(UnifiedFreeList* freeList);
403 
404 };
405 
406 } // namespace o3
407 } // namespace gem5
408 
409 #endif //__CPU_O3_RENAME_MAP_HH__
gem5::o3::UnifiedRenameMap::numFreePredEntries
unsigned numFreePredEntries() const
Definition: rename_map.hh:372
gem5::o3::UnifiedRenameMap::switchMode
void switchMode(VecMode newVecMode)
Set vector mode to Full or Elem.
Definition: rename_map.cc:166
gem5::VecElemClass
@ VecElemClass
Vector Register Native Elem lane.
Definition: reg_class.hh:62
gem5::o3::SimpleRenameMap::zeroReg
RegId zeroReg
The architectural index of the zero register.
Definition: rename_map.hh:92
gem5::CCRegClass
@ CCRegClass
Condition-code register.
Definition: reg_class.hh:64
gem5::o3::UnifiedRenameMap::RenameInfo
SimpleRenameMap::RenameInfo RenameInfo
Definition: rename_map.hh:206
gem5::RegId::flatIndex
RegIndex flatIndex() const
Index flattening.
Definition: reg_class.hh:160
gem5::o3::SimpleFreeList
Free list for a single class of registers (e.g., integer or floating point).
Definition: free_list.hh:69
gem5::o3::UnifiedRenameMap::canRename
bool canRename(uint32_t intRegs, uint32_t floatRegs, uint32_t vectorRegs, uint32_t vecElemRegs, uint32_t vecPredRegs, uint32_t ccRegs) const
Return whether there are enough registers to serve the request.
Definition: rename_map.hh:379
gem5::o3::SimpleRenameMap::begin
const_iterator begin() const
Definition: rename_map.hh:155
gem5::o3::SimpleRenameMap::end
const_iterator end() const
Definition: rename_map.hh:162
gem5::o3::SimpleRenameMap::numFreeEntries
unsigned numFreeEntries() const
Return the number of free entries on the associated free list.
Definition: rename_map.hh:148
gem5::o3::SimpleRenameMap::freeList
SimpleFreeList * freeList
Pointer to the free list from which new physical registers should be allocated in rename()
Definition: rename_map.hh:83
gem5::o3::SimpleRenameMap::end
iterator end()
Forward end/cend to the map.
Definition: rename_map.hh:161
gem5::FloatRegClass
@ FloatRegClass
Floating-point register.
Definition: reg_class.hh:58
gem5::o3::SimpleRenameMap::iterator
Arch2PhysMap::iterator iterator
Definition: rename_map.hh:75
gem5::MiscRegClass
@ MiscRegClass
Control (misc) register.
Definition: reg_class.hh:65
gem5::o3::UnifiedFreeList
FreeList class that simply holds the list of free integer and floating point registers.
Definition: free_list.hh:122
gem5::VecPredRegClass
@ VecPredRegClass
Definition: reg_class.hh:63
gem5::o3::UnifiedRenameMap::intMap
SimpleRenameMap intMap
The integer register rename map.
Definition: rename_map.hh:178
std::vector< PhysRegIdPtr >
gem5::o3::UnifiedRenameMap::numFreeFloatEntries
unsigned numFreeFloatEntries() const
Definition: rename_map.hh:364
gem5::o3::SimpleFreeList::numFreeRegs
unsigned numFreeRegs() const
Return the number of free registers on the list.
Definition: free_list.hh:102
gem5::RegId::classValue
RegClass classValue() const
Class accessor.
Definition: reg_class.hh:180
gem5::o3::SimpleRenameMap::init
void init(const RegClassInfo &reg_class_info, SimpleFreeList *_freeList)
Because we have an array of rename maps (one per thread) in the CPU, it's awkward to initialize this ...
Definition: rename_map.cc:63
gem5::o3::UnifiedRenameMap::vecElemMap
SimpleRenameMap vecElemMap
The vector element register rename map.
Definition: rename_map.hh:190
gem5::o3::UnifiedRenameMap::predMap
SimpleRenameMap predMap
The predicate register rename map.
Definition: rename_map.hh:193
gem5::o3::UnifiedRenameMap::ccMap
SimpleRenameMap ccMap
The condition-code register rename map.
Definition: rename_map.hh:184
gem5::o3::SimpleRenameMap::begin
iterator begin()
Forward begin/cbegin to the map.
Definition: rename_map.hh:154
gem5::o3::PhysRegFile
Simple physical register file class.
Definition: regfile.hh:66
gem5::o3::UnifiedRenameMap::switchFreeList
void switchFreeList(UnifiedFreeList *freeList)
Switch freeList of registers from Full to Elem or vicevers depending on vecMode (vector renaming mode...
Definition: rename_map.cc:129
gem5::o3::UnifiedRenameMap::numFreeIntEntries
unsigned numFreeIntEntries() const
Definition: rename_map.hh:363
gem5::o3::SimpleRenameMap::cend
const_iterator cend() const
Definition: rename_map.hh:163
gem5::o3::UnifiedRenameMap::vecMap
SimpleRenameMap vecMap
The vector register rename map.
Definition: rename_map.hh:187
gem5::o3::SimpleRenameMap::SimpleRenameMap
SimpleRenameMap()
Definition: rename_map.cc:56
gem5::o3::SimpleRenameMap::lookup
PhysRegIdPtr lookup(const RegId &arch_reg) const
Look up the physical register mapped to an architectural register.
Definition: rename_map.hh:128
gem5::o3::SimpleRenameMap::numArchRegs
size_t numArchRegs() const
Definition: rename_map.hh:150
gem5::o3::UnifiedRenameMap::UnifiedRenameMap
UnifiedRenameMap()
Default constructor.
Definition: rename_map.hh:209
gem5::o3::UnifiedRenameMap::~UnifiedRenameMap
~UnifiedRenameMap()
Destructor.
Definition: rename_map.hh:212
gem5::o3::UnifiedRenameMap::init
void init(const BaseISA::RegClasses &regClasses, PhysRegFile *_regFile, UnifiedFreeList *freeList, VecMode _mode)
Initializes rename map with given parameters.
Definition: rename_map.cc:113
gem5::RegId::className
const char * className() const
Return a const char* with the register class name.
Definition: reg_class.hh:182
std::pair
STL pair class.
Definition: stl.hh:58
gem5::o3::SimpleRenameMap::rename
RenameInfo rename(const RegId &arch_reg)
Tell rename map to get a new free physical register to remap the specified architectural register.
Definition: rename_map.cc:75
regfile.hh
gem5::o3::UnifiedRenameMap::numFreeCCEntries
unsigned numFreeCCEntries() const
Definition: rename_map.hh:373
gem5::o3::UnifiedRenameMap::floatMap
SimpleRenameMap floatMap
The floating-point register rename map.
Definition: rename_map.hh:181
gem5::o3::SimpleRenameMap::RenameInfo
std::pair< PhysRegIdPtr, PhysRegIdPtr > RenameInfo
Pair of a physical register and a physical register.
Definition: rename_map.hh:111
isa.hh
gem5::VecRegClass
@ VecRegClass
Vector Register.
Definition: reg_class.hh:60
gem5::o3::UnifiedRenameMap::numFreeEntries
unsigned numFreeEntries() const
Return the minimum number of free entries across all of the register classes.
Definition: rename_map.hh:354
gem5::o3::PhysRegFile::getMiscRegId
PhysRegIdPtr getMiscRegId(RegIndex reg_idx)
Gets a misc register PhysRegIdPtr.
Definition: regfile.hh:179
reg_class.hh
gem5::o3::UnifiedRenameMap::lookup
PhysRegIdPtr lookup(const RegId &arch_reg) const
Look up the physical register mapped to an architectural register.
Definition: rename_map.hh:266
free_list.hh
gem5::o3::UnifiedRenameMap::numFreeVecEntries
unsigned numFreeVecEntries() const
Definition: rename_map.hh:366
gem5::o3::SimpleRenameMap::cbegin
const_iterator cbegin() const
Definition: rename_map.hh:156
gem5::PhysRegId
Physical register ID.
Definition: reg_class.hh:198
gem5::RegClassInfo
Definition: reg_class.hh:68
gem5::o3::SimpleRenameMap::setEntry
void setEntry(const RegId &arch_reg, PhysRegIdPtr phys_reg)
Update rename map with a specific mapping.
Definition: rename_map.hh:141
gem5::PhysRegId::is
bool is(RegClass reg_class) const
Definition: reg_class.hh:150
gem5::o3::SimpleRenameMap::const_iterator
Arch2PhysMap::const_iterator const_iterator
Definition: rename_map.hh:76
gem5::o3::SimpleRenameMap
Register rename map for a single class of registers (e.g., integer or floating point).
Definition: rename_map.hh:68
gem5::IntRegClass
@ IntRegClass
Integer register.
Definition: reg_class.hh:57
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40
gem5::o3::UnifiedRenameMap::vecMode
VecMode vecMode
Definition: rename_map.hh:196
gem5::o3::UnifiedRenameMap::rename
RenameInfo rename(const RegId &arch_reg)
Tell rename map to get a new free physical register to remap the specified architectural register.
Definition: rename_map.hh:226
gem5::o3::SimpleRenameMap::map
Arch2PhysMap map
The acutal arch-to-phys register map.
Definition: rename_map.hh:73
gem5::o3::UnifiedRenameMap::regFile
PhysRegFile * regFile
The register file object is used only to get PhysRegIdPtr on MiscRegs, as they are stored in it.
Definition: rename_map.hh:202
gem5::RegId
Register ID: describe an architectural register with its class and index.
Definition: reg_class.hh:88
panic
#define panic(...)
This implements a cprintf based panic() function.
Definition: logging.hh:177
gem5::o3::UnifiedRenameMap::VecMode
enums::VecRegRenameMode VecMode
Definition: rename_map.hh:195
gem5::o3::UnifiedRenameMap::setEntry
void setEntry(const RegId &arch_reg, PhysRegIdPtr phys_reg)
Update rename map with a specific mapping.
Definition: rename_map.hh:309
gem5::o3::UnifiedRenameMap
Unified register rename map for all classes of registers.
Definition: rename_map.hh:174

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