rename_map.hh

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#ifndef __CPU_O3_RENAME_MAP_HH__
#define __CPU_O3_RENAME_MAP_HH__
 
#include <algorithm>
#include <array>
#include <iostream>
#include <limits>
#include <utility>
#include <vector>
 
#include "arch/generic/isa.hh"
#include "cpu/o3/dyn_inst_ptr.hh"
#include "cpu/o3/free_list.hh"
#include "cpu/o3/regfile.hh"
#include "cpu/reg_class.hh"
 
namespace gem5
{
 
namespace o3
{
 
class SimpleRenameMap
{
  private:
    using Arch2PhysMap = std::vector<PhysRegIdPtr>;
    Arch2PhysMap map;
  public:
    using iterator = Arch2PhysMap::iterator;
    using const_iterator = Arch2PhysMap::const_iterator;
  private:
 
    SimpleFreeList *freeList;
 
  public:
 
    SimpleRenameMap();
 
    void init(const RegClass &reg_class, SimpleFreeList *_freeList);
 
    typedef std::pair<PhysRegIdPtr, PhysRegIdPtr> RenameInfo;
 
    RenameInfo rename(const RegId& arch_reg);
 
    PhysRegIdPtr
    lookup(const RegId& arch_reg) const
    {
        assert(arch_reg.index() <= map.size());
        return map[arch_reg.index()];
    }
 
    void
    setEntry(const RegId& arch_reg, PhysRegIdPtr phys_reg)
    {
        assert(arch_reg.index() <= map.size());
        map[arch_reg.index()] = phys_reg;
    }
 
    unsigned numFreeEntries() const { return freeList->numFreeRegs(); }
 
    size_t numArchRegs() const { return map.size(); }
 
    iterator begin() { return map.begin(); }
    const_iterator begin() const { return map.begin(); }
    const_iterator cbegin() const { return map.cbegin(); }
    iterator end() { return map.end(); }
    const_iterator end() const { return map.end(); }
    const_iterator cend() const { return map.cend(); }
};
 
class UnifiedRenameMap
{
  private:
    std::array<SimpleRenameMap, CCRegClass + 1> renameMaps;
 
    static inline PhysRegId invalidPhysRegId{};
 
    PhysRegFile *regFile;
 
  public:
 
    typedef SimpleRenameMap::RenameInfo RenameInfo;
 
    typedef std::array<UnifiedRenameMap, MaxThreads> PerThreadUnifiedRenameMap;
 
    UnifiedRenameMap() : regFile(nullptr) {};
 
    ~UnifiedRenameMap() {};
 
    void init(const BaseISA::RegClasses &regClasses,
              PhysRegFile *_regFile, UnifiedFreeList *freeList);
 
    RenameInfo
    rename(const RegId& arch_reg)
    {
        if (!arch_reg.isRenameable()) {
            // misc regs aren't really renamed, just remapped
            PhysRegIdPtr phys_reg = lookup(arch_reg);
            // Set the new register to the previous one to keep the same
            // mapping throughout the execution.
            return RenameInfo(phys_reg, phys_reg);
        }
 
        return renameMaps[arch_reg.classValue()].rename(arch_reg);
    }
 
    PhysRegIdPtr
    lookup(const RegId& arch_reg) const
    {
        auto reg_class = arch_reg.classValue();
        if (reg_class == InvalidRegClass) {
            return &invalidPhysRegId;
        } else if (reg_class == MiscRegClass) {
            // misc regs aren't really renamed, they keep the same
            // mapping throughout the execution.
            return regFile->getMiscRegId(arch_reg.index());
        }
        return renameMaps[reg_class].lookup(arch_reg);
    }
 
    void
    setEntry(const RegId& arch_reg, PhysRegIdPtr phys_reg)
    {
        assert(phys_reg->is(arch_reg.classValue()));
        if (!arch_reg.isRenameable()) {
            // Misc registers do not actually rename, so don't change
            // their mappings.  We end up here when a commit or squash
            // tries to update or undo a hardwired misc reg nmapping,
            // which should always be setting it to what it already is.
            assert(phys_reg == lookup(arch_reg));
            return;
        }
 
        return renameMaps[arch_reg.classValue()].setEntry(arch_reg, phys_reg);
    }
 
    unsigned
    minFreeEntries() const
    {
        auto min_free = std::numeric_limits<unsigned>::max();
        for (auto &map: renameMaps) {
            // If this map isn't empty (not used)...
            if (map.numArchRegs())
                min_free = std::min(min_free, map.numFreeEntries());
        }
        return min_free;
    }
 
    unsigned
    numFreeEntries(RegClassType type) const
    {
        return renameMaps[type].numFreeEntries();
    }
 
    bool canRename(DynInstPtr inst) const;
};
 
} // namespace o3
} // namespace gem5
 
#endif //__CPU_O3_RENAME_MAP_HH__