gem5  v22.1.0.0
regfile.hh
Go to the documentation of this file.
1 /*
2  * Copyright (c) 2016-2018 ARM Limited
3  * All rights reserved
4  *
5  * The license below extends only to copyright in the software and shall
6  * not be construed as granting a license to any other intellectual
7  * property including but not limited to intellectual property relating
8  * to a hardware implementation of the functionality of the software
9  * licensed hereunder. You may use the software subject to the license
10  * terms below provided that you ensure that this notice is replicated
11  * unmodified and in its entirety in all distributions of the software,
12  * modified or unmodified, in source code or in binary form.
13  *
14  * Copyright (c) 2004-2005 The Regents of The University of Michigan
15  * Copyright (c) 2013 Advanced Micro Devices, Inc.
16  * All rights reserved.
17  *
18  * Redistribution and use in source and binary forms, with or without
19  * modification, are permitted provided that the following conditions are
20  * met: redistributions of source code must retain the above copyright
21  * notice, this list of conditions and the following disclaimer;
22  * redistributions in binary form must reproduce the above copyright
23  * notice, this list of conditions and the following disclaimer in the
24  * documentation and/or other materials provided with the distribution;
25  * neither the name of the copyright holders nor the names of its
26  * contributors may be used to endorse or promote products derived from
27  * this software without specific prior written permission.
28  *
29  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40  */
41 
42 #ifndef __CPU_O3_REGFILE_HH__
43 #define __CPU_O3_REGFILE_HH__
44 
45 #include <cstring>
46 #include <vector>
47 
48 #include "arch/generic/isa.hh"
49 #include "base/trace.hh"
50 #include "cpu/o3/comm.hh"
51 #include "cpu/regfile.hh"
52 #include "debug/IEW.hh"
53 
54 namespace gem5
55 {
56 
57 namespace o3
58 {
59 
60 class UnifiedFreeList;
61 
66 {
67  private:
68 
70  public:
71  using IdRange = std::pair<PhysIds::iterator,
72  PhysIds::iterator>;
73  private:
77 
81 
85 
89 
93 
97 
100 
105 
110 
115 
120 
125 
130 
132  unsigned totalNumRegs;
133 
134  public:
139  PhysRegFile(unsigned _numPhysicalIntRegs,
140  unsigned _numPhysicalFloatRegs,
141  unsigned _numPhysicalVecRegs,
142  unsigned _numPhysicalVecPredRegs,
143  unsigned _numPhysicalCCRegs,
144  const BaseISA::RegClasses &classes);
145 
150 
152  void initFreeList(UnifiedFreeList *freeList);
153 
155  unsigned totalNumPhysRegs() const { return totalNumRegs; }
156 
159  return &miscRegIds[reg_idx];
160  }
161 
162  RegVal
163  getReg(PhysRegIdPtr phys_reg) const
164  {
165  const RegClassType type = phys_reg->classValue();
166  const RegIndex idx = phys_reg->index();
167 
168  RegVal val;
169  switch (type) {
170  case IntRegClass:
171  val = intRegFile.reg(idx);
172  DPRINTF(IEW, "RegFile: Access to int register %i, has data %#x\n",
173  idx, val);
174  return val;
175  case FloatRegClass:
176  val = floatRegFile.reg(idx);
177  DPRINTF(IEW, "RegFile: Access to float register %i has data %#x\n",
178  idx, val);
179  return val;
180  case VecElemClass:
181  val = vectorElemRegFile.reg(idx);
182  DPRINTF(IEW, "RegFile: Access to vector element register %i "
183  "has data %#x\n", idx, val);
184  return val;
185  case CCRegClass:
186  val = ccRegFile.reg(idx);
187  DPRINTF(IEW, "RegFile: Access to cc register %i has data %#x\n",
188  idx, val);
189  return val;
190  default:
191  panic("Unsupported register class type %d.", type);
192  }
193  }
194 
195  void
196  getReg(PhysRegIdPtr phys_reg, void *val) const
197  {
198  const RegClassType type = phys_reg->classValue();
199  const RegIndex idx = phys_reg->index();
200 
201  switch (type) {
202  case IntRegClass:
203  *(RegVal *)val = getReg(phys_reg);
204  break;
205  case FloatRegClass:
206  *(RegVal *)val = getReg(phys_reg);
207  break;
208  case VecRegClass:
209  vectorRegFile.get(idx, val);
210  DPRINTF(IEW, "RegFile: Access to vector register %i, has "
211  "data %s\n", idx, vectorRegFile.regClass.valString(val));
212  break;
213  case VecElemClass:
214  *(RegVal *)val = getReg(phys_reg);
215  break;
216  case VecPredRegClass:
217  vecPredRegFile.get(idx, val);
218  DPRINTF(IEW, "RegFile: Access to predicate register %i, has "
219  "data %s\n", idx, vecPredRegFile.regClass.valString(val));
220  break;
221  case CCRegClass:
222  *(RegVal *)val = getReg(phys_reg);
223  break;
224  default:
225  panic("Unrecognized register class type %d.", type);
226  }
227  }
228 
229  void *
231  {
232  const RegClassType type = phys_reg->classValue();
233  const RegIndex idx = phys_reg->index();
234 
235  switch (type) {
236  case VecRegClass:
237  return vectorRegFile.ptr(idx);
238  case VecPredRegClass:
239  return vecPredRegFile.ptr(idx);
240  default:
241  panic("Unrecognized register class type %d.", type);
242  }
243  }
244 
245  void
247  {
248  const RegClassType type = phys_reg->classValue();
249  const RegIndex idx = phys_reg->index();
250 
251  switch (type) {
252  case InvalidRegClass:
253  break;
254  case IntRegClass:
255  intRegFile.reg(idx) = val;
256  DPRINTF(IEW, "RegFile: Setting int register %i to %#x\n",
257  idx, val);
258  break;
259  case FloatRegClass:
260  floatRegFile.reg(idx) = val;
261  DPRINTF(IEW, "RegFile: Setting float register %i to %#x\n",
262  idx, val);
263  break;
264  case VecElemClass:
265  vectorElemRegFile.reg(idx) = val;
266  DPRINTF(IEW, "RegFile: Setting vector element register %i to "
267  "%#x\n", idx, val);
268  break;
269  case CCRegClass:
270  ccRegFile.reg(idx) = val;
271  DPRINTF(IEW, "RegFile: Setting cc register %i to %#x\n",
272  idx, val);
273  break;
274  default:
275  panic("Unsupported register class type %d.", type);
276  }
277  }
278 
279  void
280  setReg(PhysRegIdPtr phys_reg, const void *val)
281  {
282  const RegClassType type = phys_reg->classValue();
283  const RegIndex idx = phys_reg->index();
284 
285  switch (type) {
286  case IntRegClass:
287  setReg(phys_reg, *(RegVal *)val);
288  break;
289  case FloatRegClass:
290  setReg(phys_reg, *(RegVal *)val);
291  break;
292  case VecRegClass:
293  DPRINTF(IEW, "RegFile: Setting vector register %i to %s\n",
295  vectorRegFile.set(idx, val);
296  break;
297  case VecElemClass:
298  setReg(phys_reg, *(RegVal *)val);
299  break;
300  case VecPredRegClass:
301  DPRINTF(IEW, "RegFile: Setting predicate register %i to %s\n",
303  vecPredRegFile.set(idx, val);
304  break;
305  case CCRegClass:
306  setReg(phys_reg, *(RegVal *)val);
307  break;
308  default:
309  panic("Unrecognized register class type %d.", type);
310  }
311  }
312 
319 
326 };
327 
328 } // namespace o3
329 } // namespace gem5
330 
331 #endif //__CPU_O3_REGFILE_HH__
#define DPRINTF(x,...)
Definition: trace.hh:186
Physical register ID.
Definition: reg_class.hh:392
constexpr RegClassType classValue() const
Definition: reg_class.hh:272
constexpr RegIndex index() const
Visible RegId methods.
Definition: reg_class.hh:148
std::string valString(const void *val) const
Definition: reg_class.hh:243
void set(size_t idx, const void *val)
Definition: regfile.hh:99
void get(size_t idx, void *val) const
Definition: regfile.hh:93
void * ptr(size_t idx)
Definition: regfile.hh:81
Reg & reg(size_t idx)
Definition: regfile.hh:66
const RegClass & regClass
Definition: regfile.hh:50
IEW handles both single threaded and SMT IEW (issue/execute/writeback).
Definition: iew.hh:88
Simple physical register file class.
Definition: regfile.hh:66
void setReg(PhysRegIdPtr phys_reg, const void *val)
Definition: regfile.hh:280
RegFile ccRegFile
Condition-code register file.
Definition: regfile.hh:95
std::vector< PhysRegId > vecElemIds
Definition: regfile.hh:88
RegVal getReg(PhysRegIdPtr phys_reg) const
Definition: regfile.hh:163
std::vector< PhysRegId > ccRegIds
Definition: regfile.hh:96
std::vector< PhysRegId > miscRegIds
Misc Reg Ids.
Definition: regfile.hh:99
std::pair< PhysIds::iterator, PhysIds::iterator > IdRange
Definition: regfile.hh:72
PhysRegIdPtr getMiscRegId(RegIndex reg_idx)
Gets a misc register PhysRegIdPtr.
Definition: regfile.hh:158
unsigned totalNumRegs
Total number of physical registers.
Definition: regfile.hh:132
unsigned numPhysicalVecRegs
Number of physical vector registers.
Definition: regfile.hh:114
unsigned numPhysicalCCRegs
Number of physical CC registers.
Definition: regfile.hh:129
void * getWritableReg(PhysRegIdPtr phys_reg)
Definition: regfile.hh:230
unsigned numPhysicalVecPredRegs
Number of physical predicate registers.
Definition: regfile.hh:124
RegFile vectorRegFile
Vector register file.
Definition: regfile.hh:83
~PhysRegFile()
Destructor to free resources.
Definition: regfile.hh:149
RegFile vectorElemRegFile
Vector element register file.
Definition: regfile.hh:87
std::vector< PhysRegId > floatRegIds
Definition: regfile.hh:80
std::vector< PhysRegId > vecRegIds
Definition: regfile.hh:84
RegFile vecPredRegFile
Predicate register file.
Definition: regfile.hh:91
IdRange getRegIds(RegClassType cls)
Get the PhysRegIds of the elems of all vector registers.
Definition: regfile.cc:179
RegFile intRegFile
Integer register file.
Definition: regfile.hh:75
RegFile floatRegFile
Floating point register file.
Definition: regfile.hh:79
unsigned totalNumPhysRegs() const
Definition: regfile.hh:155
PhysRegFile(unsigned _numPhysicalIntRegs, unsigned _numPhysicalFloatRegs, unsigned _numPhysicalVecRegs, unsigned _numPhysicalVecPredRegs, unsigned _numPhysicalCCRegs, const BaseISA::RegClasses &classes)
Constructs a physical register file with the specified amount of integer and floating point registers...
Definition: regfile.cc:52
unsigned numPhysicalVecElemRegs
Number of physical vector element registers.
Definition: regfile.hh:119
unsigned numPhysicalFloatRegs
Number of physical floating point registers.
Definition: regfile.hh:109
std::vector< PhysRegId > intRegIds
Definition: regfile.hh:76
std::vector< PhysRegId > vecPredRegIds
Definition: regfile.hh:92
void getReg(PhysRegIdPtr phys_reg, void *val) const
Definition: regfile.hh:196
unsigned numPhysicalIntRegs
Number of physical general purpose registers.
Definition: regfile.hh:104
void setReg(PhysRegIdPtr phys_reg, RegVal val)
Definition: regfile.hh:246
PhysRegIdPtr getTrueId(PhysRegIdPtr reg)
Get the true physical register id.
Definition: regfile.cc:206
void initFreeList(UnifiedFreeList *freeList)
Initialize the free list.
Definition: regfile.cc:134
FreeList class that simply holds the list of free integer and floating point registers.
Definition: free_list.hh:125
STL pair class.
Definition: stl.hh:58
STL vector class.
Definition: stl.hh:37
#define panic(...)
This implements a cprintf based panic() function.
Definition: logging.hh:178
Bitfield< 5, 3 > reg
Definition: types.hh:92
Bitfield< 63 > val
Definition: misc.hh:776
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
uint16_t RegIndex
Definition: types.hh:176
uint64_t RegVal
Definition: types.hh:173
RegClassType
Enumerate the classes of registers.
Definition: reg_class.hh:59
@ VecPredRegClass
Definition: reg_class.hh:66
@ FloatRegClass
Floating-point register.
Definition: reg_class.hh:61
@ CCRegClass
Condition-code register.
Definition: reg_class.hh:67
@ VecRegClass
Vector Register.
Definition: reg_class.hh:63
@ IntRegClass
Integer register.
Definition: reg_class.hh:60
@ InvalidRegClass
Definition: reg_class.hh:69
@ VecElemClass
Vector Register Native Elem lane.
Definition: reg_class.hh:65

Generated on Wed Dec 21 2022 10:22:31 for gem5 by doxygen 1.9.1