gem5  v22.0.0.2
regfile.hh
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41 
42 #ifndef __CPU_O3_REGFILE_HH__
43 #define __CPU_O3_REGFILE_HH__
44 
45 #include <cstring>
46 #include <vector>
47 
48 #include "arch/generic/isa.hh"
49 #include "arch/vecregs.hh"
50 #include "base/trace.hh"
51 #include "config/the_isa.hh"
52 #include "cpu/o3/comm.hh"
53 #include "cpu/regfile.hh"
54 #include "debug/IEW.hh"
55 
56 namespace gem5
57 {
58 
59 namespace o3
60 {
61 
62 class UnifiedFreeList;
63 
68 {
69  private:
70 
72  public:
73  using IdRange = std::pair<PhysIds::iterator,
74  PhysIds::iterator>;
75  private:
79 
83 
87 
91 
95 
99 
102 
107 
112 
117 
122 
127 
132 
134  unsigned totalNumRegs;
135 
136  public:
141  PhysRegFile(unsigned _numPhysicalIntRegs,
142  unsigned _numPhysicalFloatRegs,
143  unsigned _numPhysicalVecRegs,
144  unsigned _numPhysicalVecPredRegs,
145  unsigned _numPhysicalCCRegs,
146  const BaseISA::RegClasses &classes);
147 
152 
154  void initFreeList(UnifiedFreeList *freeList);
155 
157  unsigned totalNumPhysRegs() const { return totalNumRegs; }
158 
161  return &miscRegIds[reg_idx];
162  }
163 
164  RegVal
165  getReg(PhysRegIdPtr phys_reg) const
166  {
167  const RegClassType type = phys_reg->classValue();
168  const RegIndex idx = phys_reg->index();
169 
170  RegVal val;
171  switch (type) {
172  case IntRegClass:
173  val = intRegFile.reg(idx);
174  DPRINTF(IEW, "RegFile: Access to int register %i, has data %#x\n",
175  idx, val);
176  return val;
177  case FloatRegClass:
178  val = floatRegFile.reg(idx);
179  DPRINTF(IEW, "RegFile: Access to float register %i has data %#x\n",
180  idx, val);
181  return val;
182  case VecElemClass:
183  val = vectorElemRegFile.reg(idx);
184  DPRINTF(IEW, "RegFile: Access to vector element register %i "
185  "has data %#x\n", idx, val);
186  return val;
187  case CCRegClass:
188  val = ccRegFile.reg(idx);
189  DPRINTF(IEW, "RegFile: Access to cc register %i has data %#x\n",
190  idx, val);
191  return val;
192  default:
193  panic("Unsupported register class type %d.", type);
194  }
195  }
196 
197  void
198  getReg(PhysRegIdPtr phys_reg, void *val) const
199  {
200  const RegClassType type = phys_reg->classValue();
201  const RegIndex idx = phys_reg->index();
202 
203  switch (type) {
204  case IntRegClass:
205  *(RegVal *)val = getReg(phys_reg);
206  break;
207  case FloatRegClass:
208  *(RegVal *)val = getReg(phys_reg);
209  break;
210  case VecRegClass:
211  vectorRegFile.get(idx, val);
212  DPRINTF(IEW, "RegFile: Access to vector register %i, has "
213  "data %s\n", idx, vectorRegFile.regClass.valString(val));
214  break;
215  case VecElemClass:
216  *(RegVal *)val = getReg(phys_reg);
217  break;
218  case VecPredRegClass:
219  vecPredRegFile.get(idx, val);
220  DPRINTF(IEW, "RegFile: Access to predicate register %i, has "
221  "data %s\n", idx, vecPredRegFile.regClass.valString(val));
222  break;
223  case CCRegClass:
224  *(RegVal *)val = getReg(phys_reg);
225  break;
226  default:
227  panic("Unrecognized register class type %d.", type);
228  }
229  }
230 
231  void *
233  {
234  const RegClassType type = phys_reg->classValue();
235  const RegIndex idx = phys_reg->index();
236 
237  switch (type) {
238  case VecRegClass:
239  return vectorRegFile.ptr(idx);
240  case VecPredRegClass:
241  return vecPredRegFile.ptr(idx);
242  default:
243  panic("Unrecognized register class type %d.", type);
244  }
245  }
246 
247  void
249  {
250  const RegClassType type = phys_reg->classValue();
251  const RegIndex idx = phys_reg->index();
252 
253  switch (type) {
254  case InvalidRegClass:
255  break;
256  case IntRegClass:
257  intRegFile.reg(idx) = val;
258  DPRINTF(IEW, "RegFile: Setting int register %i to %#x\n",
259  idx, val);
260  break;
261  case FloatRegClass:
262  floatRegFile.reg(idx) = val;
263  DPRINTF(IEW, "RegFile: Setting float register %i to %#x\n",
264  idx, val);
265  break;
266  case VecElemClass:
267  vectorElemRegFile.reg(idx) = val;
268  DPRINTF(IEW, "RegFile: Setting vector element register %i to "
269  "%#x\n", idx, val);
270  break;
271  case CCRegClass:
272  ccRegFile.reg(idx) = val;
273  DPRINTF(IEW, "RegFile: Setting cc register %i to %#x\n",
274  idx, val);
275  break;
276  default:
277  panic("Unsupported register class type %d.", type);
278  }
279  }
280 
281  void
282  setReg(PhysRegIdPtr phys_reg, const void *val)
283  {
284  const RegClassType type = phys_reg->classValue();
285  const RegIndex idx = phys_reg->index();
286 
287  switch (type) {
288  case IntRegClass:
289  setReg(phys_reg, *(RegVal *)val);
290  break;
291  case FloatRegClass:
292  setReg(phys_reg, *(RegVal *)val);
293  break;
294  case VecRegClass:
295  DPRINTF(IEW, "RegFile: Setting vector register %i to %s\n",
297  vectorRegFile.set(idx, val);
298  break;
299  case VecElemClass:
300  setReg(phys_reg, *(RegVal *)val);
301  break;
302  case VecPredRegClass:
303  DPRINTF(IEW, "RegFile: Setting predicate register %i to %s\n",
305  vecPredRegFile.set(idx, val);
306  break;
307  case CCRegClass:
308  setReg(phys_reg, *(RegVal *)val);
309  break;
310  default:
311  panic("Unrecognized register class type %d.", type);
312  }
313  }
314 
321 
328 };
329 
330 } // namespace o3
331 } // namespace gem5
332 
333 #endif //__CPU_O3_REGFILE_HH__
gem5::RegFile::ptr
void * ptr(size_t idx)
Definition: regfile.hh:81
gem5::RegVal
uint64_t RegVal
Definition: types.hh:173
gem5::o3::PhysRegFile::numPhysicalVecElemRegs
unsigned numPhysicalVecElemRegs
Number of physical vector element registers.
Definition: regfile.hh:121
gem5::o3::PhysRegFile::vectorElemRegFile
RegFile vectorElemRegFile
Vector element register file.
Definition: regfile.hh:89
gem5::VecElemClass
@ VecElemClass
Vector Register Native Elem lane.
Definition: reg_class.hh:63
gem5::InvalidRegClass
@ InvalidRegClass
Definition: reg_class.hh:67
gem5::o3::PhysRegFile::ccRegFile
RegFile ccRegFile
Condition-code register file.
Definition: regfile.hh:97
gem5::o3::PhysRegFile::getRegIds
IdRange getRegIds(RegClassType cls)
Get the PhysRegIds of the elems of all vector registers.
Definition: regfile.cc:172
gem5::CCRegClass
@ CCRegClass
Condition-code register.
Definition: reg_class.hh:65
gem5::o3::PhysRegFile::getWritableReg
void * getWritableReg(PhysRegIdPtr phys_reg)
Definition: regfile.hh:232
gem5::X86ISA::val
Bitfield< 63 > val
Definition: misc.hh:769
gem5::RegFile::get
void get(size_t idx, void *val) const
Definition: regfile.hh:93
gem5::RegClass::valString
std::string valString(const void *val) const
Definition: reg_class.hh:115
gem5::o3::PhysRegFile::setReg
void setReg(PhysRegIdPtr phys_reg, RegVal val)
Definition: regfile.hh:248
gem5::o3::UnifiedFreeList
FreeList class that simply holds the list of free integer and floating point registers.
Definition: free_list.hh:124
gem5::o3::PhysRegFile::ccRegIds
std::vector< PhysRegId > ccRegIds
Definition: regfile.hh:98
std::vector
STL vector class.
Definition: stl.hh:37
gem5::o3::PhysRegFile::PhysRegFile
PhysRegFile(unsigned _numPhysicalIntRegs, unsigned _numPhysicalFloatRegs, unsigned _numPhysicalVecRegs, unsigned _numPhysicalVecPredRegs, unsigned _numPhysicalCCRegs, const BaseISA::RegClasses &classes)
Constructs a physical register file with the specified amount of integer and floating point registers...
Definition: regfile.cc:52
gem5::VecPredRegClass
@ VecPredRegClass
Definition: reg_class.hh:64
gem5::o3::PhysRegFile::getTrueId
PhysRegIdPtr getTrueId(PhysRegIdPtr reg)
Get the true physical register id.
Definition: regfile.cc:199
gem5::o3::PhysRegFile::numPhysicalVecRegs
unsigned numPhysicalVecRegs
Number of physical vector registers.
Definition: regfile.hh:116
gem5::o3::PhysRegFile::floatRegIds
std::vector< PhysRegId > floatRegIds
Definition: regfile.hh:82
comm.hh
gem5::FloatRegClass
@ FloatRegClass
Floating-point register.
Definition: reg_class.hh:59
gem5::o3::PhysRegFile::miscRegIds
std::vector< PhysRegId > miscRegIds
Misc Reg Ids.
Definition: regfile.hh:101
gem5::o3::PhysRegFile::vecElemIds
std::vector< PhysRegId > vecElemIds
Definition: regfile.hh:90
DPRINTF
#define DPRINTF(x,...)
Definition: trace.hh:186
gem5::RegFile
Definition: regfile.hh:41
gem5::o3::PhysRegFile::setReg
void setReg(PhysRegIdPtr phys_reg, const void *val)
Definition: regfile.hh:282
gem5::o3::PhysRegFile
Simple physical register file class.
Definition: regfile.hh:67
gem5::o3::PhysRegFile::getReg
RegVal getReg(PhysRegIdPtr phys_reg) const
Definition: regfile.hh:165
gem5::o3::IEW
IEW handles both single threaded and SMT IEW (issue/execute/writeback).
Definition: iew.hh:87
gem5::X86ISA::type
type
Definition: misc.hh:727
gem5::o3::PhysRegFile::vectorRegFile
RegFile vectorRegFile
Vector register file.
Definition: regfile.hh:85
gem5::o3::PhysRegFile::vecRegIds
std::vector< PhysRegId > vecRegIds
Definition: regfile.hh:86
gem5::RegFile::reg
Reg & reg(size_t idx)
Definition: regfile.hh:66
gem5::o3::PhysRegFile::IdRange
std::pair< PhysIds::iterator, PhysIds::iterator > IdRange
Definition: regfile.hh:74
gem5::RegFile::regClass
const RegClass & regClass
Definition: regfile.hh:50
std::pair
STL pair class.
Definition: stl.hh:58
gem5::o3::PhysRegFile::intRegIds
std::vector< PhysRegId > intRegIds
Definition: regfile.hh:78
regfile.hh
gem5::o3::PhysRegFile::numPhysicalIntRegs
unsigned numPhysicalIntRegs
Number of physical general purpose registers.
Definition: regfile.hh:106
gem5::o3::PhysRegFile::~PhysRegFile
~PhysRegFile()
Destructor to free resources.
Definition: regfile.hh:151
gem5::X86ISA::reg
Bitfield< 5, 3 > reg
Definition: types.hh:92
gem5::o3::PhysRegFile::numPhysicalVecPredRegs
unsigned numPhysicalVecPredRegs
Number of physical predicate registers.
Definition: regfile.hh:126
gem5::o3::PhysRegFile::getReg
void getReg(PhysRegIdPtr phys_reg, void *val) const
Definition: regfile.hh:198
gem5::IntRegClass
@ IntRegClass
Integer register.
Definition: reg_class.hh:58
isa.hh
gem5::RegClassType
RegClassType
Enumerate the classes of registers.
Definition: reg_class.hh:56
gem5::o3::PhysRegFile::getMiscRegId
PhysRegIdPtr getMiscRegId(RegIndex reg_idx)
Gets a misc register PhysRegIdPtr.
Definition: regfile.hh:160
gem5::o3::PhysRegFile::totalNumRegs
unsigned totalNumRegs
Total number of physical registers.
Definition: regfile.hh:134
gem5::o3::PhysRegFile::numPhysicalCCRegs
unsigned numPhysicalCCRegs
Number of physical CC registers.
Definition: regfile.hh:131
gem5::o3::PhysRegFile::initFreeList
void initFreeList(UnifiedFreeList *freeList)
Initialize the free list.
Definition: regfile.cc:127
gem5::o3::PhysRegFile::vecPredRegIds
std::vector< PhysRegId > vecPredRegIds
Definition: regfile.hh:94
gem5::RegFile::set
void set(size_t idx, const void *val)
Definition: regfile.hh:99
gem5::PhysRegId
Physical register ID.
Definition: reg_class.hh:245
gem5::PhysRegId::index
constexpr RegIndex index() const
Visible RegId methods.
Definition: reg_class.hh:188
trace.hh
gem5::o3::PhysRegFile::numPhysicalFloatRegs
unsigned numPhysicalFloatRegs
Number of physical floating point registers.
Definition: regfile.hh:111
gem5::VecRegClass
@ VecRegClass
Vector Register.
Definition: reg_class.hh:61
gem5::o3::PhysRegFile::vecPredRegFile
RegFile vecPredRegFile
Predicate register file.
Definition: regfile.hh:93
gem5::RegIndex
uint16_t RegIndex
Definition: types.hh:176
gem5::o3::PhysRegFile::floatRegFile
RegFile floatRegFile
Floating point register file.
Definition: regfile.hh:81
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: gpu_translation_state.hh:37
gem5::PhysRegId::classValue
constexpr RegClassType classValue() const
Class accessor.
Definition: reg_class.hh:191
gem5::o3::PhysRegFile::intRegFile
RegFile intRegFile
Integer register file.
Definition: regfile.hh:77
panic
#define panic(...)
This implements a cprintf based panic() function.
Definition: logging.hh:178
gem5::o3::PhysRegFile::totalNumPhysRegs
unsigned totalNumPhysRegs() const
Definition: regfile.hh:157

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