gem5  v22.0.0.1
gpu_static_inst.cc
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31 
33 
34 #include "debug/GPUInst.hh"
35 
36 namespace gem5
37 {
38 
40  : executed_as(enums::SC_NONE), _opcode(opcode),
41  _instNum(0), _instAddr(0), srcVecDWords(-1), dstVecDWords(-1),
42  srcScalarDWords(-1), dstScalarDWords(-1), maxOpSize(-1)
43 {
44 }
45 
46 const std::string&
48 {
49  if (disassembly.empty()) {
51  assert(!disassembly.empty());
52  }
53 
54  return disassembly;
55 }
56 
57 void
59 {
60  // Lambda function, as this is only ever used here
61  auto generateVirtToPhysMap = [&](OperandInfo& op,
63  MapRegFn mapFn, OpType opType)
64  {
65  std::vector<int> virt_idxs;
66  std::vector<int> phys_idxs;
67 
68  int num_dwords = op.sizeInDWords();
69  int virt_idx = op.registerIndex(wf->reservedScalarRegs);
70 
71  int phys_idx = -1;
72  for (int i = 0; i < num_dwords; i++){
73  phys_idx = (cu->registerManager->*mapFn)(wf, virt_idx + i);
74  virt_idxs.push_back(virt_idx + i);
75  phys_idxs.push_back(phys_idx);
76  }
77  DPRINTF(GPUInst, "%s adding %s %s (%d->%d) operand that uses "
78  "%d registers.\n", disassemble(),
79  (opType == OpType::SRC_VEC || opType == OpType::DST_VEC) ?
80  "vector" : "scalar",
81  (opType == OpType::SRC_VEC || opType == OpType::SRC_SCALAR) ?
82  "src" : "dst", virt_idxs[0], phys_idxs[0], num_dwords);
83 
84  op.setVirtToPhysMapping(virt_idxs, phys_idxs);
85 
86  opVec.emplace_back(op);
87  };
88 
89  for (auto& srcOp : srcOps) {
90  if (srcOp.isVectorReg()) {
91  generateVirtToPhysMap(srcOp, srcVecRegOps,
92  &RegisterManager::mapVgpr, OpType::SRC_VEC);
93  } else if (srcOp.isScalarReg()) {
94  generateVirtToPhysMap(srcOp, srcScalarRegOps,
95  &RegisterManager::mapSgpr, OpType::SRC_SCALAR);
96  }
97  }
98 
99  for (auto& dstOp : dstOps) {
100  if (dstOp.isVectorReg()) {
101  generateVirtToPhysMap(dstOp, dstVecRegOps,
102  &RegisterManager::mapVgpr, OpType::DST_VEC);
103  } else if (dstOp.isScalarReg()) {
104  generateVirtToPhysMap(dstOp, dstScalarRegOps,
105  &RegisterManager::mapSgpr, OpType::DST_SCALAR);
106  }
107  }
108 }
109 
110 int
112 {
113  return srcVecRegOps.size();
114 }
115 
116 int
118 {
119  return dstVecRegOps.size();
120 }
121 
122 int
124 {
125  if (srcVecDWords != -1) {
126  return srcVecDWords;
127  }
128 
129  srcVecDWords = 0;
130 
131  for (const auto& srcOp : srcOps)
132  if (srcOp.isVectorReg())
133  srcVecDWords += srcOp.sizeInDWords();
134 
135  return srcVecDWords;
136 }
137 
138 int
140 {
141  if (dstVecDWords != -1) {
142  return dstVecDWords;
143  }
144 
145  dstVecDWords = 0;
146 
147  for (const auto& dstOp : dstOps)
148  if (dstOp.isVectorReg())
149  dstVecDWords += dstOp.sizeInDWords();
150 
151  return dstVecDWords;
152 }
153 
154 int
156 {
157  return srcScalarRegOps.size();
158 }
159 
160 int
162 {
163  return dstScalarRegOps.size();
164 }
165 
166 int
168 {
169  if (srcScalarDWords != -1)
170  return srcScalarDWords;
171 
172  srcScalarDWords = 0;
173 
174  for (const auto& srcOp : srcOps)
175  if (srcOp.isScalarReg())
176  srcScalarDWords += srcOp.sizeInDWords();
177 
178  return srcScalarDWords;
179 }
180 
181 int
183 {
184  if (dstScalarDWords != -1)
185  return dstScalarDWords;
186 
187  dstScalarDWords = 0;
188 
189  for (const auto& dstOp : dstOps)
190  if (dstOp.isScalarReg())
191  dstScalarDWords += dstOp.sizeInDWords();
192 
193  return dstScalarDWords;
194 }
195 
196 int
198 {
199  if (maxOpSize != -1)
200  return maxOpSize;
201 
202  maxOpSize = 0;
203 
204  for (const auto& dstOp : dstOps)
205  if (dstOp.size() > maxOpSize)
206  maxOpSize = dstOp.size();
207 
208  for (const auto& srcOp : srcOps)
209  if (srcOp.size() > maxOpSize)
210  maxOpSize = srcOp.size();
211 
212  return maxOpSize;
213 }
214 
215 } // namespace gem5
gem5::GPUStaticInst::initDynOperandInfo
void initDynOperandInfo(Wavefront *wf, ComputeUnit *cu)
Definition: gpu_static_inst.cc:58
gem5::GPUStaticInst::numSrcVecOperands
int numSrcVecOperands()
Definition: gpu_static_inst.cc:111
gem5::GPUStaticInst::GPUStaticInst
GPUStaticInst(const std::string &opcode)
Definition: gpu_static_inst.cc:39
gem5::GPUStaticInst::disassemble
const std::string & disassemble()
Definition: gpu_static_inst.cc:47
gem5::OperandInfo
Definition: operand_info.hh:42
gem5::Wavefront
Definition: wavefront.hh:60
gem5::GPUStaticInst::disassembly
std::string disassembly
Definition: gpu_static_inst.hh:299
gem5::GPUStaticInst::srcOps
std::vector< OperandInfo > srcOps
Definition: gpu_static_inst.hh:302
gem5::GPUStaticInst::srcVecDWords
int srcVecDWords
Definition: gpu_static_inst.hh:306
gpu_static_inst.hh
std::vector
STL vector class.
Definition: stl.hh:37
gem5::ArmISA::i
Bitfield< 7 > i
Definition: misc_types.hh:67
gem5::GPUStaticInst::numDstVecOperands
int numDstVecOperands()
Definition: gpu_static_inst.cc:117
gem5::GPUStaticInst::srcScalarRegOps
std::vector< OperandInfo > srcScalarRegOps
Definition: gpu_static_inst.hh:314
gem5::RegisterManager::mapSgpr
int mapSgpr(Wavefront *w, int sgprIndex)
Definition: register_manager.cc:102
gem5::ComputeUnit
Definition: compute_unit.hh:201
gem5::ArmISA::opcode
Bitfield< 24, 21 > opcode
Definition: types.hh:92
gem5::GPUStaticInst::numDstScalarDWords
int numDstScalarDWords()
Definition: gpu_static_inst.cc:182
gem5::Wavefront::reservedScalarRegs
int reservedScalarRegs
Definition: wavefront.hh:196
gem5::GPUStaticInst::maxOperandSize
int maxOperandSize()
Definition: gpu_static_inst.cc:197
DPRINTF
#define DPRINTF(x,...)
Definition: trace.hh:186
gem5::GPUStaticInst::numDstVecDWords
int numDstVecDWords()
Definition: gpu_static_inst.cc:139
gem5::GPUStaticInst::dstOps
std::vector< OperandInfo > dstOps
Definition: gpu_static_inst.hh:303
gem5::ComputeUnit::registerManager
RegisterManager * registerManager
Definition: compute_unit.hh:278
gem5::GPUStaticInst::numDstScalarOperands
int numDstScalarOperands()
Definition: gpu_static_inst.cc:161
gem5::GPUStaticInst::numSrcScalarDWords
int numSrcScalarDWords()
Definition: gpu_static_inst.cc:167
gem5::GPUStaticInst::generateDisassembly
virtual void generateDisassembly()=0
gem5::GPUStaticInst::MapRegFn
int(RegisterManager::* MapRegFn)(Wavefront *, int)
Definition: gpu_static_inst.hh:294
gem5::RegisterManager::mapVgpr
int mapVgpr(Wavefront *w, int vgprIndex)
Definition: register_manager.cc:95
gem5::GPUStaticInst::OpType
OpType
Definition: gpu_static_inst.hh:295
gem5::GPUStaticInst::numSrcScalarOperands
int numSrcScalarOperands()
Definition: gpu_static_inst.cc:155
gem5::GPUStaticInst::srcScalarDWords
int srcScalarDWords
Definition: gpu_static_inst.hh:308
gem5::GPUStaticInst::dstScalarRegOps
std::vector< OperandInfo > dstScalarRegOps
Definition: gpu_static_inst.hh:315
gem5::GPUStaticInst::dstScalarDWords
int dstScalarDWords
Definition: gpu_static_inst.hh:309
sc_core::SC_NONE
@ SC_NONE
Definition: sc_report.hh:50
gem5::GPUStaticInst::numSrcVecDWords
int numSrcVecDWords()
Definition: gpu_static_inst.cc:123
gem5::GPUStaticInst::dstVecRegOps
std::vector< OperandInfo > dstVecRegOps
Definition: gpu_static_inst.hh:313
gem5::GPUStaticInst::dstVecDWords
int dstVecDWords
Definition: gpu_static_inst.hh:307
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: gpu_translation_state.hh:37
gem5::X86ISA::op
Bitfield< 4 > op
Definition: types.hh:83
gem5::GPUStaticInst::srcVecRegOps
std::vector< OperandInfo > srcVecRegOps
Definition: gpu_static_inst.hh:312
gem5::GPUStaticInst::maxOpSize
int maxOpSize
Definition: gpu_static_inst.hh:310

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