gem5  v21.1.0.2
gpu_static_inst.cc
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33 
35 
36 #include "debug/GPUInst.hh"
37 
38 namespace gem5
39 {
40 
42  : executed_as(enums::SC_NONE), _opcode(opcode),
43  _instNum(0), _instAddr(0), srcVecDWords(-1), dstVecDWords(-1),
44  srcScalarDWords(-1), dstScalarDWords(-1), maxOpSize(-1)
45 {
46 }
47 
48 const std::string&
50 {
51  if (disassembly.empty()) {
53  assert(!disassembly.empty());
54  }
55 
56  return disassembly;
57 }
58 
59 void
61 {
62  // Lambda function, as this is only ever used here
63  auto generateVirtToPhysMap = [&](OperandInfo& op,
65  MapRegFn mapFn, OpType opType)
66  {
67  std::vector<int> virt_idxs;
68  std::vector<int> phys_idxs;
69 
70  int num_dwords = op.sizeInDWords();
71  int virt_idx = op.registerIndex(wf->reservedScalarRegs);
72 
73  int phys_idx = -1;
74  for (int i = 0; i < num_dwords; i++){
75  phys_idx = (cu->registerManager->*mapFn)(wf, virt_idx + i);
76  virt_idxs.push_back(virt_idx + i);
77  phys_idxs.push_back(phys_idx);
78  }
79  DPRINTF(GPUInst, "%s adding %s %s (%d->%d) operand that uses "
80  "%d registers.\n", disassemble(),
81  (opType == OpType::SRC_VEC || opType == OpType::DST_VEC) ?
82  "vector" : "scalar",
83  (opType == OpType::SRC_VEC || opType == OpType::SRC_SCALAR) ?
84  "src" : "dst", virt_idxs[0], phys_idxs[0], num_dwords);
85 
86  op.setVirtToPhysMapping(virt_idxs, phys_idxs);
87 
88  opVec.emplace_back(op);
89  };
90 
91  for (auto& srcOp : srcOps) {
92  if (srcOp.isVectorReg()) {
93  generateVirtToPhysMap(srcOp, srcVecRegOps,
94  &RegisterManager::mapVgpr, OpType::SRC_VEC);
95  } else if (srcOp.isScalarReg()) {
96  generateVirtToPhysMap(srcOp, srcScalarRegOps,
97  &RegisterManager::mapSgpr, OpType::SRC_SCALAR);
98  }
99  }
100 
101  for (auto& dstOp : dstOps) {
102  if (dstOp.isVectorReg()) {
103  generateVirtToPhysMap(dstOp, dstVecRegOps,
104  &RegisterManager::mapVgpr, OpType::DST_VEC);
105  } else if (dstOp.isScalarReg()) {
106  generateVirtToPhysMap(dstOp, dstScalarRegOps,
107  &RegisterManager::mapSgpr, OpType::DST_SCALAR);
108  }
109  }
110 }
111 
112 int
114 {
115  return srcVecRegOps.size();
116 }
117 
118 int
120 {
121  return dstVecRegOps.size();
122 }
123 
124 int
126 {
127  if (srcVecDWords != -1) {
128  return srcVecDWords;
129  }
130 
131  srcVecDWords = 0;
132 
133  for (const auto& srcOp : srcOps)
134  if (srcOp.isVectorReg())
135  srcVecDWords += srcOp.sizeInDWords();
136 
137  return srcVecDWords;
138 }
139 
140 int
142 {
143  if (dstVecDWords != -1) {
144  return dstVecDWords;
145  }
146 
147  dstVecDWords = 0;
148 
149  for (const auto& dstOp : dstOps)
150  if (dstOp.isVectorReg())
151  dstVecDWords += dstOp.sizeInDWords();
152 
153  return dstVecDWords;
154 }
155 
156 int
158 {
159  return srcScalarRegOps.size();
160 }
161 
162 int
164 {
165  return dstScalarRegOps.size();
166 }
167 
168 int
170 {
171  if (srcScalarDWords != -1)
172  return srcScalarDWords;
173 
174  srcScalarDWords = 0;
175 
176  for (const auto& srcOp : srcOps)
177  if (srcOp.isScalarReg())
178  srcScalarDWords += srcOp.sizeInDWords();
179 
180  return srcScalarDWords;
181 }
182 
183 int
185 {
186  if (dstScalarDWords != -1)
187  return dstScalarDWords;
188 
189  dstScalarDWords = 0;
190 
191  for (const auto& dstOp : dstOps)
192  if (dstOp.isScalarReg())
193  dstScalarDWords += dstOp.sizeInDWords();
194 
195  return dstScalarDWords;
196 }
197 
198 int
200 {
201  if (maxOpSize != -1)
202  return maxOpSize;
203 
204  maxOpSize = 0;
205 
206  for (const auto& dstOp : dstOps)
207  if (dstOp.size() > maxOpSize)
208  maxOpSize = dstOp.size();
209 
210  for (const auto& srcOp : srcOps)
211  if (srcOp.size() > maxOpSize)
212  maxOpSize = srcOp.size();
213 
214  return maxOpSize;
215 }
216 
217 } // namespace gem5
gem5::GPUStaticInst::initDynOperandInfo
void initDynOperandInfo(Wavefront *wf, ComputeUnit *cu)
Definition: gpu_static_inst.cc:60
gem5::GPUStaticInst::numSrcVecOperands
int numSrcVecOperands()
Definition: gpu_static_inst.cc:113
gem5::GPUStaticInst::GPUStaticInst
GPUStaticInst(const std::string &opcode)
Definition: gpu_static_inst.cc:41
gem5::GPUStaticInst::disassemble
const std::string & disassemble()
Definition: gpu_static_inst.cc:49
gem5::OperandInfo
Definition: operand_info.hh:44
gem5::Wavefront
Definition: wavefront.hh:62
gem5::GPUStaticInst::disassembly
std::string disassembly
Definition: gpu_static_inst.hh:300
gem5::GPUStaticInst::srcOps
std::vector< OperandInfo > srcOps
Definition: gpu_static_inst.hh:303
gem5::GPUStaticInst::srcVecDWords
int srcVecDWords
Definition: gpu_static_inst.hh:307
gpu_static_inst.hh
std::vector
STL vector class.
Definition: stl.hh:37
gem5::ArmISA::i
Bitfield< 7 > i
Definition: misc_types.hh:66
gem5::GPUStaticInst::numDstVecOperands
int numDstVecOperands()
Definition: gpu_static_inst.cc:119
gem5::GPUStaticInst::srcScalarRegOps
std::vector< OperandInfo > srcScalarRegOps
Definition: gpu_static_inst.hh:315
gem5::RegisterManager::mapSgpr
int mapSgpr(Wavefront *w, int sgprIndex)
Definition: register_manager.cc:104
gem5::ComputeUnit
Definition: compute_unit.hh:203
gem5::ArmISA::opcode
Bitfield< 24, 21 > opcode
Definition: types.hh:92
gem5::GPUStaticInst::numDstScalarDWords
int numDstScalarDWords()
Definition: gpu_static_inst.cc:184
gem5::Wavefront::reservedScalarRegs
int reservedScalarRegs
Definition: wavefront.hh:198
gem5::GPUStaticInst::maxOperandSize
int maxOperandSize()
Definition: gpu_static_inst.cc:199
DPRINTF
#define DPRINTF(x,...)
Definition: trace.hh:186
gem5::GPUStaticInst::numDstVecDWords
int numDstVecDWords()
Definition: gpu_static_inst.cc:141
gem5::GPUStaticInst::dstOps
std::vector< OperandInfo > dstOps
Definition: gpu_static_inst.hh:304
gem5::ComputeUnit::registerManager
RegisterManager * registerManager
Definition: compute_unit.hh:280
gem5::GPUStaticInst::numDstScalarOperands
int numDstScalarOperands()
Definition: gpu_static_inst.cc:163
gem5::GPUStaticInst::numSrcScalarDWords
int numSrcScalarDWords()
Definition: gpu_static_inst.cc:169
gem5::GPUStaticInst::generateDisassembly
virtual void generateDisassembly()=0
gem5::GPUStaticInst::MapRegFn
int(RegisterManager::* MapRegFn)(Wavefront *, int)
Definition: gpu_static_inst.hh:295
gem5::RegisterManager::mapVgpr
int mapVgpr(Wavefront *w, int vgprIndex)
Definition: register_manager.cc:97
gem5::GPUStaticInst::OpType
OpType
Definition: gpu_static_inst.hh:296
gem5::GPUStaticInst::numSrcScalarOperands
int numSrcScalarOperands()
Definition: gpu_static_inst.cc:157
gem5::GPUStaticInst::srcScalarDWords
int srcScalarDWords
Definition: gpu_static_inst.hh:309
gem5::GPUStaticInst::dstScalarRegOps
std::vector< OperandInfo > dstScalarRegOps
Definition: gpu_static_inst.hh:316
gem5::GPUStaticInst::dstScalarDWords
int dstScalarDWords
Definition: gpu_static_inst.hh:310
sc_core::SC_NONE
@ SC_NONE
Definition: sc_report.hh:50
gem5::GPUStaticInst::numSrcVecDWords
int numSrcVecDWords()
Definition: gpu_static_inst.cc:125
gem5::GPUStaticInst::dstVecRegOps
std::vector< OperandInfo > dstVecRegOps
Definition: gpu_static_inst.hh:314
gem5::GPUStaticInst::dstVecDWords
int dstVecDWords
Definition: gpu_static_inst.hh:308
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40
gem5::X86ISA::op
Bitfield< 4 > op
Definition: types.hh:83
gem5::GPUStaticInst::srcVecRegOps
std::vector< OperandInfo > srcVecRegOps
Definition: gpu_static_inst.hh:313
gem5::GPUStaticInst::maxOpSize
int maxOpSize
Definition: gpu_static_inst.hh:311

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