gem5  v22.0.0.2
hbm_ctrl.hh
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28 
34 #ifndef __HBM_CTRL_HH__
35 #define __HBM_CTRL_HH__
36 
37 #include <deque>
38 #include <string>
39 #include <unordered_set>
40 #include <utility>
41 #include <vector>
42 
43 #include "mem/mem_ctrl.hh"
44 #include "params/HBMCtrl.hh"
45 
46 namespace gem5
47 {
48 
49 namespace memory
50 {
51 
52 class MemInterface;
53 class DRAMInterface;
54 
55 
64 class HBMCtrl : public MemCtrl
65 {
66 
67  protected:
68 
69  bool respQEmpty() override
70  {
71  return (respQueue.empty() && respQueuePC1.empty());
72  }
73 
74  private:
75 
81 
86  void pruneBurstTick() override;
87 
88  AddrRangeList getAddrRanges() override;
89 
90  public:
91  HBMCtrl(const HBMCtrlParams &p);
92 
93  void pruneRowBurstTick();
94  void pruneColBurstTick();
95 
109  Tick verifySingleCmd(Tick cmd_tick, Tick max_cmds_per_burst,
110  bool row_cmd) override;
111 
127  Tick verifyMultiCmd(Tick cmd_tick, Tick max_cmds_per_burst,
128  Tick max_multi_cmd_split = 0) override;
129 
136 
145  bool readQueueFullPC0(unsigned int pkt_count) const;
146  bool readQueueFullPC1(unsigned int pkt_count) const;
147  bool readQueueFull(unsigned int pkt_count) const;
148 
157  bool writeQueueFullPC0(unsigned int pkt_count) const;
158  bool writeQueueFullPC1(unsigned int pkt_count) const;
159 
165  uint64_t readQueueSizePC0 = 0;
166  uint64_t readQueueSizePC1 = 0;
167  uint64_t writeQueueSizePC0 = 0;
168  uint64_t writeQueueSizePC1 = 0;
169 
175 
181  std::unordered_multiset<Tick> rowBurstTicks;
182 
188  std::unordered_multiset<Tick> colBurstTicks;
189 
197 
203 
204  public:
205 
212  {
213  return respondEventPC1.scheduled();
214  }
215 
221  bool requestEventScheduled(uint8_t pseudo_channel) const override
222  {
223  if (pseudo_channel == 0) {
224  return MemCtrl::requestEventScheduled(pseudo_channel);
225  } else {
226  assert(pseudo_channel == 1);
227  return nextReqEventPC1.scheduled();
228  }
229  }
230 
238  void restartScheduler(Tick tick, uint8_t pseudo_channel) override
239  {
240  if (pseudo_channel == 0) {
242  } else {
244  }
245  }
246 
247 
248  virtual void init() override;
249  virtual void startup() override;
250  virtual void drainResume() override;
251 
252 
253  protected:
254  Tick recvAtomic(PacketPtr pkt) override;
255  Tick recvAtomicBackdoor(PacketPtr pkt, MemBackdoorPtr &backdoor) override;
256  void recvFunctional(PacketPtr pkt) override;
257  bool recvTimingReq(PacketPtr pkt) override;
258 
259 };
260 
261 } // namespace memory
262 } // namespace gem5
263 
264 #endif //__HBM_CTRL_HH__
gem5::memory::HBMCtrl::recvTimingReq
bool recvTimingReq(PacketPtr pkt) override
Definition: hbm_ctrl.cc:214
gem5::memory::HBMCtrl::pc1Int
DRAMInterface * pc1Int
Definition: hbm_ctrl.hh:196
memory
Definition: mem.h:38
gem5::memory::HBMCtrl::getAddrRanges
AddrRangeList getAddrRanges() override
Definition: hbm_ctrl.cc:492
gem5::memory::HBMCtrl::HBMCtrl
HBMCtrl(const HBMCtrlParams &p)
Definition: hbm_ctrl.cc:46
gem5::memory::MemCtrl::restartScheduler
virtual void restartScheduler(Tick tick, uint8_t pseudo_channel=0)
restart the controller This can be used by interfaces to restart the scheduler after maintainence com...
Definition: mem_ctrl.hh:748
gem5::memory::MemCtrl
The memory controller is a single-channel memory controller capturing the most important timing const...
Definition: mem_ctrl.hh:246
gem5::memory::HBMCtrl::verifySingleCmd
Tick verifySingleCmd(Tick cmd_tick, Tick max_cmds_per_burst, bool row_cmd) override
Check for command bus contention for single cycle command.
Definition: hbm_ctrl.cc:367
gem5::memory::MemCtrl::requestEventScheduled
virtual bool requestEventScheduled(uint8_t pseudo_channel=0) const
Is there a read/write burst Event scheduled?
Definition: mem_ctrl.hh:733
gem5::memory::HBMCtrl::colBurstTicks
std::unordered_multiset< Tick > colBurstTicks
This is used to ensure that the column command bandwidth does not exceed the allowable media constrai...
Definition: hbm_ctrl.hh:188
gem5::memory::HBMCtrl::recvFunctional
void recvFunctional(PacketPtr pkt) override
Definition: hbm_ctrl.cc:123
gem5::memory::HBMCtrl::nextReqEventPC1
EventFunctionWrapper nextReqEventPC1
NextReq and Respond events for second pseudo channel.
Definition: hbm_ctrl.hh:134
gem5::memory::HBMCtrl::readQueueSizePC1
uint64_t readQueueSizePC1
Definition: hbm_ctrl.hh:166
gem5::memory::DRAMInterface
Interface to DRAM devices with media specific parameters, statistics, and functions.
Definition: dram_interface.hh:65
gem5::memory::HBMCtrl::pruneColBurstTick
void pruneColBurstTick()
Definition: hbm_ctrl.cc:347
gem5::memory::qos::MemCtrl::schedule
uint8_t schedule(RequestorID id, uint64_t data)
Definition: mem_ctrl.cc:218
gem5::memory::HBMCtrl::recvAtomic
Tick recvAtomic(PacketPtr pkt) override
Definition: hbm_ctrl.cc:107
gem5::VegaISA::p
Bitfield< 54 > p
Definition: pagetable.hh:70
gem5::Packet
A Packet is used to encapsulate a transfer between two objects in the memory system (e....
Definition: packet.hh:291
gem5::Tick
uint64_t Tick
Tick count type.
Definition: types.hh:58
gem5::memory::HBMCtrl::pc0Int
DRAMInterface * pc0Int
Pointers to interfaces of the two pseudo channels pc0Int is same as MemCtrl::dram (it will be pointin...
Definition: hbm_ctrl.hh:195
gem5::memory::HBMCtrl::respondEventPC1
EventFunctionWrapper respondEventPC1
Definition: hbm_ctrl.hh:135
gem5::memory::HBMCtrl
HBM2 is divided into two pseudo channels which have independent data buses but share a command bus (s...
Definition: hbm_ctrl.hh:64
gem5::memory::HBMCtrl::verifyMultiCmd
Tick verifyMultiCmd(Tick cmd_tick, Tick max_cmds_per_burst, Tick max_multi_cmd_split=0) override
Check for command bus contention for multi-cycle (2 currently) command.
Definition: hbm_ctrl.cc:404
gem5::memory::HBMCtrl::writeQueueFullPC1
bool writeQueueFullPC1(unsigned int pkt_count) const
Definition: hbm_ctrl.cc:165
gem5::memory::HBMCtrl::respondEventPC1Scheduled
bool respondEventPC1Scheduled() const
Is there a respondEvent for pseudo channel 1 scheduled?
Definition: hbm_ctrl.hh:211
mem_ctrl.hh
gem5::memory::HBMCtrl::startup
virtual void startup() override
startup() is the final initialization call before simulation.
Definition: hbm_ctrl.cc:92
gem5::memory::MemCtrl::respQueue
std::deque< MemPacket * > respQueue
Response queue where read packets wait after we're done working with them, but it's not time to send ...
Definition: mem_ctrl.hh:489
gem5::memory::HBMCtrl::respQueuePC1
std::deque< MemPacket * > respQueuePC1
Response queue for pkts sent to second pseudo channel The first pseudo channel uses MemCtrl::respQueu...
Definition: hbm_ctrl.hh:174
gem5::memory::HBMCtrl::drainResume
virtual void drainResume() override
Resume execution after a successful drain.
Definition: hbm_ctrl.cc:469
gem5::MemBackdoor
Definition: backdoor.hh:41
gem5::memory::HBMCtrl::partitionedQ
bool partitionedQ
This indicates if the R/W queues will be partitioned among pseudo channels.
Definition: hbm_ctrl.hh:202
gem5::memory::HBMCtrl::pruneBurstTick
void pruneBurstTick() override
Remove commands that have already issued from rowBurstTicks and colBurstTicks.
Definition: hbm_ctrl.cc:360
gem5::EventFunctionWrapper
Definition: eventq.hh:1115
gem5::memory::HBMCtrl::readQueueFullPC0
bool readQueueFullPC0(unsigned int pkt_count) const
Check if the read queue partition of both pseudo channels has room for more entries.
Definition: hbm_ctrl.cc:176
gem5::memory::HBMCtrl::readQueueFullPC1
bool readQueueFullPC1(unsigned int pkt_count) const
Definition: hbm_ctrl.cc:189
std::deque
STL deque class.
Definition: stl.hh:44
gem5::Clocked::tick
Tick tick
Definition: clocked_object.hh:68
gem5::memory::HBMCtrl::respQEmpty
bool respQEmpty() override
Definition: hbm_ctrl.hh:69
gem5::memory::HBMCtrl::readQueueFull
bool readQueueFull(unsigned int pkt_count) const
Definition: hbm_ctrl.cc:202
gem5::memory::HBMCtrl::recvAtomicBackdoor
Tick recvAtomicBackdoor(PacketPtr pkt, MemBackdoorPtr &backdoor) override
Definition: hbm_ctrl.cc:137
std::list< AddrRange >
gem5::memory::HBMCtrl::readQueueSizePC0
uint64_t readQueueSizePC0
Following counters are used to keep track of the entries in read/write queue for each pseudo channel ...
Definition: hbm_ctrl.hh:165
gem5::memory::HBMCtrl::writeQueueSizePC0
uint64_t writeQueueSizePC0
Definition: hbm_ctrl.hh:167
gem5::memory::HBMCtrl::retryWrReqPC1
bool retryWrReqPC1
Definition: hbm_ctrl.hh:80
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: gpu_translation_state.hh:37
gem5::memory::HBMCtrl::rowBurstTicks
std::unordered_multiset< Tick > rowBurstTicks
Holds count of row commands issued in burst window starting at defined Tick.
Definition: hbm_ctrl.hh:181
gem5::memory::HBMCtrl::requestEventScheduled
bool requestEventScheduled(uint8_t pseudo_channel) const override
Is there a read/write burst Event scheduled?
Definition: hbm_ctrl.hh:221
gem5::memory::HBMCtrl::init
virtual void init() override
init() is called after all C++ SimObjects have been created and all ports are connected.
Definition: hbm_ctrl.cc:86
gem5::memory::HBMCtrl::restartScheduler
void restartScheduler(Tick tick, uint8_t pseudo_channel) override
restart the controller scheduler
Definition: hbm_ctrl.hh:238
gem5::memory::HBMCtrl::writeQueueSizePC1
uint64_t writeQueueSizePC1
Definition: hbm_ctrl.hh:168
gem5::memory::HBMCtrl::writeQueueFullPC0
bool writeQueueFullPC0(unsigned int pkt_count) const
Check if the write queue partition of both pseudo channels has room for more entries.
Definition: hbm_ctrl.cc:154
gem5::Event::scheduled
bool scheduled() const
Determine if the current event is scheduled.
Definition: eventq.hh:465
gem5::memory::HBMCtrl::pruneRowBurstTick
void pruneRowBurstTick()
Definition: hbm_ctrl.cc:334
gem5::memory::HBMCtrl::retryRdReqPC1
bool retryRdReqPC1
Remember if we have to retry a request for second pseudo channel.
Definition: hbm_ctrl.hh:79

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