gem5  v22.0.0.2
hbm_ctrl.cc
Go to the documentation of this file.
1 /*
2  * Copyright (c) 2022 The Regents of the University of California
3  * All rights reserved.
4  *
5  * Redistribution and use in source and binary forms, with or without
6  * modification, are permitted provided that the following conditions are
7  * met: redistributions of source code must retain the above copyright
8  * notice, this list of conditions and the following disclaimer;
9  * redistributions in binary form must reproduce the above copyright
10  * notice, this list of conditions and the following disclaimer in the
11  * documentation and/or other materials provided with the distribution;
12  * neither the name of the copyright holders nor the names of its
13  * contributors may be used to endorse or promote products derived from
14  * this software without specific prior written permission.
15  *
16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27  */
28 
29 #include "mem/hbm_ctrl.hh"
30 
31 #include "base/trace.hh"
32 #include "debug/DRAM.hh"
33 #include "debug/Drain.hh"
34 #include "debug/MemCtrl.hh"
35 #include "debug/QOS.hh"
36 #include "mem/dram_interface.hh"
37 #include "mem/mem_interface.hh"
38 #include "sim/system.hh"
39 
40 namespace gem5
41 {
42 
43 namespace memory
44 {
45 
46 HBMCtrl::HBMCtrl(const HBMCtrlParams &p) :
47  MemCtrl(p),
48  retryRdReqPC1(false), retryWrReqPC1(false),
49  nextReqEventPC1([this] {processNextReqEvent(pc1Int, respQueuePC1,
51  name()),
52  respondEventPC1([this] {processRespondEvent(pc1Int, respQueuePC1,
53  respondEventPC1, retryRdReqPC1); }, name()),
54  pc1Int(p.dram_2),
55  partitionedQ(p.partitioned_q)
56 {
57  DPRINTF(MemCtrl, "Setting up HBM controller\n");
58 
59  pc0Int = dynamic_cast<DRAMInterface*>(dram);
60 
61  assert(dynamic_cast<DRAMInterface*>(p.dram_2) != nullptr);
62 
63  readBufferSize = pc0Int->readBufferSize + pc1Int->readBufferSize;
64  writeBufferSize = pc0Int->writeBufferSize + pc1Int->writeBufferSize;
65 
66  fatal_if(!pc0Int, "Memory controller must have pc0 interface");
67  fatal_if(!pc1Int, "Memory controller must have pc1 interface");
68 
69  pc0Int->setCtrl(this, commandWindow, 0);
70  pc1Int->setCtrl(this, commandWindow, 1);
71 
72  if (partitionedQ) {
73  writeHighThreshold = (writeBufferSize * (p.write_high_thresh_perc/2)
74  / 100.0);
75  writeLowThreshold = (writeBufferSize * (p.write_low_thresh_perc/2)
76  / 100.0);
77  } else {
78  writeHighThreshold = (writeBufferSize * p.write_high_thresh_perc
79  / 100.0);
80  writeLowThreshold = (writeBufferSize * p.write_low_thresh_perc
81  / 100.0);
82  }
83 }
84 
85 void
87 {
88  MemCtrl::init();
89 }
90 
91 void
93 {
95 
97  if (isTimingMode) {
98  // shift the bus busy time sufficiently far ahead that we never
99  // have to worry about negative values when computing the time for
100  // the next request, this will add an insignificant bubble at the
101  // start of simulation
103  }
104 }
105 
106 Tick
108 {
109  Tick latency = 0;
110 
111  if (pc0Int->getAddrRange().contains(pkt->getAddr())) {
112  latency = MemCtrl::recvAtomicLogic(pkt, pc0Int);
113  } else if (pc1Int->getAddrRange().contains(pkt->getAddr())) {
114  latency = MemCtrl::recvAtomicLogic(pkt, pc1Int);
115  } else {
116  panic("Can't handle address range for packet %s\n", pkt->print());
117  }
118 
119  return latency;
120 }
121 
122 void
124 {
125  bool found = MemCtrl::recvFunctionalLogic(pkt, pc0Int);
126 
127  if (!found) {
128  found = MemCtrl::recvFunctionalLogic(pkt, pc1Int);
129  }
130 
131  if (!found) {
132  panic("Can't handle address range for packet %s\n", pkt->print());
133  }
134 }
135 
136 Tick
138 {
139  Tick latency = recvAtomic(pkt);
140 
141  if (pc0Int && pc0Int->getAddrRange().contains(pkt->getAddr())) {
142  pc0Int->getBackdoor(backdoor);
143  } else if (pc1Int && pc1Int->getAddrRange().contains(pkt->getAddr())) {
144  pc1Int->getBackdoor(backdoor);
145  }
146  else {
147  panic("Can't handle address range for packet %s\n",
148  pkt->print());
149  }
150  return latency;
151 }
152 
153 bool
154 HBMCtrl::writeQueueFullPC0(unsigned int neededEntries) const
155 {
157  "Write queue limit %d, PC0 size %d, entries needed %d\n",
158  writeBufferSize, writeQueueSizePC0, neededEntries);
159 
160  unsigned int wrsize_new = (writeQueueSizePC0 + neededEntries);
161  return wrsize_new > (writeBufferSize/2);
162 }
163 
164 bool
165 HBMCtrl::writeQueueFullPC1(unsigned int neededEntries) const
166 {
168  "Write queue limit %d, PC1 size %d, entries needed %d\n",
169  writeBufferSize, writeQueueSizePC1, neededEntries);
170 
171  unsigned int wrsize_new = (writeQueueSizePC1 + neededEntries);
172  return wrsize_new > (writeBufferSize/2);
173 }
174 
175 bool
176 HBMCtrl::readQueueFullPC0(unsigned int neededEntries) const
177 {
179  "Read queue limit %d, PC0 size %d, entries needed %d\n",
181  neededEntries);
182 
183  unsigned int rdsize_new = readQueueSizePC0 + respQueue.size()
184  + neededEntries;
185  return rdsize_new > (readBufferSize/2);
186 }
187 
188 bool
189 HBMCtrl::readQueueFullPC1(unsigned int neededEntries) const
190 {
192  "Read queue limit %d, PC1 size %d, entries needed %d\n",
194  neededEntries);
195 
196  unsigned int rdsize_new = readQueueSizePC1 + respQueuePC1.size()
197  + neededEntries;
198  return rdsize_new > (readBufferSize/2);
199 }
200 
201 bool
202 HBMCtrl::readQueueFull(unsigned int neededEntries) const
203 {
205  "HBMCtrl: Read queue limit %d, entries needed %d\n",
206  readBufferSize, neededEntries);
207 
208  unsigned int rdsize_new = totalReadQueueSize + respQueue.size() +
209  respQueuePC1.size() + neededEntries;
210  return rdsize_new > readBufferSize;
211 }
212 
213 bool
215 {
216  // This is where we enter from the outside world
217  DPRINTF(MemCtrl, "recvTimingReq: request %s addr %#x size %d\n",
218  pkt->cmdString(), pkt->getAddr(), pkt->getSize());
219 
220  panic_if(pkt->cacheResponding(), "Should not see packets where cache "
221  "is responding");
222 
223  panic_if(!(pkt->isRead() || pkt->isWrite()),
224  "Should only see read and writes at memory controller\n");
225 
226  // Calc avg gap between requests
227  if (prevArrival != 0) {
229  }
230  prevArrival = curTick();
231 
232  // What type of media does this packet access?
233  bool is_pc0;
234 
235  // TODO: make the interleaving bit across pseudo channels a parameter
236  if (bits(pkt->getAddr(), 6) == 0) {
237  is_pc0 = true;
238  } else {
239  is_pc0 = false;
240  }
241 
242  // Find out how many memory packets a pkt translates to
243  // If the burst size is equal or larger than the pkt size, then a pkt
244  // translates to only one memory packet. Otherwise, a pkt translates to
245  // multiple memory packets
246  unsigned size = pkt->getSize();
247  uint32_t burst_size = pc0Int->bytesPerBurst();
248  unsigned offset = pkt->getAddr() & (burst_size - 1);
249  unsigned int pkt_count = divCeil(offset + size, burst_size);
250 
251  // run the QoS scheduler and assign a QoS priority value to the packet
252  qosSchedule({&readQueue, &writeQueue}, burst_size, pkt);
253 
254  // check local buffers and do not accept if full
255  if (pkt->isWrite()) {
256  if (is_pc0) {
257  if (partitionedQ ? writeQueueFullPC0(pkt_count) :
258  writeQueueFull(pkt_count))
259  {
260  DPRINTF(MemCtrl, "Write queue full, not accepting\n");
261  // remember that we have to retry this port
262  MemCtrl::retryWrReq = true;
263  stats.numWrRetry++;
264  return false;
265  } else {
266  addToWriteQueue(pkt, pkt_count, pc0Int);
267  stats.writeReqs++;
268  stats.bytesWrittenSys += size;
269  }
270  } else {
271  if (partitionedQ ? writeQueueFullPC1(pkt_count) :
272  writeQueueFull(pkt_count))
273  {
274  DPRINTF(MemCtrl, "Write queue full, not accepting\n");
275  // remember that we have to retry this port
276  retryWrReqPC1 = true;
277  stats.numWrRetry++;
278  return false;
279  } else {
280  addToWriteQueue(pkt, pkt_count, pc1Int);
281  stats.writeReqs++;
282  stats.bytesWrittenSys += size;
283  }
284  }
285  } else {
286 
287  assert(pkt->isRead());
288  assert(size != 0);
289 
290  if (is_pc0) {
291  if (partitionedQ ? readQueueFullPC0(pkt_count) :
292  HBMCtrl::readQueueFull(pkt_count)) {
293  DPRINTF(MemCtrl, "Read queue full, not accepting\n");
294  // remember that we have to retry this port
295  retryRdReqPC1 = true;
296  stats.numRdRetry++;
297  return false;
298  } else {
299  if (!addToReadQueue(pkt, pkt_count, pc0Int)) {
300  if (!nextReqEvent.scheduled()) {
301  DPRINTF(MemCtrl, "Request scheduled immediately\n");
303  }
304  }
305 
306  stats.readReqs++;
307  stats.bytesReadSys += size;
308  }
309  } else {
310  if (partitionedQ ? readQueueFullPC1(pkt_count) :
311  HBMCtrl::readQueueFull(pkt_count)) {
312  DPRINTF(MemCtrl, "Read queue full, not accepting\n");
313  // remember that we have to retry this port
314  retryRdReqPC1 = true;
315  stats.numRdRetry++;
316  return false;
317  } else {
318  if (!addToReadQueue(pkt, pkt_count, pc1Int)) {
319  if (!nextReqEventPC1.scheduled()) {
320  DPRINTF(MemCtrl, "Request scheduled immediately\n");
322  }
323  }
324  stats.readReqs++;
325  stats.bytesReadSys += size;
326  }
327  }
328  }
329 
330  return true;
331 }
332 
333 void
335 {
336  auto it = rowBurstTicks.begin();
337  while (it != rowBurstTicks.end()) {
338  auto current_it = it++;
339  if (MemCtrl::getBurstWindow(curTick()) > *current_it) {
340  DPRINTF(MemCtrl, "Removing burstTick for %d\n", *current_it);
341  rowBurstTicks.erase(current_it);
342  }
343  }
344 }
345 
346 void
348 {
349  auto it = colBurstTicks.begin();
350  while (it != colBurstTicks.end()) {
351  auto current_it = it++;
352  if (MemCtrl::getBurstWindow(curTick()) > *current_it) {
353  DPRINTF(MemCtrl, "Removing burstTick for %d\n", *current_it);
354  colBurstTicks.erase(current_it);
355  }
356  }
357 }
358 
359 void
361 {
364 }
365 
366 Tick
367 HBMCtrl::verifySingleCmd(Tick cmd_tick, Tick max_cmds_per_burst, bool row_cmd)
368 {
369  // start with assumption that there is no contention on command bus
370  Tick cmd_at = cmd_tick;
371 
372  // get tick aligned to burst window
373  Tick burst_tick = MemCtrl::getBurstWindow(cmd_tick);
374 
375  // verify that we have command bandwidth to issue the command
376  // if not, iterate over next window(s) until slot found
377 
378  if (row_cmd) {
379  while (rowBurstTicks.count(burst_tick) >= max_cmds_per_burst) {
380  DPRINTF(MemCtrl, "Contention found on row command bus at %d\n",
381  burst_tick);
382  burst_tick += commandWindow;
383  cmd_at = burst_tick;
384  }
385  DPRINTF(MemCtrl, "Now can send a row cmd_at %d\n",
386  cmd_at);
387  rowBurstTicks.insert(burst_tick);
388 
389  } else {
390  while (colBurstTicks.count(burst_tick) >= max_cmds_per_burst) {
391  DPRINTF(MemCtrl, "Contention found on col command bus at %d\n",
392  burst_tick);
393  burst_tick += commandWindow;
394  cmd_at = burst_tick;
395  }
396  DPRINTF(MemCtrl, "Now can send a col cmd_at %d\n",
397  cmd_at);
398  colBurstTicks.insert(burst_tick);
399  }
400  return cmd_at;
401 }
402 
403 Tick
404 HBMCtrl::verifyMultiCmd(Tick cmd_tick, Tick max_cmds_per_burst,
405  Tick max_multi_cmd_split)
406 {
407 
408  // start with assumption that there is no contention on command bus
409  Tick cmd_at = cmd_tick;
410 
411  // get tick aligned to burst window
412  Tick burst_tick = MemCtrl::getBurstWindow(cmd_tick);
413 
414  // Command timing requirements are from 2nd command
415  // Start with assumption that 2nd command will issue at cmd_at and
416  // find prior slot for 1st command to issue
417  // Given a maximum latency of max_multi_cmd_split between the commands,
418  // find the burst at the maximum latency prior to cmd_at
419  Tick burst_offset = 0;
420  Tick first_cmd_offset = cmd_tick % commandWindow;
421  while (max_multi_cmd_split > (first_cmd_offset + burst_offset)) {
422  burst_offset += commandWindow;
423  }
424  // get the earliest burst aligned address for first command
425  // ensure that the time does not go negative
426  Tick first_cmd_tick = burst_tick - std::min(burst_offset, burst_tick);
427 
428  // Can required commands issue?
429  bool first_can_issue = false;
430  bool second_can_issue = false;
431  // verify that we have command bandwidth to issue the command(s)
432  while (!first_can_issue || !second_can_issue) {
433  bool same_burst = (burst_tick == first_cmd_tick);
434  auto first_cmd_count = rowBurstTicks.count(first_cmd_tick);
435  auto second_cmd_count = same_burst ?
436  first_cmd_count + 1 : rowBurstTicks.count(burst_tick);
437 
438  first_can_issue = first_cmd_count < max_cmds_per_burst;
439  second_can_issue = second_cmd_count < max_cmds_per_burst;
440 
441  if (!second_can_issue) {
442  DPRINTF(MemCtrl, "Contention (cmd2) found on command bus at %d\n",
443  burst_tick);
444  burst_tick += commandWindow;
445  cmd_at = burst_tick;
446  }
447 
448  // Verify max_multi_cmd_split isn't violated when command 2 is shifted
449  // If commands initially were issued in same burst, they are
450  // now in consecutive bursts and can still issue B2B
451  bool gap_violated = !same_burst &&
452  ((burst_tick - first_cmd_tick) > max_multi_cmd_split);
453 
454  if (!first_can_issue || (!second_can_issue && gap_violated)) {
455  DPRINTF(MemCtrl, "Contention (cmd1) found on command bus at %d\n",
456  first_cmd_tick);
457  first_cmd_tick += commandWindow;
458  }
459  }
460 
461  // Add command to burstTicks
462  rowBurstTicks.insert(burst_tick);
463  rowBurstTicks.insert(first_cmd_tick);
464 
465  return cmd_at;
466 }
467 
468 void
470 {
471 
473 
474  if (!isTimingMode && system()->isTimingMode()) {
475  // if we switched to timing mode, kick things into action,
476  // and behave as if we restored from a checkpoint
477  startup();
478  pc1Int->startup();
479  } else if (isTimingMode && !system()->isTimingMode()) {
480  // if we switch from timing mode, stop the refresh events to
481  // not cause issues with KVM
482  if (pc1Int) {
483  pc1Int->drainRanks();
484  }
485  }
486 
487  // update the mode
489 }
490 
493 {
494  AddrRangeList ranges;
495  ranges.push_back(pc0Int->getAddrRange());
496  ranges.push_back(pc1Int->getAddrRange());
497  return ranges;
498 }
499 
500 } // namespace memory
501 } // namespace gem5
gem5::memory::HBMCtrl::recvTimingReq
bool recvTimingReq(PacketPtr pkt) override
Definition: hbm_ctrl.cc:214
gem5::curTick
Tick curTick()
The universal simulation clock.
Definition: cur_tick.hh:46
gem5::Packet::cmdString
const std::string & cmdString() const
Return the string name of the cmd field (for debugging and tracing).
Definition: packet.hh:585
gem5::memory::qos::MemCtrl::totalReadQueueSize
uint64_t totalReadQueueSize
Total read request packets queue length in #packets.
Definition: mem_ctrl.hh:131
gem5::memory::MemCtrl::addToReadQueue
bool addToReadQueue(PacketPtr pkt, unsigned int pkt_count, MemInterface *mem_intr)
When a new read comes in, first check if the write q has a pending request to the same address....
Definition: mem_ctrl.cc:187
gem5::memory::HBMCtrl::pc1Int
DRAMInterface * pc1Int
Definition: hbm_ctrl.hh:196
gem5::memory::MemCtrl::nextReqEvent
EventFunctionWrapper nextReqEvent
Definition: mem_ctrl.hh:304
system.hh
memory
Definition: mem.h:38
gem5::memory::HBMCtrl::getAddrRanges
AddrRangeList getAddrRanges() override
Definition: hbm_ctrl.cc:492
gem5::memory::AbstractMemory::getAddrRange
AddrRange getAddrRange() const
Get the address range.
Definition: abstract_mem.cc:249
gem5::AddrRange::contains
bool contains(const Addr &a) const
Determine if the range contains an address.
Definition: addr_range.hh:471
gem5::memory::HBMCtrl::HBMCtrl
HBMCtrl(const HBMCtrlParams &p)
Definition: hbm_ctrl.cc:46
gem5::memory::MemCtrl
The memory controller is a single-channel memory controller capturing the most important timing const...
Definition: mem_ctrl.hh:246
gem5::memory::HBMCtrl::verifySingleCmd
Tick verifySingleCmd(Tick cmd_tick, Tick max_cmds_per_burst, bool row_cmd) override
Check for command bus contention for single cycle command.
Definition: hbm_ctrl.cc:367
gem5::Packet::cacheResponding
bool cacheResponding() const
Definition: packet.hh:655
gem5::memory::HBMCtrl::colBurstTicks
std::unordered_multiset< Tick > colBurstTicks
This is used to ensure that the column command bandwidth does not exceed the allowable media constrai...
Definition: hbm_ctrl.hh:188
gem5::Packet::isWrite
bool isWrite() const
Definition: packet.hh:591
gem5::memory::DRAMInterface::drainRanks
void drainRanks() override
Iterate through dram ranks to exit self-refresh in order to drain.
Definition: dram_interface.cc:991
gem5::memory::MemCtrl::startup
virtual void startup() override
startup() is the final initialization call before simulation.
Definition: mem_ctrl.cc:108
gem5::memory::MemCtrl::prevArrival
Tick prevArrival
Definition: mem_ctrl.hh:551
gem5::memory::HBMCtrl::recvFunctional
void recvFunctional(PacketPtr pkt) override
Definition: hbm_ctrl.cc:123
gem5::memory::HBMCtrl::nextReqEventPC1
EventFunctionWrapper nextReqEventPC1
NextReq and Respond events for second pseudo channel.
Definition: hbm_ctrl.hh:134
gem5::memory::qos::MemCtrl::qosSchedule
uint8_t qosSchedule(std::initializer_list< Queues * > queues_ptr, uint64_t queue_entry_size, const PacketPtr pkt)
Assign priority to a packet by executing the configured QoS policy.
Definition: mem_ctrl.hh:496
gem5::memory::MemCtrl::readBufferSize
uint32_t readBufferSize
The following are basic design parameters of the memory controller, and are initialized based on para...
Definition: mem_ctrl.hh:511
gem5::memory::MemCtrl::CtrlStats::bytesReadSys
statistics::Scalar bytesReadSys
Definition: mem_ctrl.hh:591
gem5::memory::HBMCtrl::readQueueSizePC1
uint64_t readQueueSizePC1
Definition: hbm_ctrl.hh:166
gem5::memory::MemCtrl::writeQueue
std::vector< MemPacketQueue > writeQueue
Definition: mem_ctrl.hh:470
gem5::memory::HBMCtrl::pruneColBurstTick
void pruneColBurstTick()
Definition: hbm_ctrl.cc:347
gem5::memory::qos::MemCtrl::schedule
uint8_t schedule(RequestorID id, uint64_t data)
Definition: mem_ctrl.cc:218
mem_interface.hh
gem5::Packet::isRead
bool isRead() const
Definition: packet.hh:590
gem5::memory::HBMCtrl::recvAtomic
Tick recvAtomic(PacketPtr pkt) override
Definition: hbm_ctrl.cc:107
gem5::memory::MemCtrl::CtrlStats::numWrRetry
statistics::Scalar numWrRetry
Definition: mem_ctrl.hh:582
gem5::VegaISA::p
Bitfield< 54 > p
Definition: pagetable.hh:70
gem5::Packet::print
void print(std::ostream &o, int verbosity=0, const std::string &prefix="") const
Definition: packet.cc:364
DPRINTF
#define DPRINTF(x,...)
Definition: trace.hh:186
gem5::Packet
A Packet is used to encapsulate a transfer between two objects in the memory system (e....
Definition: packet.hh:291
gem5::Tick
uint64_t Tick
Tick count type.
Definition: types.hh:58
gem5::memory::DRAMInterface::commandOffset
Tick commandOffset() const override
Definition: dram_interface.hh:697
gem5::memory::HBMCtrl::pc0Int
DRAMInterface * pc0Int
Pointers to interfaces of the two pseudo channels pc0Int is same as MemCtrl::dram (it will be pointin...
Definition: hbm_ctrl.hh:195
gem5::memory::MemCtrl::stats
CtrlStats stats
Definition: mem_ctrl.hh:621
gem5::memory::HBMCtrl::respondEventPC1
EventFunctionWrapper respondEventPC1
Definition: hbm_ctrl.hh:135
gem5::memory::MemCtrl::writeBufferSize
uint32_t writeBufferSize
Definition: mem_ctrl.hh:512
gem5::memory::qos::MemCtrl::system
System * system() const
read the system pointer
Definition: mem_ctrl.hh:371
gem5::memory::MemCtrl::init
virtual void init() override
init() is called after all C++ SimObjects have been created and all ports are connected.
Definition: mem_ctrl.cc:98
gem5::memory::HBMCtrl::verifyMultiCmd
Tick verifyMultiCmd(Tick cmd_tick, Tick max_cmds_per_burst, Tick max_multi_cmd_split=0) override
Check for command bus contention for multi-cycle (2 currently) command.
Definition: hbm_ctrl.cc:404
gem5::memory::HBMCtrl::writeQueueFullPC1
bool writeQueueFullPC1(unsigned int pkt_count) const
Definition: hbm_ctrl.cc:165
gem5::memory::MemCtrl::recvFunctionalLogic
bool recvFunctionalLogic(PacketPtr pkt, MemInterface *mem_intr)
Definition: mem_ctrl.cc:1365
gem5::memory::MemCtrl::retryWrReq
bool retryWrReq
Definition: mem_ctrl.hh:291
gem5::ArmISA::offset
Bitfield< 23, 0 > offset
Definition: types.hh:144
gem5::memory::MemCtrl::CtrlStats::bytesWrittenSys
statistics::Scalar bytesWrittenSys
Definition: mem_ctrl.hh:592
gem5::bits
constexpr T bits(T val, unsigned first, unsigned last)
Extract the bitfield from position 'first' to 'last' (inclusive) from 'val' and right justify it.
Definition: bitfield.hh:76
gem5::memory::HBMCtrl::startup
virtual void startup() override
startup() is the final initialization call before simulation.
Definition: hbm_ctrl.cc:92
gem5::memory::MemCtrl::CtrlStats::writeReqs
statistics::Scalar writeReqs
Definition: mem_ctrl.hh:571
gem5::System::isTimingMode
bool isTimingMode() const
Is the system in timing mode?
Definition: system.hh:274
gem5::memory::MemCtrl::isTimingMode
bool isTimingMode
Remember if the memory system is in timing mode.
Definition: mem_ctrl.hh:285
gem5::memory::MemCtrl::CtrlStats::numRdRetry
statistics::Scalar numRdRetry
Definition: mem_ctrl.hh:581
gem5::memory::MemCtrl::respQueue
std::deque< MemPacket * > respQueue
Response queue where read packets wait after we're done working with them, but it's not time to send ...
Definition: mem_ctrl.hh:489
gem5::memory::HBMCtrl::respQueuePC1
std::deque< MemPacket * > respQueuePC1
Response queue for pkts sent to second pseudo channel The first pseudo channel uses MemCtrl::respQueu...
Definition: hbm_ctrl.hh:174
gem5::memory::HBMCtrl::drainResume
virtual void drainResume() override
Resume execution after a successful drain.
Definition: hbm_ctrl.cc:469
name
const std::string & name()
Definition: trace.cc:49
gem5::MemBackdoor
Definition: backdoor.hh:41
gem5::memory::MemCtrl::CtrlStats::totGap
statistics::Scalar totGap
Definition: mem_ctrl.hh:597
gem5::memory::MemInterface::nextBurstAt
Tick nextBurstAt
Till when the controller must wait before issuing next RD/WR burst?
Definition: mem_interface.hh:189
gem5::memory::AbstractMemory::getBackdoor
void getBackdoor(MemBackdoorPtr &bd_ptr)
Definition: abstract_mem.hh:238
gem5::memory::MemCtrl::readQueue
std::vector< MemPacketQueue > readQueue
The controller's main read and write queues, with support for QoS reordering.
Definition: mem_ctrl.hh:469
gem5::divCeil
static constexpr T divCeil(const T &a, const U &b)
Definition: intmath.hh:110
gem5::memory::HBMCtrl::partitionedQ
bool partitionedQ
This indicates if the R/W queues will be partitioned among pseudo channels.
Definition: hbm_ctrl.hh:202
gem5::memory::HBMCtrl::pruneBurstTick
void pruneBurstTick() override
Remove commands that have already issued from rowBurstTicks and colBurstTicks.
Definition: hbm_ctrl.cc:360
panic_if
#define panic_if(cond,...)
Conditional panic macro that checks the supplied condition and only panics if the condition is true a...
Definition: logging.hh:204
gem5::memory::MemCtrl::CtrlStats::readReqs
statistics::Scalar readReqs
Definition: mem_ctrl.hh:570
gem5::memory::MemCtrl::recvAtomicLogic
Tick recvAtomicLogic(PacketPtr pkt, MemInterface *mem_intr)
Definition: mem_ctrl.cc:134
gem5::memory::HBMCtrl::readQueueFullPC0
bool readQueueFullPC0(unsigned int pkt_count) const
Check if the read queue partition of both pseudo channels has room for more entries.
Definition: hbm_ctrl.cc:176
dram_interface.hh
gem5::memory::HBMCtrl::readQueueFullPC1
bool readQueueFullPC1(unsigned int pkt_count) const
Definition: hbm_ctrl.cc:189
gem5::memory::MemCtrl::writeQueueFull
bool writeQueueFull(unsigned int pkt_count) const
Check if the write queue has room for more entries.
Definition: mem_ctrl.cc:176
gem5::memory::HBMCtrl::readQueueFull
bool readQueueFull(unsigned int pkt_count) const
Definition: hbm_ctrl.cc:202
gem5::memory::MemCtrl::processNextReqEvent
virtual void processNextReqEvent(MemInterface *mem_intr, MemPacketQueue &resp_queue, EventFunctionWrapper &resp_event, EventFunctionWrapper &next_req_event, bool &retry_wr_req)
Bunch of things requires to setup "events" in gem5 When event "respondEvent" occurs for example,...
Definition: mem_ctrl.cc:872
gem5::memory::MemCtrl::getBurstWindow
Tick getBurstWindow(Tick cmd_tick)
Calculate burst window aligned tick.
Definition: mem_ctrl.cc:666
gem5::memory::MemCtrl::addToWriteQueue
void addToWriteQueue(PacketPtr pkt, unsigned int pkt_count, MemInterface *mem_intr)
Decode the incoming pkt, create a mem_pkt and push to the back of the write queue.
Definition: mem_ctrl.cc:300
hbm_ctrl.hh
gem5::memory::HBMCtrl::recvAtomicBackdoor
Tick recvAtomicBackdoor(PacketPtr pkt, MemBackdoorPtr &backdoor) override
Definition: hbm_ctrl.cc:137
trace.hh
gem5::memory::MemInterface::bytesPerBurst
uint32_t bytesPerBurst() const
Definition: mem_interface.hh:256
gem5::memory::MemCtrl::drainResume
virtual void drainResume() override
Resume execution after a successful drain.
Definition: mem_ctrl.cc:1422
std::list< AddrRange >
gem5::memory::HBMCtrl::readQueueSizePC0
uint64_t readQueueSizePC0
Following counters are used to keep track of the entries in read/write queue for each pseudo channel ...
Definition: hbm_ctrl.hh:165
gem5::Packet::getAddr
Addr getAddr() const
Definition: packet.hh:790
gem5::memory::MemCtrl::commandWindow
const Tick commandWindow
Length of a command window, used to check command bandwidth.
Definition: mem_ctrl.hh:544
gem5::memory::HBMCtrl::writeQueueSizePC0
uint64_t writeQueueSizePC0
Definition: hbm_ctrl.hh:167
gem5::memory::HBMCtrl::retryWrReqPC1
bool retryWrReqPC1
Definition: hbm_ctrl.hh:80
fatal_if
#define fatal_if(cond,...)
Conditional fatal macro that checks the supplied condition and only causes a fatal error if the condi...
Definition: logging.hh:226
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: gpu_translation_state.hh:37
gem5::memory::HBMCtrl::rowBurstTicks
std::unordered_multiset< Tick > rowBurstTicks
Holds count of row commands issued in burst window starting at defined Tick.
Definition: hbm_ctrl.hh:181
gem5::memory::HBMCtrl::init
virtual void init() override
init() is called after all C++ SimObjects have been created and all ports are connected.
Definition: hbm_ctrl.cc:86
gem5::memory::HBMCtrl::writeQueueSizePC1
uint64_t writeQueueSizePC1
Definition: hbm_ctrl.hh:168
gem5::memory::HBMCtrl::writeQueueFullPC0
bool writeQueueFullPC0(unsigned int pkt_count) const
Check if the write queue partition of both pseudo channels has room for more entries.
Definition: hbm_ctrl.cc:154
gem5::Packet::getSize
unsigned getSize() const
Definition: packet.hh:800
gem5::Event::scheduled
bool scheduled() const
Determine if the current event is scheduled.
Definition: eventq.hh:465
gem5::memory::DRAMInterface::startup
void startup() override
Iterate through dram ranks and instantiate per rank startup routine.
Definition: dram_interface.cc:784
gem5::memory::HBMCtrl::pruneRowBurstTick
void pruneRowBurstTick()
Definition: hbm_ctrl.cc:334
gem5::memory::HBMCtrl::retryRdReqPC1
bool retryRdReqPC1
Remember if we have to retry a request for second pseudo channel.
Definition: hbm_ctrl.hh:79
panic
#define panic(...)
This implements a cprintf based panic() function.
Definition: logging.hh:178

Generated on Thu Jul 28 2022 13:32:34 for gem5 by doxygen 1.8.17