gem5  v22.0.0.1
mem_ctrl.hh
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40 
46 #ifndef __MEM_CTRL_HH__
47 #define __MEM_CTRL_HH__
48 
49 #include <deque>
50 #include <string>
51 #include <unordered_set>
52 #include <utility>
53 #include <vector>
54 
55 #include "base/callback.hh"
56 #include "base/statistics.hh"
57 #include "enums/MemSched.hh"
58 #include "mem/qos/mem_ctrl.hh"
59 #include "mem/qport.hh"
60 #include "params/MemCtrl.hh"
61 #include "sim/eventq.hh"
62 
63 namespace gem5
64 {
65 
66 namespace memory
67 {
68 
69 class MemInterface;
70 class DRAMInterface;
71 class NVMInterface;
72 
80 {
81  public:
82 
84  const unsigned int burstCount;
85 
87  unsigned int burstsServiced;
88 
89  BurstHelper(unsigned int _burstCount)
90  : burstCount(_burstCount), burstsServiced(0)
91  { }
92 };
93 
98 class MemPacket
99 {
100  public:
101 
104 
107 
109  const PacketPtr pkt;
110 
113 
114  const bool read;
115 
117  const bool dram;
118 
120  const uint8_t pseudoChannel;
121 
123  const uint8_t rank;
124  const uint8_t bank;
125  const uint32_t row;
126 
132  const uint16_t bankId;
133 
141 
146  unsigned int size;
147 
153 
157  uint8_t _qosValue;
158 
163  inline void qosValue(const uint8_t qv) { _qosValue = qv; }
164 
169  inline uint8_t qosValue() const { return _qosValue; }
170 
175  inline RequestorID requestorId() const { return _requestorId; }
176 
181  inline unsigned int getSize() const { return size; }
182 
187  inline Addr getAddr() const { return addr; }
188 
193  inline bool isRead() const { return read; }
194 
199  inline bool isWrite() const { return !read; }
200 
204  inline bool isDram() const { return dram; }
205 
206  MemPacket(PacketPtr _pkt, bool is_read, bool is_dram, uint8_t _channel,
207  uint8_t _rank, uint8_t _bank, uint32_t _row, uint16_t bank_id,
208  Addr _addr, unsigned int _size)
209  : entryTime(curTick()), readyTime(curTick()), pkt(_pkt),
211  read(is_read), dram(is_dram), pseudoChannel(_channel), rank(_rank),
212  bank(_bank), row(_row), bankId(bank_id), addr(_addr), size(_size),
213  burstHelper(NULL), _qosValue(_pkt->qosValue())
214  { }
215 
216 };
217 
218 // The memory packets are store in a multiple dequeue structure,
219 // based on their QoS priority
221 
222 
246 class MemCtrl : public qos::MemCtrl
247 {
248  protected:
249 
250  // For now, make use of a queued response port to avoid dealing with
251  // flow control for the responses being sent back
253  {
254 
257 
258  public:
259 
260  MemoryPort(const std::string& name, MemCtrl& _ctrl);
261 
262  protected:
263 
264  Tick recvAtomic(PacketPtr pkt) override;
266  PacketPtr pkt, MemBackdoorPtr &backdoor) override;
267 
268  void recvFunctional(PacketPtr pkt) override;
269 
270  bool recvTimingReq(PacketPtr) override;
271 
272  AddrRangeList getAddrRanges() const override;
273 
274  };
275 
281 
286 
292 
299  virtual void processNextReqEvent(MemInterface* mem_intr,
300  MemPacketQueue& resp_queue,
301  EventFunctionWrapper& resp_event,
302  EventFunctionWrapper& next_req_event,
303  bool& retry_wr_req);
305 
306  virtual void processRespondEvent(MemInterface* mem_intr,
307  MemPacketQueue& queue,
308  EventFunctionWrapper& resp_event,
309  bool& retry_rd_req);
311 
318  bool readQueueFull(unsigned int pkt_count) const;
319 
326  bool writeQueueFull(unsigned int pkt_count) const;
327 
343  bool addToReadQueue(PacketPtr pkt, unsigned int pkt_count,
344  MemInterface* mem_intr);
345 
357  void addToWriteQueue(PacketPtr pkt, unsigned int pkt_count,
358  MemInterface* mem_intr);
359 
369  virtual Tick doBurstAccess(MemPacket* mem_pkt, MemInterface* mem_intr);
370 
381  virtual void accessAndRespond(PacketPtr pkt, Tick static_latency,
382  MemInterface* mem_intr);
383 
389  virtual bool packetReady(MemPacket* pkt, MemInterface* mem_intr);
390 
396  virtual Tick minReadToWriteDataGap();
397 
403  virtual Tick minWriteToReadDataGap();
404 
417  virtual MemPacketQueue::iterator chooseNext(MemPacketQueue& queue,
418  Tick extra_col_delay, MemInterface* mem_intr);
419 
429  chooseNextFRFCFS(MemPacketQueue& queue, Tick extra_col_delay,
430  MemInterface* mem_intr);
431 
438  Tick getBurstWindow(Tick cmd_tick);
439 
443  void printQs() const;
444 
453  virtual Addr burstAlign(Addr addr, MemInterface* mem_intr) const;
454 
462  virtual bool pktSizeCheck(MemPacket* mem_pkt,
463  MemInterface* mem_intr) const;
464 
471 
479  std::unordered_set<Addr> isInWriteQueue;
480 
490 
496  std::unordered_multiset<Tick> burstTicks;
497 
502 
503  virtual AddrRangeList getAddrRanges();
504 
511  uint32_t readBufferSize;
512  uint32_t writeBufferSize;
515  const uint32_t minWritesPerSwitch;
516  const uint32_t minReadsPerSwitch;
517  uint32_t writesThisTime;
518  uint32_t readsThisTime;
519 
524  enums::MemSched memSchedPolicy;
525 
532 
539 
545 
550 
552 
560 
561  struct CtrlStats : public statistics::Group
562  {
564 
565  void regStats() override;
566 
568 
569  // All statistics that the model needs to capture
577  // Average queue lengths
580 
589 
593  // Average bandwidth
596 
599 
600  // per-requestor bytes read and written to memory
603 
604  // per-requestor bytes read and written to memory rate
607 
608  // per-requestor read and write serviced memory accesses
611 
612  // per-requestor read and write total memory access latency
615 
616  // per-requestor raed and write average memory access latency
619  };
620 
622 
627  std::unique_ptr<Packet> pendingDelete;
628 
636  {
637  return (is_read ? readQueue : writeQueue);
638  };
639 
640  virtual bool respQEmpty()
641  {
642  return respQueue.empty();
643  }
644 
651  virtual bool memBusy(MemInterface* mem_intr);
652 
658  virtual void nonDetermReads(MemInterface* mem_intr);
659 
668  virtual bool nvmWriteBlock(MemInterface* mem_intr);
669 
673  virtual void pruneBurstTick();
674 
675  public:
676 
677  MemCtrl(const MemCtrlParams &p);
678 
684  virtual bool allIntfDrained() const;
685 
686  DrainState drain() override;
687 
701  virtual Tick verifySingleCmd(Tick cmd_tick, Tick max_cmds_per_burst,
702  bool row_cmd);
703 
718  virtual Tick verifyMultiCmd(Tick cmd_tick, Tick max_cmds_per_burst,
719  Tick max_multi_cmd_split = 0);
720 
726  bool respondEventScheduled() const { return respondEvent.scheduled(); }
727 
733  virtual bool requestEventScheduled(uint8_t pseudo_channel = 0) const
734  {
735  assert(pseudo_channel == 0);
736  return nextReqEvent.scheduled();
737  }
738 
748  virtual void restartScheduler(Tick tick, uint8_t pseudo_channel = 0)
749  {
750  assert(pseudo_channel == 0);
752  }
753 
760  bool inReadBusState(bool next_state) const;
761 
768  bool inWriteBusState(bool next_state) const;
769 
770  Port &getPort(const std::string &if_name,
771  PortID idx=InvalidPortID) override;
772 
773  virtual void init() override;
774  virtual void startup() override;
775  virtual void drainResume() override;
776 
777  protected:
778 
779  virtual Tick recvAtomic(PacketPtr pkt);
780  virtual Tick recvAtomicBackdoor(PacketPtr pkt, MemBackdoorPtr &backdoor);
781  virtual void recvFunctional(PacketPtr pkt);
782  virtual bool recvTimingReq(PacketPtr pkt);
783 
784  bool recvFunctionalLogic(PacketPtr pkt, MemInterface* mem_intr);
785  Tick recvAtomicLogic(PacketPtr pkt, MemInterface* mem_intr);
786 
787 };
788 
789 } // namespace memory
790 } // namespace gem5
791 
792 #endif //__MEM_CTRL_HH__
gem5::statistics::Scalar
This is a simple scalar statistic, like a counter.
Definition: statistics.hh:1930
gem5::curTick
Tick curTick()
The universal simulation clock.
Definition: cur_tick.hh:46
gem5::memory::MemCtrl::CtrlStats::requestorReadRate
statistics::Formula requestorReadRate
Definition: mem_ctrl.hh:605
gem5::PortID
int16_t PortID
Port index/ID type, and a symbolic name for an invalid port id.
Definition: types.hh:245
gem5::memory::MemCtrl::addToReadQueue
bool addToReadQueue(PacketPtr pkt, unsigned int pkt_count, MemInterface *mem_intr)
When a new read comes in, first check if the write q has a pending request to the same address....
Definition: mem_ctrl.cc:187
gem5::memory::MemCtrl::backendLatency
const Tick backendLatency
Pipeline latency of the backend and PHY.
Definition: mem_ctrl.hh:538
gem5::memory::MemCtrl::writeLowThreshold
uint32_t writeLowThreshold
Definition: mem_ctrl.hh:514
gem5::memory::MemCtrl::CtrlStats::bytesReadWrQ
statistics::Scalar bytesReadWrQ
Definition: mem_ctrl.hh:590
gem5::Port::name
const std::string name() const
Return port name (for DPRINTF).
Definition: port.hh:111
gem5::memory::MemCtrl::nextReqEvent
EventFunctionWrapper nextReqEvent
Definition: mem_ctrl.hh:304
gem5::memory::MemCtrl::verifySingleCmd
virtual Tick verifySingleCmd(Tick cmd_tick, Tick max_cmds_per_burst, bool row_cmd)
Check for command bus contention for single cycle command.
Definition: mem_ctrl.cc:674
gem5::memory::MemCtrl::MemoryPort::recvTimingReq
bool recvTimingReq(PacketPtr) override
Receive a timing request from the peer.
Definition: mem_ctrl.cc:1488
gem5::memory::MemPacket::burstHelper
BurstHelper * burstHelper
A pointer to the BurstHelper if this MemPacket is a split packet If not a split packet (common case),...
Definition: mem_ctrl.hh:152
gem5::RespPacketQueue
Definition: packet_queue.hh:300
gem5::memory::MemPacket::readyTime
Tick readyTime
When will request leave the controller.
Definition: mem_ctrl.hh:106
gem5::memory::MemPacket::size
unsigned int size
The size of this dram packet in bytes It is always equal or smaller than the burst size.
Definition: mem_ctrl.hh:146
gem5::memory::MemPacket::isWrite
bool isWrite() const
Return true if its a write packet (interface compatibility with Packet)
Definition: mem_ctrl.hh:199
gem5::memory::MemCtrl::readsThisTime
uint32_t readsThisTime
Definition: mem_ctrl.hh:518
gem5::memory::MemCtrl::isInWriteQueue
std::unordered_set< Addr > isInWriteQueue
To avoid iterating over the write queue to check for overlapping transactions, maintain a set of burs...
Definition: mem_ctrl.hh:479
memory
Definition: mem.h:38
gem5::memory::MemCtrl::recvAtomicBackdoor
virtual Tick recvAtomicBackdoor(PacketPtr pkt, MemBackdoorPtr &backdoor)
Definition: mem_ctrl.cc:156
gem5::memory::MemCtrl::CtrlStats
Definition: mem_ctrl.hh:561
gem5::memory::MemCtrl::CtrlStats::requestorWriteAccesses
statistics::Vector requestorWriteAccesses
Definition: mem_ctrl.hh:610
gem5::memory::MemCtrl::MemoryPort::MemoryPort
MemoryPort(const std::string &name, MemCtrl &_ctrl)
Definition: mem_ctrl.cc:1448
gem5::memory::MemCtrl::MemoryPort
Definition: mem_ctrl.hh:252
gem5::memory::MemCtrl::CtrlStats::requestorReadTotalLat
statistics::Vector requestorReadTotalLat
Definition: mem_ctrl.hh:613
gem5::memory::MemPacket::pkt
const PacketPtr pkt
This comes from the outside world.
Definition: mem_ctrl.hh:109
gem5::memory::MemCtrl::burstAlign
virtual Addr burstAlign(Addr addr, MemInterface *mem_intr) const
Burst-align an address.
Definition: mem_ctrl.cc:1151
gem5::memory::MemCtrl::restartScheduler
virtual void restartScheduler(Tick tick, uint8_t pseudo_channel=0)
restart the controller This can be used by interfaces to restart the scheduler after maintainence com...
Definition: mem_ctrl.hh:748
gem5::memory::MemCtrl
The memory controller is a single-channel memory controller capturing the most important timing const...
Definition: mem_ctrl.hh:246
gem5::memory::MemCtrl::requestEventScheduled
virtual bool requestEventScheduled(uint8_t pseudo_channel=0) const
Is there a read/write burst Event scheduled?
Definition: mem_ctrl.hh:733
gem5::statistics::Average
A stat that calculates the per tick average of a value.
Definition: statistics.hh:1958
gem5::memory::MemCtrl::writeHighThreshold
uint32_t writeHighThreshold
Definition: mem_ctrl.hh:513
gem5::statistics::Vector
A vector of scalar stats.
Definition: statistics.hh:2006
gem5::statistics::Formula
A formula for statistics that is calculated when printed.
Definition: statistics.hh:2539
std::vector
STL vector class.
Definition: stl.hh:37
gem5::memory::MemCtrl::respondEvent
EventFunctionWrapper respondEvent
Definition: mem_ctrl.hh:310
gem5::memory::MemCtrl::startup
virtual void startup() override
startup() is the final initialization call before simulation.
Definition: mem_ctrl.cc:108
gem5::memory::MemCtrl::CtrlStats::requestorWriteTotalLat
statistics::Vector requestorWriteTotalLat
Definition: mem_ctrl.hh:614
gem5::memory::MemCtrl::prevArrival
Tick prevArrival
Definition: mem_ctrl.hh:551
gem5::memory::MemCtrl::selQueue
std::vector< MemPacketQueue > & selQueue(bool is_read)
Select either the read or write queue.
Definition: mem_ctrl.hh:635
gem5::memory::MemCtrl::doBurstAccess
virtual Tick doBurstAccess(MemPacket *mem_pkt, MemInterface *mem_intr)
Actually do the burst based on media specific access function.
Definition: mem_ctrl.cc:787
gem5::memory::MemCtrl::memSchedPolicy
enums::MemSched memSchedPolicy
Memory controller configuration initialized based on parameter values.
Definition: mem_ctrl.hh:524
gem5::InvalidPortID
const PortID InvalidPortID
Definition: types.hh:246
gem5::memory::MemCtrl::CtrlStats::readPktSize
statistics::Vector readPktSize
Definition: mem_ctrl.hh:583
gem5::memory::MemCtrl::MemCtrl
MemCtrl(const MemCtrlParams &p)
Definition: mem_ctrl.cc:60
gem5::memory::MemCtrl::MemoryPort::queue
RespPacketQueue queue
Definition: mem_ctrl.hh:255
gem5::memory::MemCtrl::minReadsPerSwitch
const uint32_t minReadsPerSwitch
Definition: mem_ctrl.hh:516
gem5::memory::MemCtrl::CtrlStats::avgGap
statistics::Formula avgGap
Definition: mem_ctrl.hh:598
gem5::memory::MemCtrl::readBufferSize
uint32_t readBufferSize
The following are basic design parameters of the memory controller, and are initialized based on para...
Definition: mem_ctrl.hh:511
gem5::memory::MemCtrl::CtrlStats::bytesReadSys
statistics::Scalar bytesReadSys
Definition: mem_ctrl.hh:591
gem5::memory::MemCtrl::inReadBusState
bool inReadBusState(bool next_state) const
Check the current direction of the memory channel.
Definition: mem_ctrl.cc:761
gem5::memory::MemCtrl::retryRdReq
bool retryRdReq
Remember if we have to retry a request when available.
Definition: mem_ctrl.hh:290
gem5::memory::MemCtrl::CtrlStats::requestorReadAccesses
statistics::Vector requestorReadAccesses
Definition: mem_ctrl.hh:609
gem5::memory::MemPacket::entryTime
const Tick entryTime
When did request enter the controller.
Definition: mem_ctrl.hh:103
gem5::memory::MemCtrl::CtrlStats::avgWrQLen
statistics::Average avgWrQLen
Definition: mem_ctrl.hh:579
gem5::memory::MemCtrl::recvAtomic
virtual Tick recvAtomic(PacketPtr pkt)
Definition: mem_ctrl.cc:123
gem5::memory::MemCtrl::CtrlStats::writePktSize
statistics::Vector writePktSize
Definition: mem_ctrl.hh:584
gem5::statistics::Histogram
A simple histogram stat.
Definition: statistics.hh:2126
gem5::memory::MemCtrl::writeQueue
std::vector< MemPacketQueue > writeQueue
Definition: mem_ctrl.hh:470
gem5::memory::MemCtrl::respondEventScheduled
bool respondEventScheduled() const
Is there a respondEvent scheduled?
Definition: mem_ctrl.hh:726
gem5::DrainState
DrainState
Object drain/handover states.
Definition: drain.hh:74
gem5::memory::MemCtrl::inWriteBusState
bool inWriteBusState(bool next_state) const
Check the current direction of the memory channel.
Definition: mem_ctrl.cc:774
gem5::memory::MemCtrl::MemoryPort::ctrl
MemCtrl & ctrl
Definition: mem_ctrl.hh:256
gem5::memory::qos::MemCtrl::schedule
uint8_t schedule(RequestorID id, uint64_t data)
Definition: mem_ctrl.cc:218
gem5::memory::MemPacket::addr
Addr addr
The starting address of the packet.
Definition: mem_ctrl.hh:140
gem5::memory::MemCtrl::processRespondEvent
virtual void processRespondEvent(MemInterface *mem_intr, MemPacketQueue &queue, EventFunctionWrapper &resp_event, bool &retry_rd_req)
Definition: mem_ctrl.cc:482
gem5::memory::MemCtrl::CtrlStats::neitherReadNorWriteReqs
statistics::Scalar neitherReadNorWriteReqs
Definition: mem_ctrl.hh:576
gem5::memory::MemCtrl::minWriteToReadDataGap
virtual Tick minWriteToReadDataGap()
Calculate the minimum delay used when scheduling a write-to-read transision.
Definition: mem_ctrl.cc:1145
gem5::memory::MemCtrl::port
MemoryPort port
Our incoming port, for a multi-ported controller add a crossbar in front of it.
Definition: mem_ctrl.hh:280
gem5::memory::MemCtrl::CtrlStats::CtrlStats
CtrlStats(MemCtrl &ctrl)
Definition: mem_ctrl.cc:1162
gem5::memory::MemCtrl::nextBurstAt
Tick nextBurstAt
Till when must we wait before issuing next RD/WR burst?
Definition: mem_ctrl.hh:549
gem5::memory::MemInterface
General interface to memory device Includes functions and parameters shared across media types.
Definition: mem_interface.hh:74
gem5::memory::MemCtrl::CtrlStats::requestorReadBytes
statistics::Vector requestorReadBytes
Definition: mem_ctrl.hh:601
gem5::memory::MemCtrl::CtrlStats::numWrRetry
statistics::Scalar numWrRetry
Definition: mem_ctrl.hh:582
gem5::VegaISA::p
Bitfield< 54 > p
Definition: pagetable.hh:70
gem5::memory::MemPacket::row
const uint32_t row
Definition: mem_ctrl.hh:125
gem5::QueuedResponsePort
A queued port is a port that has an infinite queue for outgoing packets and thus decouples the module...
Definition: qport.hh:61
gem5::Packet
A Packet is used to encapsulate a transfer between two objects in the memory system (e....
Definition: packet.hh:291
gem5::memory::MemCtrl::CtrlStats::requestorReadAvgLat
statistics::Formula requestorReadAvgLat
Definition: mem_ctrl.hh:617
gem5::memory::MemCtrl::readQueueFull
bool readQueueFull(unsigned int pkt_count) const
Check if the read queue has room for more entries.
Definition: mem_ctrl.cc:164
statistics.hh
gem5::Tick
uint64_t Tick
Tick count type.
Definition: types.hh:58
gem5::memory::MemPacket::isDram
bool isDram() const
Return true if its a DRAM access.
Definition: mem_ctrl.hh:204
gem5::memory::MemCtrl::recvFunctional
virtual void recvFunctional(PacketPtr pkt)
Definition: mem_ctrl.cc:1356
gem5::memory::MemCtrl::packetReady
virtual bool packetReady(MemPacket *pkt, MemInterface *mem_intr)
Determine if there is a packet that can issue.
Definition: mem_ctrl.cc:1133
gem5::memory::MemCtrl::recvTimingReq
virtual bool recvTimingReq(PacketPtr pkt)
Definition: mem_ctrl.cc:401
gem5::memory::MemPacket
A memory packet stores packets along with the timestamp of when the packet entered the queue,...
Definition: mem_ctrl.hh:98
gem5::memory::MemCtrl::stats
CtrlStats stats
Definition: mem_ctrl.hh:621
gem5::memory::MemCtrl::drain
DrainState drain() override
Draining is the process of clearing out the states of SimObjects.These are the SimObjects that are pa...
Definition: mem_ctrl.cc:1396
gem5::memory::MemCtrl::getAddrRanges
virtual AddrRangeList getAddrRanges()
Definition: mem_ctrl.cc:1440
gem5::memory::MemCtrl::writeBufferSize
uint32_t writeBufferSize
Definition: mem_ctrl.hh:512
gem5::memory::MemCtrl::init
virtual void init() override
init() is called after all C++ SimObjects have been created and all ports are connected.
Definition: mem_ctrl.cc:98
gem5::memory::MemPacket::pseudoChannel
const uint8_t pseudoChannel
pseudo channel num
Definition: mem_ctrl.hh:120
gem5::memory::MemCtrl::recvFunctionalLogic
bool recvFunctionalLogic(PacketPtr pkt, MemInterface *mem_intr)
Definition: mem_ctrl.cc:1365
gem5::memory::MemPacket::qosValue
void qosValue(const uint8_t qv)
Set the packet QoS value (interface compatibility with Packet)
Definition: mem_ctrl.hh:163
gem5::memory::MemCtrl::pruneBurstTick
virtual void pruneBurstTick()
Remove commands that have already issued from burstTicks.
Definition: mem_ctrl.cc:653
gem5::memory::MemCtrl::pendingDelete
std::unique_ptr< Packet > pendingDelete
Upstream caches need this packet until true is returned, so hold it for deletion until a subsequent c...
Definition: mem_ctrl.hh:627
gem5::memory::MemCtrl::retryWrReq
bool retryWrReq
Definition: mem_ctrl.hh:291
gem5::memory::MemPacket::_qosValue
uint8_t _qosValue
QoS value of the encapsulated packet read at queuing time.
Definition: mem_ctrl.hh:157
gem5::memory::MemPacket::MemPacket
MemPacket(PacketPtr _pkt, bool is_read, bool is_dram, uint8_t _channel, uint8_t _rank, uint8_t _bank, uint32_t _row, uint16_t bank_id, Addr _addr, unsigned int _size)
Definition: mem_ctrl.hh:206
gem5::memory::MemCtrl::allIntfDrained
virtual bool allIntfDrained() const
Ensure that all interfaced have drained commands.
Definition: mem_ctrl.cc:1387
gem5::memory::MemCtrl::CtrlStats::rdQLenPdf
statistics::Vector rdQLenPdf
Definition: mem_ctrl.hh:585
gem5::memory::MemCtrl::CtrlStats::bytesWrittenSys
statistics::Scalar bytesWrittenSys
Definition: mem_ctrl.hh:592
gem5::memory::MemCtrl::MemoryPort::recvFunctional
void recvFunctional(PacketPtr pkt) override
Receive a functional request packet from the peer.
Definition: mem_ctrl.cc:1460
gem5::memory::MemCtrl::CtrlStats::writeReqs
statistics::Scalar writeReqs
Definition: mem_ctrl.hh:571
gem5::memory::BurstHelper::burstsServiced
unsigned int burstsServiced
Number of bursts serviced so far for a system packet.
Definition: mem_ctrl.hh:87
gem5::memory::MemCtrl::CtrlStats::regStats
void regStats() override
Callback to set stat parameters.
Definition: mem_ctrl.cc:1260
gem5::memory::MemPacket::requestorId
RequestorID requestorId() const
Get the packet RequestorID (interface compatibility with Packet)
Definition: mem_ctrl.hh:175
gem5::memory::MemCtrl::dram
MemInterface * dram
Definition: mem_ctrl.hh:501
gem5::memory::MemCtrl::isTimingMode
bool isTimingMode
Remember if the memory system is in timing mode.
Definition: mem_ctrl.hh:285
std::pair
STL pair class.
Definition: stl.hh:58
gem5::memory::MemPacket::qosValue
uint8_t qosValue() const
Get the packet QoS value (interface compatibility with Packet)
Definition: mem_ctrl.hh:169
gem5::memory::MemCtrl::CtrlStats::numRdRetry
statistics::Scalar numRdRetry
Definition: mem_ctrl.hh:581
gem5::memory::MemCtrl::CtrlStats::avgRdBWSys
statistics::Formula avgRdBWSys
Definition: mem_ctrl.hh:594
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::memory::MemCtrl::respQueue
std::deque< MemPacket * > respQueue
Response queue where read packets wait after we're done working with them, but it's not time to send ...
Definition: mem_ctrl.hh:489
gem5::memory::MemCtrl::frontendLatency
const Tick frontendLatency
Pipeline latency of the controller frontend.
Definition: mem_ctrl.hh:531
gem5::memory::BurstHelper::BurstHelper
BurstHelper(unsigned int _burstCount)
Definition: mem_ctrl.hh:89
gem5::memory::MemCtrl::CtrlStats::wrQLenPdf
statistics::Vector wrQLenPdf
Definition: mem_ctrl.hh:586
gem5::memory::MemCtrl::MemoryPort::recvAtomicBackdoor
Tick recvAtomicBackdoor(PacketPtr pkt, MemBackdoorPtr &backdoor) override
Receive an atomic request packet from the peer, and optionally provide a backdoor to the data being a...
Definition: mem_ctrl.cc:1481
gem5::memory::MemCtrl::pktSizeCheck
virtual bool pktSizeCheck(MemPacket *mem_pkt, MemInterface *mem_intr) const
Check if mem pkt's size is sane.
Definition: mem_ctrl.cc:1157
gem5::MemBackdoor
Definition: backdoor.hh:41
gem5::memory::MemCtrl::CtrlStats::servicedByWrQ
statistics::Scalar servicedByWrQ
Definition: mem_ctrl.hh:574
gem5::memory::MemCtrl::CtrlStats::totGap
statistics::Scalar totGap
Definition: mem_ctrl.hh:597
gem5::memory::MemCtrl::chooseNextFRFCFS
virtual std::pair< MemPacketQueue::iterator, Tick > chooseNextFRFCFS(MemPacketQueue &queue, Tick extra_col_delay, MemInterface *mem_intr)
For FR-FCFS policy reorder the read/write queue depending on row buffer hits and earliest bursts avai...
Definition: mem_ctrl.cc:592
gem5::memory::MemCtrl::readQueue
std::vector< MemPacketQueue > readQueue
The controller's main read and write queues, with support for QoS reordering.
Definition: mem_ctrl.hh:469
gem5::memory::MemCtrl::CtrlStats::readBursts
statistics::Scalar readBursts
Definition: mem_ctrl.hh:572
gem5::memory::MemPacket::getAddr
Addr getAddr() const
Get the packet address (interface compatibility with Packet)
Definition: mem_ctrl.hh:187
gem5::memory::MemCtrl::burstTicks
std::unordered_multiset< Tick > burstTicks
Holds count of commands issued in burst window starting at defined Tick.
Definition: mem_ctrl.hh:496
gem5::memory::MemCtrl::respQEmpty
virtual bool respQEmpty()
Definition: mem_ctrl.hh:640
gem5::EventFunctionWrapper
Definition: eventq.hh:1115
gem5::memory::MemCtrl::CtrlStats::requestorWriteRate
statistics::Formula requestorWriteRate
Definition: mem_ctrl.hh:606
mem_ctrl.hh
gem5::memory::MemPacket::bank
const uint8_t bank
Definition: mem_ctrl.hh:124
gem5::memory::MemCtrl::CtrlStats::readReqs
statistics::Scalar readReqs
Definition: mem_ctrl.hh:570
gem5::memory::MemCtrl::minReadToWriteDataGap
virtual Tick minReadToWriteDataGap()
Calculate the minimum delay used when scheduling a read-to-write transision.
Definition: mem_ctrl.cc:1139
gem5::memory::MemCtrl::accessAndRespond
virtual void accessAndRespond(PacketPtr pkt, Tick static_latency, MemInterface *mem_intr)
When a packet reaches its "readyTime" in the response Q, use the "access()" method in AbstractMemory ...
Definition: mem_ctrl.cc:613
gem5::memory::MemPacket::_requestorId
const RequestorID _requestorId
RequestorID associated with the packet.
Definition: mem_ctrl.hh:112
gem5::memory::MemCtrl::MemoryPort::getAddrRanges
AddrRangeList getAddrRanges() const override
Get a list of the non-overlapping address ranges the owner is responsible for.
Definition: mem_ctrl.cc:1454
gem5::memory::MemCtrl::verifyMultiCmd
virtual Tick verifyMultiCmd(Tick cmd_tick, Tick max_cmds_per_burst, Tick max_multi_cmd_split=0)
Check for command bus contention for multi-cycle (2 currently) command.
Definition: mem_ctrl.cc:697
gem5::memory::MemCtrl::getPort
Port & getPort(const std::string &if_name, PortID idx=InvalidPortID) override
Get a port with a given name and index.
Definition: mem_ctrl.cc:1377
gem5::memory::MemCtrl::memBusy
virtual bool memBusy(MemInterface *mem_intr)
Checks if the memory interface is already busy.
Definition: mem_ctrl.cc:829
gem5::memory::MemCtrl::MemoryPort::recvAtomic
Tick recvAtomic(PacketPtr pkt) override
Receive an atomic request packet from the peer.
Definition: mem_ctrl.cc:1475
gem5::Port
Ports are used to interface objects to each other.
Definition: port.hh:61
qport.hh
gem5::memory::MemPacket::rank
const uint8_t rank
Will be populated by address decoder.
Definition: mem_ctrl.hh:123
gem5::memory::MemCtrl::recvAtomicLogic
Tick recvAtomicLogic(PacketPtr pkt, MemInterface *mem_intr)
Definition: mem_ctrl.cc:134
gem5::memory::MemPacket::dram
const bool dram
Does this packet access DRAM?
Definition: mem_ctrl.hh:117
std::deque
STL deque class.
Definition: stl.hh:44
gem5::memory::MemCtrl::writeQueueFull
bool writeQueueFull(unsigned int pkt_count) const
Check if the write queue has room for more entries.
Definition: mem_ctrl.cc:176
gem5::memory::MemPacket::getSize
unsigned int getSize() const
Get the packet size (interface compatibility with Packet)
Definition: mem_ctrl.hh:181
gem5::Clocked::tick
Tick tick
Definition: clocked_object.hh:68
gem5::memory::MemCtrl::CtrlStats::writeBursts
statistics::Scalar writeBursts
Definition: mem_ctrl.hh:573
gem5::memory::MemCtrl::CtrlStats::rdPerTurnAround
statistics::Histogram rdPerTurnAround
Definition: mem_ctrl.hh:587
gem5::memory::MemCtrl::CtrlStats::requestorWriteAvgLat
statistics::Formula requestorWriteAvgLat
Definition: mem_ctrl.hh:618
gem5::memory::BurstHelper
A burst helper helps organize and manage a packet that is larger than the memory burst size.
Definition: mem_ctrl.hh:79
gem5::statistics::Group
Statistics container.
Definition: group.hh:93
gem5::memory::MemCtrl::processNextReqEvent
virtual void processNextReqEvent(MemInterface *mem_intr, MemPacketQueue &resp_queue, EventFunctionWrapper &resp_event, EventFunctionWrapper &next_req_event, bool &retry_wr_req)
Bunch of things requires to setup "events" in gem5 When event "respondEvent" occurs for example,...
Definition: mem_ctrl.cc:872
gem5::memory::MemCtrl::CtrlStats::ctrl
MemCtrl & ctrl
Definition: mem_ctrl.hh:567
gem5::memory::MemCtrl::getBurstWindow
Tick getBurstWindow(Tick cmd_tick)
Calculate burst window aligned tick.
Definition: mem_ctrl.cc:666
gem5::memory::MemCtrl::addToWriteQueue
void addToWriteQueue(PacketPtr pkt, unsigned int pkt_count, MemInterface *mem_intr)
Decode the incoming pkt, create a mem_pkt and push to the back of the write queue.
Definition: mem_ctrl.cc:300
gem5::memory::qos::MemCtrl
The qos::MemCtrl is a base class for Memory objects which support QoS - it provides access to a set o...
Definition: mem_ctrl.hh:80
gem5::RequestorID
uint16_t RequestorID
Definition: request.hh:95
gem5::memory::MemCtrl::CtrlStats::avgWrBWSys
statistics::Formula avgWrBWSys
Definition: mem_ctrl.hh:595
gem5::memory::MemPacketQueue
std::deque< MemPacket * > MemPacketQueue
Definition: mem_ctrl.hh:220
gem5::memory::MemCtrl::minWritesPerSwitch
const uint32_t minWritesPerSwitch
Definition: mem_ctrl.hh:515
gem5::memory::MemCtrl::drainResume
virtual void drainResume() override
Resume execution after a successful drain.
Definition: mem_ctrl.cc:1422
std::list< AddrRange >
gem5::memory::MemCtrl::commandWindow
const Tick commandWindow
Length of a command window, used to check command bandwidth.
Definition: mem_ctrl.hh:544
gem5::memory::MemCtrl::CtrlStats::mergedWrBursts
statistics::Scalar mergedWrBursts
Definition: mem_ctrl.hh:575
gem5::memory::MemCtrl::printQs
void printQs() const
Used for debugging to observe the contents of the queues.
Definition: mem_ctrl.cc:376
gem5::memory::MemCtrl::nextReqTime
Tick nextReqTime
The soonest you have to start thinking about the next request is the longest access time that can occ...
Definition: mem_ctrl.hh:559
gem5::memory::BurstHelper::burstCount
const unsigned int burstCount
Number of bursts requred for a system packet.
Definition: mem_ctrl.hh:84
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: gpu_translation_state.hh:37
gem5::memory::MemPacket::isRead
bool isRead() const
Return true if its a read packet (interface compatibility with Packet)
Definition: mem_ctrl.hh:193
gem5::memory::MemCtrl::chooseNext
virtual MemPacketQueue::iterator chooseNext(MemPacketQueue &queue, Tick extra_col_delay, MemInterface *mem_intr)
The memory schduler/arbiter - picks which request needs to go next, based on the specified policy suc...
Definition: mem_ctrl.cc:551
gem5::memory::MemCtrl::CtrlStats::avgRdQLen
statistics::Average avgRdQLen
Definition: mem_ctrl.hh:578
gem5::memory::MemCtrl::CtrlStats::wrPerTurnAround
statistics::Histogram wrPerTurnAround
Definition: mem_ctrl.hh:588
gem5::memory::MemCtrl::writesThisTime
uint32_t writesThisTime
Definition: mem_ctrl.hh:517
gem5::memory::MemCtrl::nonDetermReads
virtual void nonDetermReads(MemInterface *mem_intr)
Will access memory interface and select non-deterministic reads to issue.
Definition: mem_ctrl.cc:857
gem5::memory::MemPacket::bankId
const uint16_t bankId
Bank id is calculated considering banks in all the ranks eg: 2 ranks each with 8 banks,...
Definition: mem_ctrl.hh:132
callback.hh
gem5::memory::MemCtrl::CtrlStats::requestorWriteBytes
statistics::Vector requestorWriteBytes
Definition: mem_ctrl.hh:602
gem5::Event::scheduled
bool scheduled() const
Determine if the current event is scheduled.
Definition: eventq.hh:465
gem5::memory::MemPacket::read
const bool read
Definition: mem_ctrl.hh:114
gem5::X86ISA::addr
Bitfield< 3 > addr
Definition: types.hh:84
gem5::memory::MemCtrl::nvmWriteBlock
virtual bool nvmWriteBlock(MemInterface *mem_intr)
Will check if all writes are for nvm interface and nvm's write resp queue is full.
Definition: mem_ctrl.cc:850
eventq.hh

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