gem5  v21.1.0.2
mem_ctrl.hh
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40 
46 #ifndef __MEM_CTRL_HH__
47 #define __MEM_CTRL_HH__
48 
49 #include <deque>
50 #include <string>
51 #include <unordered_set>
52 #include <utility>
53 #include <vector>
54 
55 #include "base/callback.hh"
56 #include "base/statistics.hh"
57 #include "enums/MemSched.hh"
58 #include "mem/qos/mem_ctrl.hh"
59 #include "mem/qport.hh"
60 #include "params/MemCtrl.hh"
61 #include "sim/eventq.hh"
62 
63 namespace gem5
64 {
65 
66 namespace memory
67 {
68 
69 class DRAMInterface;
70 class NVMInterface;
71 
79 {
80  public:
81 
83  const unsigned int burstCount;
84 
86  unsigned int burstsServiced;
87 
88  BurstHelper(unsigned int _burstCount)
89  : burstCount(_burstCount), burstsServiced(0)
90  { }
91 };
92 
97 class MemPacket
98 {
99  public:
100 
103 
106 
108  const PacketPtr pkt;
109 
112 
113  const bool read;
114 
116  const bool dram;
117 
119  const uint8_t rank;
120  const uint8_t bank;
121  const uint32_t row;
122 
128  const uint16_t bankId;
129 
137 
142  unsigned int size;
143 
149 
153  uint8_t _qosValue;
154 
159  inline void qosValue(const uint8_t qv) { _qosValue = qv; }
160 
165  inline uint8_t qosValue() const { return _qosValue; }
166 
171  inline RequestorID requestorId() const { return _requestorId; }
172 
177  inline unsigned int getSize() const { return size; }
178 
183  inline Addr getAddr() const { return addr; }
184 
189  inline bool isRead() const { return read; }
190 
195  inline bool isWrite() const { return !read; }
196 
200  inline bool isDram() const { return dram; }
201 
202  MemPacket(PacketPtr _pkt, bool is_read, bool is_dram, uint8_t _rank,
203  uint8_t _bank, uint32_t _row, uint16_t bank_id, Addr _addr,
204  unsigned int _size)
205  : entryTime(curTick()), readyTime(curTick()), pkt(_pkt),
207  read(is_read), dram(is_dram), rank(_rank), bank(_bank), row(_row),
208  bankId(bank_id), addr(_addr), size(_size), burstHelper(NULL),
209  _qosValue(_pkt->qosValue())
210  { }
211 
212 };
213 
214 // The memory packets are store in a multiple dequeue structure,
215 // based on their QoS priority
217 
218 
242 class MemCtrl : public qos::MemCtrl
243 {
244  private:
245 
246  // For now, make use of a queued response port to avoid dealing with
247  // flow control for the responses being sent back
249  {
250 
253 
254  public:
255 
256  MemoryPort(const std::string& name, MemCtrl& _ctrl);
257 
258  protected:
259 
260  Tick recvAtomic(PacketPtr pkt) override;
262  PacketPtr pkt, MemBackdoorPtr &backdoor) override;
263 
264  void recvFunctional(PacketPtr pkt) override;
265 
266  bool recvTimingReq(PacketPtr) override;
267 
268  AddrRangeList getAddrRanges() const override;
269 
270  };
271 
277 
282 
288 
295  void processNextReqEvent();
297 
298  void processRespondEvent();
300 
307  bool readQueueFull(unsigned int pkt_count) const;
308 
315  bool writeQueueFull(unsigned int pkt_count) const;
316 
332  void addToReadQueue(PacketPtr pkt, unsigned int pkt_count, bool is_dram);
333 
346  void addToWriteQueue(PacketPtr pkt, unsigned int pkt_count, bool is_dram);
347 
354  void doBurstAccess(MemPacket* mem_pkt);
355 
365  void accessAndRespond(PacketPtr pkt, Tick static_latency);
366 
372  bool packetReady(MemPacket* pkt);
373 
380 
387 
399  MemPacketQueue::iterator chooseNext(MemPacketQueue& queue,
400  Tick extra_col_delay);
401 
410  MemPacketQueue::iterator chooseNextFRFCFS(MemPacketQueue& queue,
411  Tick extra_col_delay);
412 
419  Tick getBurstWindow(Tick cmd_tick);
420 
424  void printQs() const;
425 
434  Addr burstAlign(Addr addr, bool is_dram) const;
435 
442 
450  std::unordered_set<Addr> isInWriteQueue;
451 
461 
467  std::unordered_multiset<Tick> burstTicks;
468 
473 
478 
485  const uint32_t readBufferSize;
486  const uint32_t writeBufferSize;
487  const uint32_t writeHighThreshold;
488  const uint32_t writeLowThreshold;
489  const uint32_t minWritesPerSwitch;
490  uint32_t writesThisTime;
491  uint32_t readsThisTime;
492 
497  enums::MemSched memSchedPolicy;
498 
505 
512 
518 
523 
525 
533 
534  struct CtrlStats : public statistics::Group
535  {
537 
538  void regStats() override;
539 
541 
542  // All statistics that the model needs to capture
550  // Average queue lengths
553 
562 
566  // Average bandwidth
569 
572 
573  // per-requestor bytes read and written to memory
576 
577  // per-requestor bytes read and written to memory rate
580 
581  // per-requestor read and write serviced memory accesses
584 
585  // per-requestor read and write total memory access latency
588 
589  // per-requestor raed and write average memory access latency
592  };
593 
595 
600  std::unique_ptr<Packet> pendingDelete;
601 
609  {
610  return (is_read ? readQueue : writeQueue);
611  };
612 
616  void pruneBurstTick();
617 
618  public:
619 
620  MemCtrl(const MemCtrlParams &p);
621 
627  bool allIntfDrained() const;
628 
629  DrainState drain() override;
630 
644  Tick verifySingleCmd(Tick cmd_tick, Tick max_cmds_per_burst);
645 
660  Tick verifyMultiCmd(Tick cmd_tick, Tick max_cmds_per_burst,
661  Tick max_multi_cmd_split = 0);
662 
668  bool respondEventScheduled() const { return respondEvent.scheduled(); }
669 
675  bool requestEventScheduled() const { return nextReqEvent.scheduled(); }
676 
685 
692  bool inReadBusState(bool next_state) const;
693 
700  bool inWriteBusState(bool next_state) const;
701 
702  Port &getPort(const std::string &if_name,
703  PortID idx=InvalidPortID) override;
704 
705  virtual void init() override;
706  virtual void startup() override;
707  virtual void drainResume() override;
708 
709  protected:
710 
713  void recvFunctional(PacketPtr pkt);
714  bool recvTimingReq(PacketPtr pkt);
715 
716 };
717 
718 } // namespace memory
719 } // namespace gem5
720 
721 #endif //__MEM_CTRL_HH__
gem5::statistics::Scalar
This is a simple scalar statistic, like a counter.
Definition: statistics.hh:1927
gem5::memory::MemCtrl::readBufferSize
const uint32_t readBufferSize
The following are basic design parameters of the memory controller, and are initialized based on para...
Definition: mem_ctrl.hh:485
gem5::curTick
Tick curTick()
The universal simulation clock.
Definition: cur_tick.hh:46
gem5::memory::MemCtrl::CtrlStats::requestorReadRate
statistics::Formula requestorReadRate
Definition: mem_ctrl.hh:578
gem5::PortID
int16_t PortID
Port index/ID type, and a symbolic name for an invalid port id.
Definition: types.hh:252
gem5::memory::NVMInterface
Interface to NVM devices with media specific parameters, statistics, and functions.
Definition: mem_interface.hh:1028
gem5::memory::MemCtrl::backendLatency
const Tick backendLatency
Pipeline latency of the backend and PHY.
Definition: mem_ctrl.hh:511
gem5::memory::MemCtrl::dram
DRAMInterface *const dram
Create pointer to interface of the actual dram media when connected.
Definition: mem_ctrl.hh:472
gem5::memory::MemCtrl::CtrlStats::bytesReadWrQ
statistics::Scalar bytesReadWrQ
Definition: mem_ctrl.hh:563
gem5::Port::name
const std::string name() const
Return port name (for DPRINTF).
Definition: port.hh:111
gem5::memory::MemCtrl::nextReqEvent
EventFunctionWrapper nextReqEvent
Definition: mem_ctrl.hh:296
gem5::memory::MemCtrl::MemoryPort::recvTimingReq
bool recvTimingReq(PacketPtr) override
Receive a timing request from the peer.
Definition: mem_ctrl.cc:1514
gem5::memory::MemPacket::burstHelper
BurstHelper * burstHelper
A pointer to the BurstHelper if this MemPacket is a split packet If not a split packet (common case),...
Definition: mem_ctrl.hh:148
gem5::RespPacketQueue
Definition: packet_queue.hh:300
gem5::memory::MemPacket::readyTime
Tick readyTime
When will request leave the controller.
Definition: mem_ctrl.hh:105
gem5::memory::MemPacket::size
unsigned int size
The size of this dram packet in bytes It is always equal or smaller than the burst size.
Definition: mem_ctrl.hh:142
gem5::memory::MemPacket::isWrite
bool isWrite() const
Return true if its a write packet (interface compatibility with Packet)
Definition: mem_ctrl.hh:195
gem5::memory::MemCtrl::readsThisTime
uint32_t readsThisTime
Definition: mem_ctrl.hh:491
gem5::memory::MemCtrl::isInWriteQueue
std::unordered_set< Addr > isInWriteQueue
To avoid iterating over the write queue to check for overlapping transactions, maintain a set of burs...
Definition: mem_ctrl.hh:450
memory
Definition: mem.h:38
gem5::memory::MemCtrl::recvAtomicBackdoor
Tick recvAtomicBackdoor(PacketPtr pkt, MemBackdoorPtr &backdoor)
Definition: mem_ctrl.cc:162
gem5::memory::MemCtrl::CtrlStats
Definition: mem_ctrl.hh:534
gem5::memory::MemCtrl::CtrlStats::requestorWriteAccesses
statistics::Vector requestorWriteAccesses
Definition: mem_ctrl.hh:583
gem5::memory::MemCtrl::MemoryPort::MemoryPort
MemoryPort(const std::string &name, MemCtrl &_ctrl)
Definition: mem_ctrl.cc:1465
gem5::memory::MemCtrl::addToWriteQueue
void addToWriteQueue(PacketPtr pkt, unsigned int pkt_count, bool is_dram)
Decode the incoming pkt, create a mem_pkt and push to the back of the write queue.
Definition: mem_ctrl.cc:316
gem5::memory::MemCtrl::restartScheduler
void restartScheduler(Tick tick)
restart the controller This can be used by interfaces to restart the scheduler after maintainence com...
Definition: mem_ctrl.hh:684
gem5::memory::MemCtrl::MemoryPort
Definition: mem_ctrl.hh:248
gem5::memory::MemCtrl::processRespondEvent
void processRespondEvent()
Definition: mem_ctrl.cc:499
gem5::memory::MemCtrl::verifySingleCmd
Tick verifySingleCmd(Tick cmd_tick, Tick max_cmds_per_burst)
Check for command bus contention for single cycle command.
Definition: mem_ctrl.cc:704
gem5::memory::MemCtrl::CtrlStats::requestorReadTotalLat
statistics::Vector requestorReadTotalLat
Definition: mem_ctrl.hh:586
gem5::memory::MemPacket::pkt
const PacketPtr pkt
This comes from the outside world.
Definition: mem_ctrl.hh:108
gem5::memory::MemCtrl
The memory controller is a single-channel memory controller capturing the most important timing const...
Definition: mem_ctrl.hh:242
gem5::statistics::Average
A stat that calculates the per tick average of a value.
Definition: statistics.hh:1955
gem5::memory::MemCtrl::writeBufferSize
const uint32_t writeBufferSize
Definition: mem_ctrl.hh:486
gem5::statistics::Vector
A vector of scalar stats.
Definition: statistics.hh:2003
gem5::statistics::Formula
A formula for statistics that is calculated when printed.
Definition: statistics.hh:2536
std::vector
STL vector class.
Definition: stl.hh:37
gem5::memory::MemCtrl::respondEvent
EventFunctionWrapper respondEvent
Definition: mem_ctrl.hh:299
gem5::memory::MemCtrl::startup
virtual void startup() override
startup() is the final initialization call before simulation.
Definition: mem_ctrl.cc:111
gem5::memory::MemCtrl::CtrlStats::requestorWriteTotalLat
statistics::Vector requestorWriteTotalLat
Definition: mem_ctrl.hh:587
gem5::memory::MemCtrl::prevArrival
Tick prevArrival
Definition: mem_ctrl.hh:524
gem5::memory::MemCtrl::selQueue
std::vector< MemPacketQueue > & selQueue(bool is_read)
Select either the read or write queue.
Definition: mem_ctrl.hh:608
gem5::memory::MemCtrl::memSchedPolicy
enums::MemSched memSchedPolicy
Memory controller configuration initialized based on parameter values.
Definition: mem_ctrl.hh:497
gem5::memory::MemCtrl::packetReady
bool packetReady(MemPacket *pkt)
Determine if there is a packet that can issue.
Definition: mem_ctrl.cc:1160
gem5::InvalidPortID
const PortID InvalidPortID
Definition: types.hh:253
gem5::memory::MemCtrl::CtrlStats::readPktSize
statistics::Vector readPktSize
Definition: mem_ctrl.hh:556
gem5::memory::MemCtrl::MemCtrl
MemCtrl(const MemCtrlParams &p)
Definition: mem_ctrl.cc:58
gem5::memory::MemCtrl::MemoryPort::queue
RespPacketQueue queue
Definition: mem_ctrl.hh:251
gem5::memory::MemCtrl::CtrlStats::avgGap
statistics::Formula avgGap
Definition: mem_ctrl.hh:571
gem5::memory::MemCtrl::CtrlStats::bytesReadSys
statistics::Scalar bytesReadSys
Definition: mem_ctrl.hh:564
gem5::memory::MemCtrl::inReadBusState
bool inReadBusState(bool next_state) const
Check the current direction of the memory channel.
Definition: mem_ctrl.cc:791
gem5::memory::MemCtrl::retryRdReq
bool retryRdReq
Remember if we have to retry a request when available.
Definition: mem_ctrl.hh:286
gem5::memory::MemCtrl::CtrlStats::requestorReadAccesses
statistics::Vector requestorReadAccesses
Definition: mem_ctrl.hh:582
gem5::memory::DRAMInterface
Interface to DRAM devices with media specific parameters, statistics, and functions.
Definition: mem_interface.hh:308
gem5::memory::MemPacket::entryTime
const Tick entryTime
When did request enter the controller.
Definition: mem_ctrl.hh:102
gem5::memory::MemCtrl::nvm
NVMInterface *const nvm
Create pointer to interface of the actual nvm media when connected.
Definition: mem_ctrl.hh:477
gem5::memory::MemCtrl::CtrlStats::avgWrQLen
statistics::Average avgWrQLen
Definition: mem_ctrl.hh:552
gem5::memory::MemCtrl::recvAtomic
Tick recvAtomic(PacketPtr pkt)
Definition: mem_ctrl.cc:127
gem5::memory::MemCtrl::CtrlStats::writePktSize
statistics::Vector writePktSize
Definition: mem_ctrl.hh:557
gem5::statistics::Histogram
A simple histogram stat.
Definition: statistics.hh:2123
gem5::memory::MemCtrl::writeQueue
std::vector< MemPacketQueue > writeQueue
Definition: mem_ctrl.hh:441
gem5::memory::MemCtrl::writeHighThreshold
const uint32_t writeHighThreshold
Definition: mem_ctrl.hh:487
gem5::memory::MemCtrl::respondEventScheduled
bool respondEventScheduled() const
Is there a respondEvent scheduled?
Definition: mem_ctrl.hh:668
gem5::DrainState
DrainState
Object drain/handover states.
Definition: drain.hh:74
gem5::memory::MemCtrl::inWriteBusState
bool inWriteBusState(bool next_state) const
Check the current direction of the memory channel.
Definition: mem_ctrl.cc:804
gem5::memory::MemCtrl::MemoryPort::ctrl
MemCtrl & ctrl
Definition: mem_ctrl.hh:252
gem5::memory::qos::MemCtrl::schedule
uint8_t schedule(RequestorID id, uint64_t data)
Definition: mem_ctrl.cc:218
gem5::memory::MemCtrl::accessAndRespond
void accessAndRespond(PacketPtr pkt, Tick static_latency)
When a packet reaches its "readyTime" in the response Q, use the "access()" method in AbstractMemory ...
Definition: mem_ctrl.cc:639
gem5::memory::MemPacket::addr
Addr addr
The starting address of the packet.
Definition: mem_ctrl.hh:136
gem5::memory::MemCtrl::CtrlStats::neitherReadNorWriteReqs
statistics::Scalar neitherReadNorWriteReqs
Definition: mem_ctrl.hh:549
gem5::memory::MemCtrl::minWriteToReadDataGap
Tick minWriteToReadDataGap()
Calculate the minimum delay used when scheduling a write-to-read transision.
Definition: mem_ctrl.cc:1175
gem5::memory::MemCtrl::port
MemoryPort port
Our incoming port, for a multi-ported controller add a crossbar in front of it.
Definition: mem_ctrl.hh:276
gem5::memory::MemCtrl::CtrlStats::CtrlStats
CtrlStats(MemCtrl &ctrl)
Definition: mem_ctrl.cc:1191
gem5::memory::MemCtrl::nextBurstAt
Tick nextBurstAt
Till when must we wait before issuing next RD/WR burst?
Definition: mem_ctrl.hh:522
gem5::memory::MemCtrl::processNextReqEvent
void processNextReqEvent()
Bunch of things requires to setup "events" in gem5 When event "respondEvent" occurs for example,...
Definition: mem_ctrl.cc:874
gem5::memory::MemCtrl::CtrlStats::requestorReadBytes
statistics::Vector requestorReadBytes
Definition: mem_ctrl.hh:574
gem5::memory::MemCtrl::CtrlStats::numWrRetry
statistics::Scalar numWrRetry
Definition: mem_ctrl.hh:555
gem5::memory::MemPacket::row
const uint32_t row
Definition: mem_ctrl.hh:121
gem5::QueuedResponsePort
A queued port is a port that has an infinite queue for outgoing packets and thus decouples the module...
Definition: qport.hh:61
gem5::Packet
A Packet is used to encapsulate a transfer between two objects in the memory system (e....
Definition: packet.hh:283
gem5::memory::MemCtrl::CtrlStats::requestorReadAvgLat
statistics::Formula requestorReadAvgLat
Definition: mem_ctrl.hh:590
gem5::memory::MemCtrl::readQueueFull
bool readQueueFull(unsigned int pkt_count) const
Check if the read queue has room for more entries.
Definition: mem_ctrl.cc:174
gem5::MipsISA::p
Bitfield< 0 > p
Definition: pra_constants.hh:326
statistics.hh
gem5::Tick
uint64_t Tick
Tick count type.
Definition: types.hh:58
gem5::memory::MemPacket::isDram
bool isDram() const
Return true if its a DRAM access.
Definition: mem_ctrl.hh:200
gem5::memory::MemCtrl::recvFunctional
void recvFunctional(PacketPtr pkt)
Definition: mem_ctrl.cc:1384
gem5::memory::MemCtrl::recvTimingReq
bool recvTimingReq(PacketPtr pkt)
Definition: mem_ctrl.cc:422
gem5::memory::MemPacket
A memory packet stores packets along with the timestamp of when the packet entered the queue,...
Definition: mem_ctrl.hh:97
gem5::memory::MemCtrl::stats
CtrlStats stats
Definition: mem_ctrl.hh:594
gem5::memory::MemCtrl::drain
DrainState drain() override
Draining is the process of clearing out the states of SimObjects.These are the SimObjects that are pa...
Definition: mem_ctrl.cc:1420
gem5::memory::MemCtrl::init
virtual void init() override
init() is called after all C++ SimObjects have been created and all ports are connected.
Definition: mem_ctrl.cc:101
gem5::memory::MemPacket::qosValue
void qosValue(const uint8_t qv)
Set the packet QoS value (interface compatibility with Packet)
Definition: mem_ctrl.hh:159
gem5::memory::MemCtrl::pruneBurstTick
void pruneBurstTick()
Remove commands that have already issued from burstTicks.
Definition: mem_ctrl.cc:683
gem5::memory::MemCtrl::pendingDelete
std::unique_ptr< Packet > pendingDelete
Upstream caches need this packet until true is returned, so hold it for deletion until a subsequent c...
Definition: mem_ctrl.hh:600
gem5::memory::MemCtrl::retryWrReq
bool retryWrReq
Definition: mem_ctrl.hh:287
gem5::memory::MemPacket::_qosValue
uint8_t _qosValue
QoS value of the encapsulated packet read at queuing time.
Definition: mem_ctrl.hh:153
gem5::memory::MemCtrl::allIntfDrained
bool allIntfDrained() const
Ensure that all interfaced have drained commands.
Definition: mem_ctrl.cc:1409
gem5::memory::MemCtrl::CtrlStats::rdQLenPdf
statistics::Vector rdQLenPdf
Definition: mem_ctrl.hh:558
gem5::memory::MemCtrl::chooseNextFRFCFS
MemPacketQueue::iterator chooseNextFRFCFS(MemPacketQueue &queue, Tick extra_col_delay)
For FR-FCFS policy reorder the read/write queue depending on row buffer hits and earliest bursts avai...
Definition: mem_ctrl.cc:597
gem5::memory::MemCtrl::CtrlStats::bytesWrittenSys
statistics::Scalar bytesWrittenSys
Definition: mem_ctrl.hh:565
gem5::memory::MemCtrl::MemoryPort::recvFunctional
void recvFunctional(PacketPtr pkt) override
Receive a functional request packet from the peer.
Definition: mem_ctrl.cc:1486
gem5::memory::MemCtrl::CtrlStats::writeReqs
statistics::Scalar writeReqs
Definition: mem_ctrl.hh:544
gem5::memory::BurstHelper::burstsServiced
unsigned int burstsServiced
Number of bursts serviced so far for a system packet.
Definition: mem_ctrl.hh:86
gem5::memory::MemCtrl::CtrlStats::regStats
void regStats() override
Callback to set stat parameters.
Definition: mem_ctrl.cc:1288
gem5::memory::MemPacket::requestorId
RequestorID requestorId() const
Get the packet RequestorID (interface compatibility with Packet)
Definition: mem_ctrl.hh:171
gem5::memory::MemCtrl::isTimingMode
bool isTimingMode
Remember if the memory system is in timing mode.
Definition: mem_ctrl.hh:281
gem5::memory::MemPacket::qosValue
uint8_t qosValue() const
Get the packet QoS value (interface compatibility with Packet)
Definition: mem_ctrl.hh:165
gem5::memory::MemCtrl::CtrlStats::numRdRetry
statistics::Scalar numRdRetry
Definition: mem_ctrl.hh:554
gem5::memory::MemCtrl::CtrlStats::avgRdBWSys
statistics::Formula avgRdBWSys
Definition: mem_ctrl.hh:567
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::memory::MemCtrl::respQueue
std::deque< MemPacket * > respQueue
Response queue where read packets wait after we're done working with them, but it's not time to send ...
Definition: mem_ctrl.hh:460
gem5::memory::MemCtrl::frontendLatency
const Tick frontendLatency
Pipeline latency of the controller frontend.
Definition: mem_ctrl.hh:504
gem5::memory::BurstHelper::BurstHelper
BurstHelper(unsigned int _burstCount)
Definition: mem_ctrl.hh:88
gem5::memory::MemCtrl::CtrlStats::wrQLenPdf
statistics::Vector wrQLenPdf
Definition: mem_ctrl.hh:559
gem5::memory::MemCtrl::MemoryPort::recvAtomicBackdoor
Tick recvAtomicBackdoor(PacketPtr pkt, MemBackdoorPtr &backdoor) override
Receive an atomic request packet from the peer, and optionally provide a backdoor to the data being a...
Definition: mem_ctrl.cc:1507
gem5::MemBackdoor
Definition: backdoor.hh:41
gem5::memory::MemCtrl::CtrlStats::servicedByWrQ
statistics::Scalar servicedByWrQ
Definition: mem_ctrl.hh:547
gem5::memory::MemCtrl::CtrlStats::totGap
statistics::Scalar totGap
Definition: mem_ctrl.hh:570
gem5::memory::MemCtrl::readQueue
std::vector< MemPacketQueue > readQueue
The controller's main read and write queues, with support for QoS reordering.
Definition: mem_ctrl.hh:440
gem5::memory::MemCtrl::CtrlStats::readBursts
statistics::Scalar readBursts
Definition: mem_ctrl.hh:545
gem5::memory::MemPacket::getAddr
Addr getAddr() const
Get the packet address (interface compatibility with Packet)
Definition: mem_ctrl.hh:183
gem5::memory::MemCtrl::requestEventScheduled
bool requestEventScheduled() const
Is there a read/write burst Event scheduled?
Definition: mem_ctrl.hh:675
gem5::memory::MemCtrl::burstTicks
std::unordered_multiset< Tick > burstTicks
Holds count of commands issued in burst window starting at defined Tick.
Definition: mem_ctrl.hh:467
gem5::EventFunctionWrapper
Definition: eventq.hh:1115
gem5::memory::MemCtrl::CtrlStats::requestorWriteRate
statistics::Formula requestorWriteRate
Definition: mem_ctrl.hh:579
mem_ctrl.hh
gem5::memory::MemPacket::bank
const uint8_t bank
Definition: mem_ctrl.hh:120
gem5::memory::MemCtrl::CtrlStats::readReqs
statistics::Scalar readReqs
Definition: mem_ctrl.hh:543
gem5::memory::MemCtrl::doBurstAccess
void doBurstAccess(MemPacket *mem_pkt)
Actually do the burst based on media specific access function.
Definition: mem_ctrl.cc:817
gem5::memory::MemCtrl::minReadToWriteDataGap
Tick minReadToWriteDataGap()
Calculate the minimum delay used when scheduling a read-to-write transision.
Definition: mem_ctrl.cc:1167
gem5::memory::MemCtrl::writeLowThreshold
const uint32_t writeLowThreshold
Definition: mem_ctrl.hh:488
gem5::memory::MemPacket::_requestorId
const RequestorID _requestorId
RequestorID associated with the packet.
Definition: mem_ctrl.hh:111
gem5::memory::MemCtrl::MemoryPort::getAddrRanges
AddrRangeList getAddrRanges() const override
Get a list of the non-overlapping address ranges the owner is responsible for.
Definition: mem_ctrl.cc:1471
gem5::memory::MemCtrl::verifyMultiCmd
Tick verifyMultiCmd(Tick cmd_tick, Tick max_cmds_per_burst, Tick max_multi_cmd_split=0)
Check for command bus contention for multi-cycle (2 currently) command.
Definition: mem_ctrl.cc:727
gem5::memory::MemCtrl::getPort
Port & getPort(const std::string &if_name, PortID idx=InvalidPortID) override
Get a port with a given name and index.
Definition: mem_ctrl.cc:1399
gem5::memory::MemCtrl::MemoryPort::recvAtomic
Tick recvAtomic(PacketPtr pkt) override
Receive an atomic request packet from the peer.
Definition: mem_ctrl.cc:1501
gem5::Port
Ports are used to interface objects to each other.
Definition: port.hh:61
qport.hh
gem5::memory::MemPacket::rank
const uint8_t rank
Will be populated by address decoder.
Definition: mem_ctrl.hh:119
gem5::memory::MemPacket::dram
const bool dram
Does this packet access DRAM?
Definition: mem_ctrl.hh:116
gem5::memory::MemCtrl::burstAlign
Addr burstAlign(Addr addr, bool is_dram) const
Burst-align an address.
Definition: mem_ctrl.cc:1183
std::deque
STL deque class.
Definition: stl.hh:44
gem5::memory::MemCtrl::writeQueueFull
bool writeQueueFull(unsigned int pkt_count) const
Check if the write queue has room for more entries.
Definition: mem_ctrl.cc:186
gem5::memory::MemPacket::getSize
unsigned int getSize() const
Get the packet size (interface compatibility with Packet)
Definition: mem_ctrl.hh:177
gem5::Clocked::tick
Tick tick
Definition: clocked_object.hh:68
gem5::memory::MemCtrl::CtrlStats::writeBursts
statistics::Scalar writeBursts
Definition: mem_ctrl.hh:546
gem5::memory::MemCtrl::CtrlStats::rdPerTurnAround
statistics::Histogram rdPerTurnAround
Definition: mem_ctrl.hh:560
gem5::memory::MemCtrl::CtrlStats::requestorWriteAvgLat
statistics::Formula requestorWriteAvgLat
Definition: mem_ctrl.hh:591
gem5::memory::BurstHelper
A burst helper helps organize and manage a packet that is larger than the memory burst size.
Definition: mem_ctrl.hh:78
gem5::statistics::Group
Statistics container.
Definition: group.hh:93
gem5::memory::MemCtrl::CtrlStats::ctrl
MemCtrl & ctrl
Definition: mem_ctrl.hh:540
gem5::memory::MemCtrl::getBurstWindow
Tick getBurstWindow(Tick cmd_tick)
Calculate burst window aligned tick.
Definition: mem_ctrl.cc:696
gem5::memory::qos::MemCtrl
The qos::MemCtrl is a base class for Memory objects which support QoS - it provides access to a set o...
Definition: mem_ctrl.hh:80
gem5::memory::MemCtrl::chooseNext
MemPacketQueue::iterator chooseNext(MemPacketQueue &queue, Tick extra_col_delay)
The memory schduler/arbiter - picks which request needs to go next, based on the specified policy suc...
Definition: mem_ctrl.cc:562
gem5::RequestorID
uint16_t RequestorID
Definition: request.hh:95
gem5::memory::MemCtrl::CtrlStats::avgWrBWSys
statistics::Formula avgWrBWSys
Definition: mem_ctrl.hh:568
gem5::memory::MemPacketQueue
std::deque< MemPacket * > MemPacketQueue
Definition: mem_ctrl.hh:216
gem5::memory::MemCtrl::minWritesPerSwitch
const uint32_t minWritesPerSwitch
Definition: mem_ctrl.hh:489
gem5::memory::MemCtrl::drainResume
virtual void drainResume() override
Resume execution after a successful drain.
Definition: mem_ctrl.cc:1447
std::list< AddrRange >
gem5::memory::MemCtrl::commandWindow
const Tick commandWindow
Length of a command window, used to check command bandwidth.
Definition: mem_ctrl.hh:517
gem5::memory::MemCtrl::CtrlStats::mergedWrBursts
statistics::Scalar mergedWrBursts
Definition: mem_ctrl.hh:548
gem5::memory::MemCtrl::printQs
void printQs() const
Used for debugging to observe the contents of the queues.
Definition: mem_ctrl.cc:397
gem5::memory::MemCtrl::nextReqTime
Tick nextReqTime
The soonest you have to start thinking about the next request is the longest access time that can occ...
Definition: mem_ctrl.hh:532
gem5::memory::BurstHelper::burstCount
const unsigned int burstCount
Number of bursts requred for a system packet.
Definition: mem_ctrl.hh:83
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40
gem5::memory::MemPacket::isRead
bool isRead() const
Return true if its a read packet (interface compatibility with Packet)
Definition: mem_ctrl.hh:189
gem5::memory::MemCtrl::CtrlStats::avgRdQLen
statistics::Average avgRdQLen
Definition: mem_ctrl.hh:551
gem5::memory::MemCtrl::addToReadQueue
void addToReadQueue(PacketPtr pkt, unsigned int pkt_count, bool is_dram)
When a new read comes in, first check if the write q has a pending request to the same address....
Definition: mem_ctrl.cc:197
gem5::memory::MemCtrl::CtrlStats::wrPerTurnAround
statistics::Histogram wrPerTurnAround
Definition: mem_ctrl.hh:561
gem5::memory::MemCtrl::writesThisTime
uint32_t writesThisTime
Definition: mem_ctrl.hh:490
gem5::memory::MemPacket::bankId
const uint16_t bankId
Bank id is calculated considering banks in all the ranks eg: 2 ranks each with 8 banks,...
Definition: mem_ctrl.hh:128
callback.hh
gem5::memory::MemPacket::MemPacket
MemPacket(PacketPtr _pkt, bool is_read, bool is_dram, uint8_t _rank, uint8_t _bank, uint32_t _row, uint16_t bank_id, Addr _addr, unsigned int _size)
Definition: mem_ctrl.hh:202
gem5::memory::MemCtrl::CtrlStats::requestorWriteBytes
statistics::Vector requestorWriteBytes
Definition: mem_ctrl.hh:575
gem5::Event::scheduled
bool scheduled() const
Determine if the current event is scheduled.
Definition: eventq.hh:465
gem5::memory::MemPacket::read
const bool read
Definition: mem_ctrl.hh:113
gem5::X86ISA::addr
Bitfield< 3 > addr
Definition: types.hh:84
eventq.hh

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