gem5  v22.0.0.2
dram_interface.hh
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40 
46 #ifndef __DRAM_INTERFACE_HH__
47 #define __DRAM_INTERFACE_HH__
48 
49 #include "mem/drampower.hh"
50 #include "mem/mem_interface.hh"
51 #include "params/DRAMInterface.hh"
52 
53 namespace gem5
54 {
55 
56 namespace memory
57 {
58 
66 {
67  private:
72  struct Command
73  {
74  Data::MemCommand::cmds type;
75  uint8_t bank;
77 
78  constexpr Command(Data::MemCommand::cmds _type, uint8_t _bank,
79  Tick time_stamp)
80  : type(_type), bank(_bank), timeStamp(time_stamp)
81  { }
82  };
83 
112  {
113  PWR_IDLE = 0,
119  };
120 
152  {
153  REF_IDLE = 0,
160  };
161 
162  class Rank;
163  struct RankStats : public statistics::Group
164  {
165  RankStats(DRAMInterface &dram, Rank &rank);
166 
167  void regStats() override;
168  void resetStats() override;
169  void preDumpStats() override;
170 
172 
173  /*
174  * Command energies
175  */
181 
182  /*
183  * Active Background Energy
184  */
186 
187  /*
188  * Precharge Background Energy
189  */
191 
192  /*
193  * Active Power-Down Energy
194  */
196 
197  /*
198  * Precharge Power-Down Energy
199  */
201 
202  /*
203  * self Refresh Energy
204  */
206 
209 
215 
220  };
221 
229  class Rank : public EventManager
230  {
231  private:
232 
237 
243 
248 
253 
258 
262  void updatePowerStats();
263 
271  void schedulePowerEvent(PowerState pwr_state, Tick tick);
272 
273  public:
274 
279 
284 
289 
293  uint8_t rank;
294 
298  uint32_t readEntries;
299 
303  uint32_t writeEntries;
304 
311 
316 
321 
329 
335 
340  unsigned int numBanksActive;
341 
344 
349 
350  Rank(const DRAMInterfaceParams &_p, int _rank,
351  DRAMInterface& _dram);
352 
353  const std::string name() const { return csprintf("%d", rank); }
354 
361  void startup(Tick ref_tick);
362 
366  void suspend();
367 
374  bool inRefIdleState() const { return refreshState == REF_IDLE; }
375 
383  bool inPwrIdleState() const { return pwrState == PWR_IDLE; }
384 
395  bool forceSelfRefreshExit() const;
396 
403  bool isQueueEmpty() const;
404 
409  void checkDrainDone();
410 
417  void flushCmdList();
418 
422  void computeStats();
423 
427  void resetStats();
428 
435  void powerDownSleep(PowerState pwr_state, Tick tick);
436 
444  void scheduleWakeUpEvent(Tick exit_delay);
445 
446  void processWriteDoneEvent();
448 
449  void processActivateEvent();
451 
452  void processPrechargeEvent();
454 
455  void processRefreshEvent();
457 
458  void processPowerEvent();
460 
461  void processWakeUpEvent();
463 
464  protected:
466  };
467 
475  static bool
476  sortTime(const Command& cmd, const Command& cmd_next)
477  {
478  return cmd.timeStamp < cmd_next.timeStamp;
479  }
480 
484  const uint32_t bankGroupsPerRank;
485  const bool bankGroupArch;
486 
490  const Tick tRL;
491  const Tick tWL;
495  const Tick tCCD_L;
496  const Tick tRCD_RD;
497  const Tick tRCD_WR;
498  const Tick tRP;
499  const Tick tRAS;
500  const Tick tWR;
501  const Tick tRTP;
502  const Tick tRFC;
503  const Tick tREFI;
504  const Tick tRRD;
505  const Tick tRRD_L;
506  const Tick tPPD;
507  const Tick tAAD;
508  const Tick tXAW;
509  const Tick tXP;
510  const Tick tXS;
512  const bool dataClockSync;
513  const bool burstInterleave;
514  const uint8_t twoCycleActivate;
515  const uint32_t activationLimit;
518 
519 
520  enums::PageManage pageMgmt;
525  const uint32_t maxAccessesPerRow;
526 
527  // timestamp offset
528  uint64_t timeStampOffset;
529 
530  // Holds the value of the DRAM rank of burst issued
531  uint8_t activeRank;
532 
535 
538 
550  void activateBank(Rank& rank_ref, Bank& bank_ref, Tick act_tick,
551  uint32_t row);
552 
564  void prechargeBank(Rank& rank_ref, Bank& bank_ref,
565  Tick pre_tick, bool auto_or_preall = false,
566  bool trace = true);
567 
568  struct DRAMStats : public statistics::Group
569  {
571 
572  void regStats() override;
573  void resetStats() override;
574 
576 
580 
584 
585  // Latencies summed over all requests
589 
590  // Average latencies per request
594 
595  // Row hit count and rate
601  // Number of bytes transferred to/from DRAM
604 
605  // Average bandwidth
609  // bus utilization
614  };
615 
617 
622 
623  /*
624  * @return delay between write and read commands
625  */
626  Tick writeToReadDelay() const override { return tBURST + tWTR + tWL; }
627 
639  minBankPrep(const MemPacketQueue& queue, Tick min_col_at) const;
640 
641  /*
642  * @return time to send a burst of data without gaps
643  */
644  Tick
645  burstDelay() const
646  {
647  return (burstInterleave ? tBURST_MAX / 2 : tBURST);
648  }
649 
650  public:
654  void init() override;
655 
659  void startup() override;
660 
667  void setupRank(const uint8_t rank, const bool is_read) override;
668 
669  MemPacket* decodePacket(const PacketPtr pkt, Addr pkt_addr,
670  unsigned int size, bool is_read,
671  uint8_t pseudo_channel = 0) override;
672 
676  void drainRanks() override;
677 
687  bool allRanksDrained() const override;
688 
692  void suspend() override;
693 
694  /*
695  * @return time to offset next command
696  */
697  Tick commandOffset() const override
698  {
699  return (tRP + std::max(tRCD_RD, tRCD_WR));
700  }
701 
702  /*
703  * Function to calulate unloaded, closed bank access latency
704  */
705  Tick accessLatency() const override { return (tRP + tRCD_RD + tRL); }
706 
716  chooseNextFRFCFS(MemPacketQueue& queue, Tick min_col_at) const override;
717 
733  doBurstAccess(MemPacket* mem_pkt, Tick next_burst_at,
734  const std::vector<MemPacketQueue>& queue) override;
735 
743  bool
744  burstReady(MemPacket* pkt) const override
745  {
746  return ranks[pkt->rank]->inRefIdleState();
747  }
748 
757  bool isBusy(bool read_queue_empty, bool all_writes_nvm) override;
758 
766  void addRankToRankDelay(Tick cmd_at) override;
767 
775  void respondEvent(uint8_t rank) override;
776 
783  void checkRefreshState(uint8_t rank) override;
784 
788  bool readsWaitingToIssue() const override { return false;}
789  void chooseRead(MemPacketQueue& queue) override { }
790  bool writeRespQueueFull() const override { return false;}
791 
792  DRAMInterface(const DRAMInterfaceParams &_p);
793 };
794 
795 } // namespace memory
796 } // namespace gem5
797 
798 #endif //__DRAM_INTERFACE_HH__
gem5::memory::DRAMInterface::Rank::suspend
void suspend()
Stop the refresh events.
Definition: dram_interface.cc:1168
gem5::statistics::Scalar
This is a simple scalar statistic, like a counter.
Definition: statistics.hh:1930
gem5::memory::DRAMInterface::tRRD_L
const Tick tRRD_L
Definition: dram_interface.hh:505
gem5::memory::DRAMInterface::DRAMStats::avgWrBW
statistics::Formula avgWrBW
Definition: dram_interface.hh:607
gem5::memory::DRAMInterface::enableDRAMPowerdown
bool enableDRAMPowerdown
Enable or disable DRAM powerdown states.
Definition: dram_interface.hh:534
gem5::memory::DRAMInterface::DRAMStats::perBankRdBursts
statistics::Vector perBankRdBursts
DRAM per bank stats.
Definition: dram_interface.hh:582
gem5::memory::DRAMInterface::burstReady
bool burstReady(MemPacket *pkt) const override
Check if a burst operation can be issued to the DRAM.
Definition: dram_interface.hh:744
gem5::memory::DRAMInterface::tWR
const Tick tWR
Definition: dram_interface.hh:500
gem5::memory::DRAMInterface::burstDelay
Tick burstDelay() const
Definition: dram_interface.hh:645
gem5::memory::DRAMInterface::Rank::computeStats
void computeStats()
Computes stats just prior to dump event.
Definition: dram_interface.cc:1809
gem5::memory::DRAMInterface::Rank::processPrechargeEvent
void processPrechargeEvent()
Definition: dram_interface.cc:1244
gem5::memory::DRAMInterface::Rank::writeEntries
uint32_t writeEntries
Track number of packets in write queue going to this rank.
Definition: dram_interface.hh:303
gem5::memory::DRAMInterface::PowerState
PowerState
The power state captures the different operational states of the DRAM and interacts with the bus read...
Definition: dram_interface.hh:111
gem5::memory::DRAMInterface::Rank::processPowerEvent
void processPowerEvent()
Definition: dram_interface.cc:1633
gem5::memory::DRAMInterface::RefreshState
RefreshState
The refresh state is used to control the progress of the refresh scheduling.
Definition: dram_interface.hh:151
gem5::memory::DRAMInterface::DRAMStats::writeRowHits
statistics::Scalar writeRowHits
Definition: dram_interface.hh:597
gem5::memory::DRAMInterface::DRAMStats::writeBursts
statistics::Scalar writeBursts
Definition: dram_interface.hh:579
gem5::memory::DRAMInterface::activeRank
uint8_t activeRank
Definition: dram_interface.hh:531
gem5::memory::DRAMInterface::DRAMStats::avgQLat
statistics::Formula avgQLat
Definition: dram_interface.hh:591
gem5::memory::MemInterface::tBURST
const Tick tBURST
Definition: mem_interface.hh:149
gem5::memory::DRAMInterface::Rank::pwrStateTrans
PowerState pwrStateTrans
Since we are taking decisions out of order, we need to keep track of what power transition is happeni...
Definition: dram_interface.hh:242
gem5::memory::DRAMInterface::PWR_PRE_PDN
@ PWR_PRE_PDN
Definition: dram_interface.hh:116
gem5::memory::DRAMInterface::DRAMStats::totQLat
statistics::Scalar totQLat
Definition: dram_interface.hh:586
memory
Definition: mem.h:38
gem5::memory::DRAMInterface::Rank::writeDoneEvent
EventFunctionWrapper writeDoneEvent
Definition: dram_interface.hh:447
drampower.hh
gem5::memory::DRAMInterface::RankStats::readEnergy
statistics::Scalar readEnergy
Definition: dram_interface.hh:178
gem5::memory::DRAMInterface::RankStats::preBackEnergy
statistics::Scalar preBackEnergy
Definition: dram_interface.hh:190
gem5::memory::DRAMInterface::DRAMStats::readBursts
statistics::Scalar readBursts
total number of DRAM bursts serviced
Definition: dram_interface.hh:578
gem5::memory::DRAMInterface::tREFI
const Tick tREFI
Definition: dram_interface.hh:503
gem5::memory::DRAMInterface::tBURST_MAX
const Tick tBURST_MAX
Definition: dram_interface.hh:493
gem5::memory::DRAMInterface::addRankToRankDelay
void addRankToRankDelay(Tick cmd_at) override
Add rank to rank delay to bus timing to all DRAM banks in alli ranks when access to an alternate inte...
Definition: dram_interface.cc:620
gem5::memory::DRAMInterface::Rank::processWakeUpEvent
void processWakeUpEvent()
Definition: dram_interface.cc:1615
gem5::memory::DRAMInterface::DRAMStats::totBusLat
statistics::Scalar totBusLat
Definition: dram_interface.hh:587
gem5::memory::DRAMInterface::RankStats::refreshEnergy
statistics::Scalar refreshEnergy
Definition: dram_interface.hh:180
gem5::memory::DRAMInterface::tWL
const Tick tWL
Definition: dram_interface.hh:491
gem5::memory::DRAMInterface::DRAMStats
Definition: dram_interface.hh:568
gem5::memory::DRAMInterface::Rank::prechargeEvent
EventFunctionWrapper prechargeEvent
Definition: dram_interface.hh:453
gem5::memory::DRAMInterface::Rank::inLowPowerState
bool inLowPowerState
rank is in or transitioning to power-down or self-refresh
Definition: dram_interface.hh:288
gem5::memory::DRAMInterface::Rank::scheduleWakeUpEvent
void scheduleWakeUpEvent(Tick exit_delay)
schedule and event to wake-up from power-down or self-refresh and update bank timing parameters
Definition: dram_interface.cc:1563
gem5::memory::DRAMInterface::checkRefreshState
void checkRefreshState(uint8_t rank) override
Check the refresh state to determine if refresh needs to be kicked back into action after a read resp...
Definition: dram_interface.cc:978
gem5::memory::DRAMInterface::Command
Simple structure to hold the values needed to keep track of commands for DRAMPower.
Definition: dram_interface.hh:72
gem5::memory::DRAMInterface::PWR_REF
@ PWR_REF
Definition: dram_interface.hh:114
gem5::memory::DRAMInterface::chooseNextFRFCFS
std::pair< MemPacketQueue::iterator, Tick > chooseNextFRFCFS(MemPacketQueue &queue, Tick min_col_at) const override
For FR-FCFS policy, find first DRAM command that can issue.
Definition: dram_interface.cc:60
gem5::memory::DRAMInterface::ranks
std::vector< Rank * > ranks
Vector of dram ranks.
Definition: dram_interface.hh:621
gem5::memory::MemInterface::Bank
A basic class to track the bank state, i.e.
Definition: mem_interface.hh:86
gem5::memory::DRAMInterface::tXP
const Tick tXP
Definition: dram_interface.hh:509
gem5::memory::DRAMInterface::RankStats::pwrStateTime
statistics::Vector pwrStateTime
Track time spent in each power state.
Definition: dram_interface.hh:219
gem5::memory::DRAMInterface::activateBank
void activateBank(Rank &rank_ref, Bank &bank_ref, Tick act_tick, uint32_t row)
Keep track of when row activations happen, in order to enforce the maximum number of activations in t...
Definition: dram_interface.cc:175
gem5::memory::DRAMInterface::REF_DRAIN
@ REF_DRAIN
Definition: dram_interface.hh:154
gem5::memory::DRAMInterface::allRanksDrained
bool allRanksDrained() const override
Return true once refresh is complete for all ranks and there are no additional commands enqueued.
Definition: dram_interface.cc:1005
gem5::memory::DRAMInterface::Rank::processWriteDoneEvent
void processWriteDoneEvent()
Definition: dram_interface.cc:1275
gem5::memory::DRAMInterface::bankGroupArch
const bool bankGroupArch
Definition: dram_interface.hh:485
gem5::DRAMPower
DRAMPower is a standalone tool which calculates the power consumed by a DRAM in the system.
Definition: drampower.hh:56
gem5::memory::DRAMInterface::Rank::resetStats
void resetStats()
Reset stats on a stats event.
Definition: dram_interface.cc:1822
gem5::memory::DRAMInterface::maxAccessesPerRow
const uint32_t maxAccessesPerRow
Max column accesses (read and write) per row, before forefully closing it.
Definition: dram_interface.hh:525
gem5::memory::DRAMInterface::DRAMStats::avgBusLat
statistics::Formula avgBusLat
Definition: dram_interface.hh:592
gem5::statistics::Vector
A vector of scalar stats.
Definition: statistics.hh:2006
gem5::memory::DRAMInterface::PWR_ACT
@ PWR_ACT
Definition: dram_interface.hh:117
gem5::memory::DRAMInterface::drainRanks
void drainRanks() override
Iterate through dram ranks to exit self-refresh in order to drain.
Definition: dram_interface.cc:991
gem5::memory::DRAMInterface::Rank::refreshEvent
EventFunctionWrapper refreshEvent
Definition: dram_interface.hh:456
gem5::statistics::Formula
A formula for statistics that is calculated when printed.
Definition: statistics.hh:2539
gem5::memory::DRAMInterface::DRAMStats::bytesPerActivate
statistics::Histogram bytesPerActivate
Definition: dram_interface.hh:600
gem5::memory::DRAMInterface::Rank::outstandingEvents
uint8_t outstandingEvents
Number of ACT, RD, and WR events currently scheduled Incremented when a refresh event is started as w...
Definition: dram_interface.hh:310
std::vector
STL vector class.
Definition: stl.hh:37
gem5::memory::DRAMInterface::Rank::activateEvent
EventFunctionWrapper activateEvent
Definition: dram_interface.hh:450
gem5::memory::DRAMInterface::PWR_IDLE
@ PWR_IDLE
Definition: dram_interface.hh:113
gem5::csprintf
std::string csprintf(const char *format, const Args &...args)
Definition: cprintf.hh:161
gem5::memory::DRAMInterface::Rank::Rank
Rank(const DRAMInterfaceParams &_p, int _rank, DRAMInterface &_dram)
Definition: dram_interface.cc:1117
gem5::memory::DRAMInterface::RankStats::prePowerDownEnergy
statistics::Scalar prePowerDownEnergy
Definition: dram_interface.hh:200
gem5::memory::DRAMInterface::tRTP
const Tick tRTP
Definition: dram_interface.hh:501
gem5::memory::DRAMInterface::Rank::checkDrainDone
void checkDrainDone()
Let the rank check if it was waiting for requests to drain to allow it to transition states.
Definition: dram_interface.cc:1191
gem5::memory::DRAMInterface::rdToWrDlySameBG
const Tick rdToWrDlySameBG
Definition: dram_interface.hh:517
gem5::memory::DRAMInterface::Rank::powerDownSleep
void powerDownSleep(PowerState pwr_state, Tick tick)
Schedule a transition to power-down (sleep)
Definition: dram_interface.cc:1512
gem5::memory::DRAMInterface::Rank::pwrStateTick
Tick pwrStateTick
Track when we transitioned to the current power state.
Definition: dram_interface.hh:252
gem5::memory::DRAMInterface::Command::Command
constexpr Command(Data::MemCommand::cmds _type, uint8_t _bank, Tick time_stamp)
Definition: dram_interface.hh:78
gem5::memory::DRAMInterface::RankStats::totalEnergy
statistics::Scalar totalEnergy
Definition: dram_interface.hh:207
gem5::memory::DRAMInterface::accessLatency
Tick accessLatency() const override
Definition: dram_interface.hh:705
gem5::memory::DRAMInterface::Rank::readEntries
uint32_t readEntries
Track number of packets in read queue going to this rank.
Definition: dram_interface.hh:298
gem5::memory::DRAMInterface::RankStats::regStats
void regStats() override
Callback to set stat parameters.
Definition: dram_interface.cc:2000
gem5::memory::DRAMInterface::RankStats::rank
Rank & rank
Definition: dram_interface.hh:171
gem5::memory::DRAMInterface::Rank::processRefreshEvent
void processRefreshEvent()
Definition: dram_interface.cc:1286
gem5::memory::DRAMInterface::bankGroupsPerRank
const uint32_t bankGroupsPerRank
DRAM specific device characteristics.
Definition: dram_interface.hh:484
gem5::memory::DRAMInterface::RankStats::actEnergy
statistics::Scalar actEnergy
Definition: dram_interface.hh:176
gem5::memory::DRAMInterface::setupRank
void setupRank(const uint8_t rank, const bool is_read) override
Setup the rank based on packet received.
Definition: dram_interface.cc:920
gem5::memory::DRAMInterface::PWR_SREF
@ PWR_SREF
Definition: dram_interface.hh:115
gem5::memory::DRAMInterface::Rank::processActivateEvent
void processActivateEvent()
Definition: dram_interface.cc:1234
gem5::memory::DRAMInterface
Interface to DRAM devices with media specific parameters, statistics, and functions.
Definition: dram_interface.hh:65
gem5::memory::DRAMInterface::Command::type
Data::MemCommand::cmds type
Definition: dram_interface.hh:74
gem5::memory::DRAMInterface::lastStatsResetTick
Tick lastStatsResetTick
The time when stats were last reset used to calculate average power.
Definition: dram_interface.hh:537
gem5::memory::DRAMInterface::REF_PRE
@ REF_PRE
Definition: dram_interface.hh:157
gem5::memory::DRAMInterface::RankStats::averagePower
statistics::Scalar averagePower
Definition: dram_interface.hh:208
gem5::memory::DRAMInterface::Rank::rank
uint8_t rank
Current Rank index.
Definition: dram_interface.hh:293
gem5::statistics::Histogram
A simple histogram stat.
Definition: statistics.hh:2126
gem5::EventManager
Definition: eventq.hh:987
gem5::memory::DRAMInterface::REF_RUN
@ REF_RUN
Definition: dram_interface.hh:159
gem5::memory::DRAMInterface::stats
DRAMStats stats
Definition: dram_interface.hh:616
gem5::memory::DRAMInterface::DRAMStats::peakBW
statistics::Formula peakBW
Definition: dram_interface.hh:608
gem5::memory::DRAMInterface::Rank::name
const std::string name() const
Definition: dram_interface.hh:353
mem_interface.hh
gem5::memory::DRAMInterface::tRCD_RD
const Tick tRCD_RD
Definition: dram_interface.hh:496
gem5::memory::DRAMInterface::tPPD
const Tick tPPD
Definition: dram_interface.hh:506
gem5::memory::DRAMInterface::DRAMInterface
DRAMInterface(const DRAMInterfaceParams &_p)
Definition: dram_interface.cc:636
gem5::memory::DRAMInterface::DRAMStats::avgMemAccLat
statistics::Formula avgMemAccLat
Definition: dram_interface.hh:593
gem5::memory::DRAMInterface::DRAMStats::regStats
void regStats() override
Callback to set stat parameters.
Definition: dram_interface.cc:1915
gem5::memory::DRAMInterface::DRAMStats::DRAMStats
DRAMStats(DRAMInterface &dram)
Definition: dram_interface.cc:1843
gem5::memory::MemInterface
General interface to memory device Includes functions and parameters shared across media types.
Definition: mem_interface.hh:74
gem5::memory::DRAMInterface::tRL
const Tick tRL
DRAM specific timing requirements.
Definition: dram_interface.hh:490
gem5::memory::DRAMInterface::DRAMStats::busUtil
statistics::Formula busUtil
Definition: dram_interface.hh:610
gem5::memory::DRAMInterface::Rank::dram
DRAMInterface & dram
A reference to the parent DRAMInterface instance.
Definition: dram_interface.hh:236
gem5::memory::DRAMInterface::DRAMStats::busUtilWrite
statistics::Formula busUtilWrite
Definition: dram_interface.hh:612
gem5::memory::DRAMInterface::DRAMStats::avgRdBW
statistics::Formula avgRdBW
Definition: dram_interface.hh:606
gem5::memory::DRAMInterface::Rank::banks
std::vector< Bank > banks
Vector of Banks.
Definition: dram_interface.hh:334
gem5::memory::DRAMInterface::DRAMStats::dram
DRAMInterface & dram
Definition: dram_interface.hh:575
gem5::memory::DRAMInterface::tRP
const Tick tRP
Definition: dram_interface.hh:498
gem5::memory::DRAMInterface::Rank::inPwrIdleState
bool inPwrIdleState() const
Check if the current rank has all banks closed and is not in a low power state.
Definition: dram_interface.hh:383
gem5::Packet
A Packet is used to encapsulate a transfer between two objects in the memory system (e....
Definition: packet.hh:291
gem5::memory::DRAMInterface::PWR_ACT_PDN
@ PWR_ACT_PDN
Definition: dram_interface.hh:118
gem5::memory::DRAMInterface::Rank::refreshState
RefreshState refreshState
current refresh state
Definition: dram_interface.hh:283
gem5::memory::DRAMInterface::tXAW
const Tick tXAW
Definition: dram_interface.hh:508
gem5::memory::DRAMInterface::minBankPrep
std::pair< std::vector< uint32_t >, bool > minBankPrep(const MemPacketQueue &queue, Tick min_col_at) const
Find which are the earliest banks ready to issue an activate for the enqueued requests.
Definition: dram_interface.cc:1028
gem5::memory::DRAMInterface::DRAMStats::pageHitRate
statistics::Formula pageHitRate
Definition: dram_interface.hh:613
gem5::memory::DRAMInterface::activationLimit
const uint32_t activationLimit
Definition: dram_interface.hh:515
gem5::Tick
uint64_t Tick
Tick count type.
Definition: types.hh:58
gem5::memory::DRAMInterface::commandOffset
Tick commandOffset() const override
Definition: dram_interface.hh:697
gem5::memory::DRAMInterface::RankStats::actBackEnergy
statistics::Scalar actBackEnergy
Definition: dram_interface.hh:185
gem5::memory::DRAMInterface::isBusy
bool isBusy(bool read_queue_empty, bool all_writes_nvm) override
This function checks if ranks are actively refreshing and therefore busy.
Definition: dram_interface.cc:797
gem5::memory::DRAMInterface::Rank::flushCmdList
void flushCmdList()
Push command out of cmdList queue that are scheduled at or before curTick() to DRAMPower library All ...
Definition: dram_interface.cc:1206
gem5::memory::MemPacket
A memory packet stores packets along with the timestamp of when the packet entered the queue,...
Definition: mem_ctrl.hh:98
gem5::memory::DRAMInterface::Rank::power
DRAMPower power
One DRAMPower instance per rank.
Definition: dram_interface.hh:320
gem5::memory::DRAMInterface::Rank::actTicks
std::deque< Tick > actTicks
List to keep track of activate ticks.
Definition: dram_interface.hh:343
gem5::memory::DRAMInterface::tRRD
const Tick tRRD
Definition: dram_interface.hh:504
gem5::memory::DRAMInterface::Rank::isQueueEmpty
bool isQueueEmpty() const
Check if the command queue of current rank is idle.
Definition: dram_interface.cc:1180
gem5::memory::DRAMInterface::DRAMStats::readRowHits
statistics::Scalar readRowHits
Definition: dram_interface.hh:596
gem5::memory::DRAMInterface::tXS
const Tick tXS
Definition: dram_interface.hh:510
gem5::memory::DRAMInterface::RankStats::writeEnergy
statistics::Scalar writeEnergy
Definition: dram_interface.hh:179
gem5::memory::DRAMInterface::writeToReadDelay
Tick writeToReadDelay() const override
Definition: dram_interface.hh:626
gem5::memory::DRAMInterface::REF_IDLE
@ REF_IDLE
Definition: dram_interface.hh:153
gem5::memory::DRAMInterface::tAAD
const Tick tAAD
Definition: dram_interface.hh:507
std::pair
STL pair class.
Definition: stl.hh:58
gem5::memory::DRAMInterface::Rank::wakeUpEvent
EventFunctionWrapper wakeUpEvent
Definition: dram_interface.hh:462
gem5::memory::MemInterface::tWTR
const Tick tWTR
Definition: mem_interface.hh:151
gem5::memory::DRAMInterface::RankStats::selfRefreshEnergy
statistics::Scalar selfRefreshEnergy
Definition: dram_interface.hh:205
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::memory::DRAMInterface::Rank::updatePowerStats
void updatePowerStats()
Function to update Power Stats.
Definition: dram_interface.cc:1766
gem5::memory::DRAMInterface::tCCD_L
const Tick tCCD_L
Definition: dram_interface.hh:495
gem5::memory::DRAMInterface::wrToRdDlySameBG
const Tick wrToRdDlySameBG
Definition: dram_interface.hh:516
gem5::memory::DRAMInterface::readsWaitingToIssue
bool readsWaitingToIssue() const override
The next three functions are NVM-specific and will be ignored by DRAM.
Definition: dram_interface.hh:788
gem5::memory::DRAMInterface::DRAMStats::totMemAccLat
statistics::Scalar totMemAccLat
Definition: dram_interface.hh:588
gem5::memory::DRAMInterface::Rank::lastBurstTick
Tick lastBurstTick
Track when we issued the last read/write burst.
Definition: dram_interface.hh:348
gem5::EventFunctionWrapper
Definition: eventq.hh:1115
gem5::memory::AbstractMemory::size
uint64_t size() const
Get the memory size.
Definition: abstract_mem.hh:301
gem5::memory::DRAMInterface::twoCycleActivate
const uint8_t twoCycleActivate
Definition: dram_interface.hh:514
gem5::memory::DRAMInterface::REF_START
@ REF_START
Definition: dram_interface.hh:158
gem5::memory::DRAMInterface::Rank::stats
RankStats stats
Definition: dram_interface.hh:465
gem5::memory::DRAMInterface::tRCD_WR
const Tick tRCD_WR
Definition: dram_interface.hh:497
gem5::memory::DRAMInterface::RankStats
Definition: dram_interface.hh:163
gem5::memory::DRAMInterface::Rank::inRefIdleState
bool inRefIdleState() const
Check if there is no refresh and no preparation of refresh ongoing i.e.
Definition: dram_interface.hh:374
gem5::memory::DRAMInterface::respondEvent
void respondEvent(uint8_t rank) override
Complete response process for DRAM when read burst is complete This will update the counters and chec...
Definition: dram_interface.cc:931
gem5::memory::DRAMInterface::REF_PD_EXIT
@ REF_PD_EXIT
Definition: dram_interface.hh:155
gem5::memory::DRAMInterface::Rank::numBanksActive
unsigned int numBanksActive
To track number of banks which are currently active for this rank.
Definition: dram_interface.hh:340
gem5::memory::DRAMInterface::init
void init() override
Initialize the DRAM interface and verify parameters.
Definition: dram_interface.cc:742
gem5::memory::DRAMInterface::suspend
void suspend() override
Iterate through DRAM ranks and suspend them.
Definition: dram_interface.cc:1020
gem5::memory::MemPacket::rank
const uint8_t rank
Will be populated by address decoder.
Definition: mem_ctrl.hh:123
gem5::memory::DRAMInterface::tBURST_MIN
const Tick tBURST_MIN
Definition: dram_interface.hh:492
gem5::memory::DRAMInterface::decodePacket
MemPacket * decodePacket(const PacketPtr pkt, Addr pkt_addr, unsigned int size, bool is_read, uint8_t pseudo_channel=0) override
Address decoder to figure out physical mapping onto ranks, banks, and rows.
Definition: dram_interface.cc:835
gem5::memory::DRAMInterface::tCCD_L_WR
const Tick tCCD_L_WR
Definition: dram_interface.hh:494
gem5::memory::DRAMInterface::REF_SREF_EXIT
@ REF_SREF_EXIT
Definition: dram_interface.hh:156
std::deque< Tick >
gem5::memory::DRAMInterface::dataClockSync
const bool dataClockSync
Definition: dram_interface.hh:512
gem5::memory::DRAMInterface::DRAMStats::perBankWrBursts
statistics::Vector perBankWrBursts
Definition: dram_interface.hh:583
gem5::memory::DRAMInterface::Rank::refreshDueAt
Tick refreshDueAt
Keep track of when a refresh is due.
Definition: dram_interface.hh:257
gem5::memory::DRAMInterface::burstInterleave
const bool burstInterleave
Definition: dram_interface.hh:513
gem5::Clocked::tick
Tick tick
Definition: clocked_object.hh:68
gem5::memory::DRAMInterface::writeRespQueueFull
bool writeRespQueueFull() const override
This function is NVM specific.
Definition: dram_interface.hh:790
gem5::memory::DRAMInterface::DRAMStats::bytesRead
statistics::Scalar bytesRead
Definition: dram_interface.hh:602
gem5::memory::DRAMInterface::clkResyncDelay
const Tick clkResyncDelay
Definition: dram_interface.hh:511
gem5::statistics::Group
Statistics container.
Definition: group.hh:93
gem5::memory::DRAMInterface::Command::timeStamp
Tick timeStamp
Definition: dram_interface.hh:76
gem5::memory::DRAMInterface::prechargeBank
void prechargeBank(Rank &rank_ref, Bank &bank_ref, Tick pre_tick, bool auto_or_preall=false, bool trace=true)
Precharge a given bank and also update when the precharge is done.
Definition: dram_interface.cc:284
gem5::memory::DRAMInterface::RankStats::actPowerDownEnergy
statistics::Scalar actPowerDownEnergy
Definition: dram_interface.hh:195
gem5::memory::DRAMInterface::DRAMStats::bytesWritten
statistics::Scalar bytesWritten
Definition: dram_interface.hh:603
gem5::memory::DRAMInterface::RankStats::preEnergy
statistics::Scalar preEnergy
Definition: dram_interface.hh:177
gem5::memory::DRAMInterface::DRAMStats::writeRowHitRate
statistics::Formula writeRowHitRate
Definition: dram_interface.hh:599
gem5::memory::DRAMInterface::Rank::powerEvent
EventFunctionWrapper powerEvent
Definition: dram_interface.hh:459
gem5::memory::DRAMInterface::Rank::cmdList
std::vector< Command > cmdList
List of commands issued, to be sent to DRAMPpower at refresh and stats dump.
Definition: dram_interface.hh:328
gem5::memory::DRAMInterface::tRFC
const Tick tRFC
Definition: dram_interface.hh:502
gem5::memory::DRAMInterface::chooseRead
void chooseRead(MemPacketQueue &queue) override
This function is NVM specific.
Definition: dram_interface.hh:789
gem5::memory::DRAMInterface::Rank::wakeUpAllowedAt
Tick wakeUpAllowedAt
delay low-power exit until this requirement is met
Definition: dram_interface.hh:315
gem5::memory::DRAMInterface::Rank
Rank class includes a vector of banks.
Definition: dram_interface.hh:229
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: gpu_translation_state.hh:37
gem5::memory::DRAMInterface::DRAMStats::readRowHitRate
statistics::Formula readRowHitRate
Definition: dram_interface.hh:598
gem5::memory::DRAMInterface::RankStats::totalIdleTime
statistics::Scalar totalIdleTime
Stat to track total DRAM idle time.
Definition: dram_interface.hh:214
gem5::memory::DRAMInterface::pageMgmt
enums::PageManage pageMgmt
Definition: dram_interface.hh:520
gem5::memory::DRAMInterface::Rank::schedulePowerEvent
void schedulePowerEvent(PowerState pwr_state, Tick tick)
Schedule a power state transition in the future, and potentially override an already scheduled transi...
Definition: dram_interface.cc:1491
gem5::memory::DRAMInterface::DRAMStats::resetStats
void resetStats() override
Callback to reset stats.
Definition: dram_interface.cc:1838
gem5::memory::DRAMInterface::Rank::startup
void startup(Tick ref_tick)
Kick off accounting for power and refresh states and schedule initial refresh.
Definition: dram_interface.cc:1156
gem5::memory::DRAMInterface::timeStampOffset
uint64_t timeStampOffset
Definition: dram_interface.hh:528
gem5::memory::DRAMInterface::RankStats::preDumpStats
void preDumpStats() override
Callback before stats are dumped.
Definition: dram_interface.cc:2023
gem5::memory::DRAMInterface::Command::bank
uint8_t bank
Definition: dram_interface.hh:75
gem5::memory::DRAMInterface::Rank::pwrStatePostRefresh
PowerState pwrStatePostRefresh
Previous low-power state, which will be re-entered after refresh.
Definition: dram_interface.hh:247
gem5::memory::DRAMInterface::sortTime
static bool sortTime(const Command &cmd, const Command &cmd_next)
Function for sorting Command structures based on timeStamp.
Definition: dram_interface.hh:476
gem5::memory::DRAMInterface::tRAS
const Tick tRAS
Definition: dram_interface.hh:499
gem5::memory::DRAMInterface::doBurstAccess
std::pair< Tick, Tick > doBurstAccess(MemPacket *mem_pkt, Tick next_burst_at, const std::vector< MemPacketQueue > &queue) override
Actually do the burst - figure out the latency it will take to service the req based on bank state,...
Definition: dram_interface.cc:347
gem5::memory::DRAMInterface::Rank::pwrState
PowerState pwrState
Current power state.
Definition: dram_interface.hh:278
gem5::memory::DRAMInterface::startup
void startup() override
Iterate through dram ranks and instantiate per rank startup routine.
Definition: dram_interface.cc:784
gem5::memory::DRAMInterface::DRAMStats::busUtilRead
statistics::Formula busUtilRead
Definition: dram_interface.hh:611
gem5::memory::DRAMInterface::RankStats::RankStats
RankStats(DRAMInterface &dram, Rank &rank)
Definition: dram_interface.cc:1962
gem5::memory::DRAMInterface::RankStats::resetStats
void resetStats() override
Callback to reset stats.
Definition: dram_interface.cc:2015
gem5::memory::DRAMInterface::Rank::forceSelfRefreshExit
bool forceSelfRefreshExit() const
Trigger a self-refresh exit if there are entries enqueued Exit if there are any read entries regardle...
Definition: dram_interface.cc:1832

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