dram_interface.hh

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/*
 * Copyright (c) 2012-2020 ARM Limited
 * All rights reserved
 *
 * The license below extends only to copyright in the software and shall
 * not be construed as granting a license to any other intellectual
 * property including but not limited to intellectual property relating
 * to a hardware implementation of the functionality of the software
 * licensed hereunder.  You may use the software subject to the license
 * terms below provided that you ensure that this notice is replicated
 * unmodified and in its entirety in all distributions of the software,
 * modified or unmodified, in source code or in binary form.
 *
 * Copyright (c) 2013 Amin Farmahini-Farahani
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions are
 * met: redistributions of source code must retain the above copyright
 * notice, this list of conditions and the following disclaimer;
 * redistributions in binary form must reproduce the above copyright
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 * this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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 */
 
#ifndef __DRAM_INTERFACE_HH__
#define __DRAM_INTERFACE_HH__
 
#include "mem/drampower.hh"
#include "mem/mem_interface.hh"
#include "params/DRAMInterface.hh"
 
namespace gem5
{
 
namespace memory
{
 
class DRAMInterface : public MemInterface
{
  private:
    struct Command
    {
       Data::MemCommand::cmds type;
       uint8_t bank;
       Tick timeStamp;
 
       constexpr Command(Data::MemCommand::cmds _type, uint8_t _bank,
                         Tick time_stamp)
            : type(_type), bank(_bank), timeStamp(time_stamp)
        { }
    };
 
    enum PowerState
    {
        PWR_IDLE = 0,
        PWR_REF,
        PWR_SREF,
        PWR_PRE_PDN,
        PWR_ACT,
        PWR_ACT_PDN
    };
 
    enum RefreshState
    {
        REF_IDLE = 0,
        REF_DRAIN,
        REF_PD_EXIT,
        REF_SREF_EXIT,
        REF_PRE,
        REF_START,
        REF_RUN
    };
 
    class Rank;
    struct RankStats : public statistics::Group
    {
        RankStats(DRAMInterface &dram, Rank &rank);
 
        void regStats() override;
        void resetStats() override;
        void preDumpStats() override;
 
        Rank &rank;
 
        /*
         * Command energies
         */
        statistics::Scalar actEnergy;
        statistics::Scalar preEnergy;
        statistics::Scalar readEnergy;
        statistics::Scalar writeEnergy;
        statistics::Scalar refreshEnergy;
 
        /*
         * Active Background Energy
         */
        statistics::Scalar actBackEnergy;
 
        /*
         * Precharge Background Energy
         */
        statistics::Scalar preBackEnergy;
 
        /*
         * Active Power-Down Energy
         */
        statistics::Scalar actPowerDownEnergy;
 
        /*
         * Precharge Power-Down Energy
         */
        statistics::Scalar prePowerDownEnergy;
 
        /*
         * self Refresh Energy
         */
        statistics::Scalar selfRefreshEnergy;
 
        statistics::Scalar totalEnergy;
        statistics::Scalar averagePower;
 
        statistics::Scalar totalIdleTime;
 
        statistics::Vector pwrStateTime;
    };
 
    class Rank : public EventManager
    {
      private:
 
        DRAMInterface& dram;
 
        PowerState pwrStateTrans;
 
        PowerState pwrStatePostRefresh;
 
        Tick pwrStateTick;
 
        Tick refreshDueAt;
 
        void updatePowerStats();
 
        void schedulePowerEvent(PowerState pwr_state, Tick tick);
 
      public:
 
        PowerState pwrState;
 
        RefreshState refreshState;
 
        bool inLowPowerState;
 
        uint8_t rank;
 
        uint32_t readEntries;
 
        uint32_t writeEntries;
 
        uint8_t outstandingEvents;
 
        Tick wakeUpAllowedAt;
 
        DRAMPower power;
 
        std::vector<Command> cmdList;
 
        std::vector<Bank> banks;
 
        unsigned int numBanksActive;
 
        std::deque<Tick> actTicks;
 
        Tick lastBurstTick;
 
        Rank(const DRAMInterfaceParams &_p, int _rank,
             DRAMInterface& _dram);
 
        const std::string
        name() const
        {
            return csprintf("%s.rank%d", dram.name(), rank);
        }
 
        void startup(Tick ref_tick);
 
        void suspend();
 
        bool inRefIdleState() const { return refreshState == REF_IDLE; }
 
        bool
        inPwrIdleState() const
        {
            // If powerdown is not enabled, then the ranks never go to idle
            // states. In that case return true here to prevent checkpointing
            // from getting stuck waiting for DRAM to be idle.
            if (!dram.enableDRAMPowerdown) {
                return true;
            }
 
            return pwrState == PWR_IDLE;
        }
 
        bool forceSelfRefreshExit() const;
 
        bool isQueueEmpty() const;
 
        void checkDrainDone();
 
        void flushCmdList();
 
        void computeStats();
 
        void resetStats();
 
        void powerDownSleep(PowerState pwr_state, Tick tick);
 
        void scheduleWakeUpEvent(Tick exit_delay);
 
        void processWriteDoneEvent();
        EventFunctionWrapper writeDoneEvent;
 
        void processActivateEvent();
        EventFunctionWrapper activateEvent;
 
        void processPrechargeEvent();
        EventFunctionWrapper prechargeEvent;
 
        void processRefreshEvent();
        EventFunctionWrapper refreshEvent;
 
        void processPowerEvent();
        EventFunctionWrapper powerEvent;
 
        void processWakeUpEvent();
        EventFunctionWrapper wakeUpEvent;
 
      protected:
        RankStats stats;
    };
 
    static bool
    sortTime(const Command& cmd, const Command& cmd_next)
    {
        return cmd.timeStamp < cmd_next.timeStamp;
    }
 
    const uint32_t bankGroupsPerRank;
    const bool bankGroupArch;
 
    const Tick tRL;
    const Tick tWL;
    const Tick tBURST_MIN;
    const Tick tBURST_MAX;
    const Tick tCCD_L_WR;
    const Tick tCCD_L;
    const Tick tRCD_RD;
    const Tick tRCD_WR;
    const Tick tRP;
    const Tick tRAS;
    const Tick tWR;
    const Tick tRTP;
    const Tick tRFC;
    const Tick tREFI;
    const Tick tRRD;
    const Tick tRRD_L;
    const Tick tPPD;
    const Tick tAAD;
    const Tick tXAW;
    const Tick tXP;
    const Tick tXS;
    const Tick clkResyncDelay;
    const bool dataClockSync;
    const bool burstInterleave;
    const uint8_t twoCycleActivate;
    const uint32_t activationLimit;
    const Tick wrToRdDlySameBG;
    const Tick rdToWrDlySameBG;
 
 
    enums::PageManage pageMgmt;
    const uint32_t maxAccessesPerRow;
 
    // timestamp offset
    uint64_t timeStampOffset;
 
    // Holds the value of the DRAM rank of burst issued
    uint8_t activeRank;
 
    bool enableDRAMPowerdown;
 
    Tick lastStatsResetTick;
 
    void activateBank(Rank& rank_ref, Bank& bank_ref, Tick act_tick,
                      uint32_t row);
 
    void prechargeBank(Rank& rank_ref, Bank& bank_ref,
                       Tick pre_tick, bool auto_or_preall = false,
                       bool trace = true);
 
    struct DRAMStats : public statistics::Group
    {
        DRAMStats(DRAMInterface &dram);
 
        void regStats() override;
        void resetStats() override;
 
        DRAMInterface &dram;
 
        statistics::Scalar readBursts;
        statistics::Scalar writeBursts;
 
        statistics::Vector perBankRdBursts;
        statistics::Vector perBankWrBursts;
 
        // Latencies summed over all requests
        statistics::Scalar totQLat;
        statistics::Scalar totBusLat;
        statistics::Scalar totMemAccLat;
 
        // Average latencies per request
        statistics::Formula avgQLat;
        statistics::Formula avgBusLat;
        statistics::Formula avgMemAccLat;
 
        // Row hit count and rate
        statistics::Scalar readRowHits;
        statistics::Scalar writeRowHits;
        statistics::Formula readRowHitRate;
        statistics::Formula writeRowHitRate;
        statistics::Histogram bytesPerActivate;
        // Number of bytes transferred to/from DRAM
        statistics::Scalar dramBytesRead;
        statistics::Scalar dramBytesWritten;
 
        // Average bandwidth
        statistics::Formula avgRdBW;
        statistics::Formula avgWrBW;
        statistics::Formula peakBW;
        // bus utilization
        statistics::Formula busUtil;
        statistics::Formula busUtilRead;
        statistics::Formula busUtilWrite;
        statistics::Formula pageHitRate;
    };
 
    DRAMStats stats;
 
    std::vector<Rank*> ranks;
 
    /*
     * @return delay between write and read commands
     */
    Tick writeToReadDelay() const override { return tBURST + tWTR + tWL; }
 
    std::pair<std::vector<uint32_t>, bool>
    minBankPrep(const MemPacketQueue& queue, Tick min_col_at) const;
 
    /*
     * @return time to send a burst of data without gaps
     */
    Tick
    burstDelay() const
    {
        return (burstInterleave ? tBURST_MAX / 2 : tBURST);
    }
 
  public:
    void init() override;
 
    void startup() override;
 
    void setupRank(const uint8_t rank, const bool is_read) override;
 
    MemPacket* decodePacket(const PacketPtr pkt, Addr pkt_addr,
                           unsigned int size, bool is_read,
                           uint8_t pseudo_channel = 0) override;
 
    void drainRanks() override;
 
    bool allRanksDrained() const override;
 
    void suspend() override;
 
    /*
     * @return time to offset next command
     */
    Tick commandOffset() const override
    {
        return (tRP + std::max(tRCD_RD, tRCD_WR));
    }
 
    /*
     * Function to calulate unloaded, closed bank access latency
     */
    Tick accessLatency() const override { return (tRP + tRCD_RD + tRL); }
 
    std::pair<MemPacketQueue::iterator, Tick>
    chooseNextFRFCFS(MemPacketQueue& queue, Tick min_col_at) const override;
 
    std::pair<Tick, Tick>
    doBurstAccess(MemPacket* mem_pkt, Tick next_burst_at,
                  const std::vector<MemPacketQueue>& queue) override;
 
    bool
    burstReady(MemPacket* pkt) const override
    {
        return ranks[pkt->rank]->inRefIdleState();
    }
 
    bool isBusy(bool read_queue_empty, bool all_writes_nvm) override;
 
    void addRankToRankDelay(Tick cmd_at) override;
 
    void respondEvent(uint8_t rank) override;
 
    void checkRefreshState(uint8_t rank) override;
 
    bool readsWaitingToIssue() const override { return false;}
    void chooseRead(MemPacketQueue& queue) override { }
    bool writeRespQueueFull() const override { return false;}
 
    DRAMInterface(const DRAMInterfaceParams &_p);
};
 
} // namespace memory
} // namespace gem5
 
#endif //__DRAM_INTERFACE_HH__