gem5  v21.1.0.2
Classes | Public Member Functions | Protected Member Functions | Private Member Functions | Private Attributes | List of all members
gem5::memory::MemCtrl Class Reference

The memory controller is a single-channel memory controller capturing the most important timing constraints associated with a contemporary controller. More...

#include <mem_ctrl.hh>

Inheritance diagram for gem5::memory::MemCtrl:
gem5::memory::qos::MemCtrl gem5::ClockedObject gem5::SimObject gem5::Clocked gem5::EventManager gem5::Serializable gem5::Drainable gem5::statistics::Group gem5::Named

Classes

struct  CtrlStats
 
class  MemoryPort
 

Public Member Functions

 MemCtrl (const MemCtrlParams &p)
 
bool allIntfDrained () const
 Ensure that all interfaced have drained commands. More...
 
DrainState drain () override
 Draining is the process of clearing out the states of SimObjects.These are the SimObjects that are partially executed or are partially in flight. More...
 
Tick verifySingleCmd (Tick cmd_tick, Tick max_cmds_per_burst)
 Check for command bus contention for single cycle command. More...
 
Tick verifyMultiCmd (Tick cmd_tick, Tick max_cmds_per_burst, Tick max_multi_cmd_split=0)
 Check for command bus contention for multi-cycle (2 currently) command. More...
 
bool respondEventScheduled () const
 Is there a respondEvent scheduled? More...
 
bool requestEventScheduled () const
 Is there a read/write burst Event scheduled? More...
 
void restartScheduler (Tick tick)
 restart the controller This can be used by interfaces to restart the scheduler after maintainence commands complete More...
 
bool inReadBusState (bool next_state) const
 Check the current direction of the memory channel. More...
 
bool inWriteBusState (bool next_state) const
 Check the current direction of the memory channel. More...
 
PortgetPort (const std::string &if_name, PortID idx=InvalidPortID) override
 Get a port with a given name and index. More...
 
virtual void init () override
 init() is called after all C++ SimObjects have been created and all ports are connected. More...
 
virtual void startup () override
 startup() is the final initialization call before simulation. More...
 
virtual void drainResume () override
 Resume execution after a successful drain. More...
 
- Public Member Functions inherited from gem5::memory::qos::MemCtrl
 MemCtrl (const QoSMemCtrlParams &)
 QoS Memory base class. More...
 
virtual ~MemCtrl ()
 
BusState getBusState () const
 Gets the current bus state. More...
 
BusState getBusStateNext () const
 Gets the next bus state. More...
 
bool hasRequestor (RequestorID id) const
 hasRequestor returns true if the selected requestor(ID) has been registered in the memory controller, which happens if the memory controller has received at least a packet from that requestor. More...
 
uint64_t getReadQueueSize (const uint8_t prio) const
 Gets a READ queue size. More...
 
uint64_t getWriteQueueSize (const uint8_t prio) const
 Gets a WRITE queue size. More...
 
uint64_t getTotalReadQueueSize () const
 Gets the total combined READ queues size. More...
 
uint64_t getTotalWriteQueueSize () const
 Gets the total combined WRITE queues size. More...
 
Tick getServiceTick (const uint8_t prio) const
 Gets the last service tick related to a QoS Priority. More...
 
uint8_t numPriorities () const
 Gets the total number of priority levels in the QoS memory controller. More...
 
Systemsystem () const
 read the system pointer More...
 
- Public Member Functions inherited from gem5::ClockedObject
 ClockedObject (const ClockedObjectParams &p)
 
void serialize (CheckpointOut &cp) const override
 Serialize an object. More...
 
void unserialize (CheckpointIn &cp) override
 Unserialize an object. More...
 
- Public Member Functions inherited from gem5::SimObject
const Paramsparams () const
 
 SimObject (const Params &p)
 
virtual ~SimObject ()
 
virtual void loadState (CheckpointIn &cp)
 loadState() is called on each SimObject when restoring from a checkpoint. More...
 
virtual void initState ()
 initState() is called on each SimObject when not restoring from a checkpoint. More...
 
virtual void regProbePoints ()
 Register probe points for this object. More...
 
virtual void regProbeListeners ()
 Register probe listeners for this object. More...
 
ProbeManagergetProbeManager ()
 Get the probe manager for this object. More...
 
DrainState drain () override
 Provide a default implementation of the drain interface for objects that don't need draining. More...
 
virtual void memWriteback ()
 Write back dirty buffers to memory using functional writes. More...
 
virtual void memInvalidate ()
 Invalidate the contents of memory buffers. More...
 
void serialize (CheckpointOut &cp) const override
 Serialize an object. More...
 
void unserialize (CheckpointIn &cp) override
 Unserialize an object. More...
 
- Public Member Functions inherited from gem5::EventManager
EventQueueeventQueue () const
 
void schedule (Event &event, Tick when)
 
void deschedule (Event &event)
 
void reschedule (Event &event, Tick when, bool always=false)
 
void schedule (Event *event, Tick when)
 
void deschedule (Event *event)
 
void reschedule (Event *event, Tick when, bool always=false)
 
void wakeupEventQueue (Tick when=(Tick) -1)
 This function is not needed by the usual gem5 event loop but may be necessary in derived EventQueues which host gem5 on other schedulers. More...
 
void setCurTick (Tick newVal)
 
 EventManager (EventManager &em)
 Event manger manages events in the event queue. More...
 
 EventManager (EventManager *em)
 
 EventManager (EventQueue *eq)
 
- Public Member Functions inherited from gem5::Serializable
 Serializable ()
 
virtual ~Serializable ()
 
void serializeSection (CheckpointOut &cp, const char *name) const
 Serialize an object into a new section. More...
 
void serializeSection (CheckpointOut &cp, const std::string &name) const
 
void unserializeSection (CheckpointIn &cp, const char *name)
 Unserialize an a child object. More...
 
void unserializeSection (CheckpointIn &cp, const std::string &name)
 
- Public Member Functions inherited from gem5::Drainable
DrainState drainState () const
 Return the current drain state of an object. More...
 
virtual void notifyFork ()
 Notify a child process of a fork. More...
 
- Public Member Functions inherited from gem5::statistics::Group
 Group (Group *parent, const char *name=nullptr)
 Construct a new statistics group. More...
 
virtual ~Group ()
 
virtual void regStats ()
 Callback to set stat parameters. More...
 
virtual void resetStats ()
 Callback to reset stats. More...
 
virtual void preDumpStats ()
 Callback before stats are dumped. More...
 
void addStat (statistics::Info *info)
 Register a stat with this group. More...
 
const std::map< std::string, Group * > & getStatGroups () const
 Get all child groups associated with this object. More...
 
const std::vector< Info * > & getStats () const
 Get all stats associated with this object. More...
 
void addStatGroup (const char *name, Group *block)
 Add a stat block as a child of this block. More...
 
const InforesolveStat (std::string name) const
 Resolve a stat by its name within this group. More...
 
void mergeStatGroup (Group *block)
 Merge the contents (stats & children) of a block to this block. More...
 
 Group ()=delete
 
 Group (const Group &)=delete
 
Groupoperator= (const Group &)=delete
 
- Public Member Functions inherited from gem5::Named
 Named (const std::string &name_)
 
virtual ~Named ()=default
 
virtual std::string name () const
 
- Public Member Functions inherited from gem5::Clocked
void updateClockPeriod ()
 Update the tick to the current tick. More...
 
Tick clockEdge (Cycles cycles=Cycles(0)) const
 Determine the tick when a cycle begins, by default the current one, but the argument also enables the caller to determine a future cycle. More...
 
Cycles curCycle () const
 Determine the current cycle, corresponding to a tick aligned to a clock edge. More...
 
Tick nextCycle () const
 Based on the clock of the object, determine the start tick of the first cycle that is at least one cycle in the future. More...
 
uint64_t frequency () const
 
Tick clockPeriod () const
 
double voltage () const
 
Cycles ticksToCycles (Tick t) const
 
Tick cyclesToTicks (Cycles c) const
 

Protected Member Functions

Tick recvAtomic (PacketPtr pkt)
 
Tick recvAtomicBackdoor (PacketPtr pkt, MemBackdoorPtr &backdoor)
 
void recvFunctional (PacketPtr pkt)
 
bool recvTimingReq (PacketPtr pkt)
 
- Protected Member Functions inherited from gem5::memory::qos::MemCtrl
void addRequestor (const RequestorID id)
 Initializes dynamically counters and statistics for a given Requestor. More...
 
void logRequest (BusState dir, RequestorID id, uint8_t _qos, Addr addr, uint64_t entries)
 Called upon receiving a request or updates statistics and updates queues status. More...
 
void logResponse (BusState dir, RequestorID id, uint8_t _qos, Addr addr, uint64_t entries, double delay)
 Called upon receiving a response, updates statistics and updates queues status. More...
 
template<typename Queues >
uint8_t qosSchedule (std::initializer_list< Queues * > queues_ptr, uint64_t queue_entry_size, const PacketPtr pkt)
 Assign priority to a packet by executing the configured QoS policy. More...
 
uint8_t schedule (RequestorID id, uint64_t data)
 
uint8_t schedule (const PacketPtr pkt)
 
BusState selectNextBusState ()
 Returns next bus direction (READ or WRITE) based on configured policy. More...
 
void setCurrentBusState ()
 Set current bus direction (READ or WRITE) from next selected one. More...
 
void recordTurnaroundStats ()
 Record statistics on turnarounds based on busStateNext and busState values. More...
 
template<typename Queues >
void escalate (std::initializer_list< Queues * > queues, uint64_t queue_entry_size, RequestorID id, uint8_t tgt_prio)
 Escalates/demotes priority of all packets belonging to the passed requestor to given priority value. More...
 
template<typename Queues >
void escalateQueues (Queues &queues, uint64_t queue_entry_size, RequestorID id, uint8_t curr_prio, uint8_t tgt_prio)
 Escalates/demotes priority of all packets belonging to the passed requestor to given priority value in a specified cluster of queues (e.g. More...
 
- Protected Member Functions inherited from gem5::Drainable
 Drainable ()
 
virtual ~Drainable ()
 
void signalDrainDone () const
 Signal that an object is drained. More...
 
- Protected Member Functions inherited from gem5::Clocked
 Clocked (ClockDomain &clk_domain)
 Create a clocked object and set the clock domain based on the parameters. More...
 
 Clocked (Clocked &)=delete
 
Clockedoperator= (Clocked &)=delete
 
virtual ~Clocked ()
 Virtual destructor due to inheritance. More...
 
void resetClock () const
 Reset the object's clock using the current global tick value. More...
 
virtual void clockPeriodUpdated ()
 A hook subclasses can implement so they can do any extra work that's needed when the clock rate is changed. More...
 

Private Member Functions

void processNextReqEvent ()
 Bunch of things requires to setup "events" in gem5 When event "respondEvent" occurs for example, the method processRespondEvent is called; no parameters are allowed in these methods. More...
 
void processRespondEvent ()
 
bool readQueueFull (unsigned int pkt_count) const
 Check if the read queue has room for more entries. More...
 
bool writeQueueFull (unsigned int pkt_count) const
 Check if the write queue has room for more entries. More...
 
void addToReadQueue (PacketPtr pkt, unsigned int pkt_count, bool is_dram)
 When a new read comes in, first check if the write q has a pending request to the same address. If not, decode the address to populate rank/bank/row, create one or mutliple "mem_pkt", and push them to the back of the read queue. More...
 
void addToWriteQueue (PacketPtr pkt, unsigned int pkt_count, bool is_dram)
 Decode the incoming pkt, create a mem_pkt and push to the back of the write queue. More...
 
void doBurstAccess (MemPacket *mem_pkt)
 Actually do the burst based on media specific access function. More...
 
void accessAndRespond (PacketPtr pkt, Tick static_latency)
 When a packet reaches its "readyTime" in the response Q, use the "access()" method in AbstractMemory to actually create the response packet, and send it back to the outside world requestor. More...
 
bool packetReady (MemPacket *pkt)
 Determine if there is a packet that can issue. More...
 
Tick minReadToWriteDataGap ()
 Calculate the minimum delay used when scheduling a read-to-write transision. More...
 
Tick minWriteToReadDataGap ()
 Calculate the minimum delay used when scheduling a write-to-read transision. More...
 
MemPacketQueue::iterator chooseNext (MemPacketQueue &queue, Tick extra_col_delay)
 The memory schduler/arbiter - picks which request needs to go next, based on the specified policy such as FCFS or FR-FCFS and moves it to the head of the queue. More...
 
MemPacketQueue::iterator chooseNextFRFCFS (MemPacketQueue &queue, Tick extra_col_delay)
 For FR-FCFS policy reorder the read/write queue depending on row buffer hits and earliest bursts available in memory. More...
 
Tick getBurstWindow (Tick cmd_tick)
 Calculate burst window aligned tick. More...
 
void printQs () const
 Used for debugging to observe the contents of the queues. More...
 
Addr burstAlign (Addr addr, bool is_dram) const
 Burst-align an address. More...
 
std::vector< MemPacketQueue > & selQueue (bool is_read)
 Select either the read or write queue. More...
 
void pruneBurstTick ()
 Remove commands that have already issued from burstTicks. More...
 

Private Attributes

MemoryPort port
 Our incoming port, for a multi-ported controller add a crossbar in front of it. More...
 
bool isTimingMode
 Remember if the memory system is in timing mode. More...
 
bool retryRdReq
 Remember if we have to retry a request when available. More...
 
bool retryWrReq
 
EventFunctionWrapper nextReqEvent
 
EventFunctionWrapper respondEvent
 
std::vector< MemPacketQueuereadQueue
 The controller's main read and write queues, with support for QoS reordering. More...
 
std::vector< MemPacketQueuewriteQueue
 
std::unordered_set< AddrisInWriteQueue
 To avoid iterating over the write queue to check for overlapping transactions, maintain a set of burst addresses that are currently queued. More...
 
std::deque< MemPacket * > respQueue
 Response queue where read packets wait after we're done working with them, but it's not time to send the response yet. More...
 
std::unordered_multiset< TickburstTicks
 Holds count of commands issued in burst window starting at defined Tick. More...
 
DRAMInterface *const dram
 Create pointer to interface of the actual dram media when connected. More...
 
NVMInterface *const nvm
 Create pointer to interface of the actual nvm media when connected. More...
 
const uint32_t readBufferSize
 The following are basic design parameters of the memory controller, and are initialized based on parameter values. More...
 
const uint32_t writeBufferSize
 
const uint32_t writeHighThreshold
 
const uint32_t writeLowThreshold
 
const uint32_t minWritesPerSwitch
 
uint32_t writesThisTime
 
uint32_t readsThisTime
 
enums::MemSched memSchedPolicy
 Memory controller configuration initialized based on parameter values. More...
 
const Tick frontendLatency
 Pipeline latency of the controller frontend. More...
 
const Tick backendLatency
 Pipeline latency of the backend and PHY. More...
 
const Tick commandWindow
 Length of a command window, used to check command bandwidth. More...
 
Tick nextBurstAt
 Till when must we wait before issuing next RD/WR burst? More...
 
Tick prevArrival
 
Tick nextReqTime
 The soonest you have to start thinking about the next request is the longest access time that can occur before nextBurstAt. More...
 
CtrlStats stats
 
std::unique_ptr< PacketpendingDelete
 Upstream caches need this packet until true is returned, so hold it for deletion until a subsequent call. More...
 

Additional Inherited Members

- Public Types inherited from gem5::memory::qos::MemCtrl
enum  BusState { READ, WRITE }
 Bus Direction. More...
 
- Public Types inherited from gem5::ClockedObject
using Params = ClockedObjectParams
 Parameters of ClockedObject. More...
 
- Public Types inherited from gem5::SimObject
typedef SimObjectParams Params
 
- Static Public Member Functions inherited from gem5::SimObject
static void serializeAll (const std::string &cpt_dir)
 Create a checkpoint by serializing all SimObjects in the system. More...
 
static SimObjectfind (const char *name)
 Find the SimObject with the given name and return a pointer to it. More...
 
static void setSimObjectResolver (SimObjectResolver *resolver)
 There is a single object name resolver, and it is only set when simulation is restoring from checkpoints. More...
 
static SimObjectResolvergetSimObjectResolver ()
 There is a single object name resolver, and it is only set when simulation is restoring from checkpoints. More...
 
- Static Public Member Functions inherited from gem5::Serializable
static const std::string & currentSection ()
 Gets the fully-qualified name of the active section. More...
 
static void generateCheckpointOut (const std::string &cpt_dir, std::ofstream &outstream)
 Generate a checkpoint file so that the serialization can be routed to it. More...
 
- Public Attributes inherited from gem5::ClockedObject
PowerStatepowerState
 
- Protected Attributes inherited from gem5::memory::qos::MemCtrl
const std::unique_ptr< Policypolicy
 QoS Policy, assigns QoS priority to the incoming packets. More...
 
const std::unique_ptr< TurnaroundPolicyturnPolicy
 QoS Bus Turnaround Policy: selects the bus direction (READ/WRITE) More...
 
const std::unique_ptr< QueuePolicyqueuePolicy
 QoS Queue Policy: selects packet among same-priority queue. More...
 
const uint8_t _numPriorities
 Number of configured QoS priorities. More...
 
const bool qosPriorityEscalation
 Enables QoS priority escalation. More...
 
const bool qosSyncroScheduler
 Enables QoS synchronized scheduling invokes the QoS scheduler on all requestors, at every packet arrival. More...
 
std::unordered_map< RequestorID, const std::string > requestors
 Hash of requestor ID - requestor name. More...
 
std::unordered_map< RequestorID, std::vector< uint64_t > > packetPriorities
 Hash of requestors - number of packets queued per priority. More...
 
std::unordered_map< RequestorID, std::unordered_map< uint64_t, std::deque< uint64_t > > > requestTimes
 Hash of requestors - address of request - queue of times of request. More...
 
std::vector< TickserviceTick
 Vector of QoS priorities/last service time. More...
 
std::vector< uint64_t > readQueueSizes
 Read request packets queue length in #packets, per QoS priority. More...
 
std::vector< uint64_t > writeQueueSizes
 Write request packets queue length in #packets, per QoS priority. More...
 
uint64_t totalReadQueueSize
 Total read request packets queue length in #packets. More...
 
uint64_t totalWriteQueueSize
 Total write request packets queue length in #packets. More...
 
BusState busState
 Bus state used to control the read/write switching and drive the scheduling of the next request. More...
 
BusState busStateNext
 bus state for next request event triggered More...
 
gem5::memory::qos::MemCtrl::MemCtrlStats stats
 
System_system
 Pointer to the System object. More...
 
- Protected Attributes inherited from gem5::SimObject
const SimObjectParams & _params
 Cached copy of the object parameters. More...
 
- Protected Attributes inherited from gem5::EventManager
EventQueueeventq
 A pointer to this object's event queue. More...
 

Detailed Description

The memory controller is a single-channel memory controller capturing the most important timing constraints associated with a contemporary controller.

For multi-channel memory systems, the controller is combined with a crossbar model, with the channel address interleaving taking part in the crossbar.

As a basic design principle, this controller model is not cycle callable, but instead uses events to: 1) decide when new decisions can be made, 2) when resources become available, 3) when things are to be considered done, and 4) when to send things back. The controller interfaces to media specific interfaces to enable flexible topoloties. Through these simple principles, the model delivers high performance, and lots of flexibility, allowing users to evaluate the system impact of a wide range of memory technologies.

For more details, please see Hansson et al, "Simulating DRAM controllers for future system architecture exploration", Proc. ISPASS, 2014. If you use this model as part of your research please cite the paper.

Definition at line 242 of file mem_ctrl.hh.

Constructor & Destructor Documentation

◆ MemCtrl()

gem5::memory::MemCtrl::MemCtrl ( const MemCtrlParams &  p)

Definition at line 58 of file mem_ctrl.cc.

References processNextReqEvent().

Member Function Documentation

◆ accessAndRespond()

void gem5::memory::MemCtrl::accessAndRespond ( PacketPtr  pkt,
Tick  static_latency 
)
private

When a packet reaches its "readyTime" in the response Q, use the "access()" method in AbstractMemory to actually create the response packet, and send it back to the outside world requestor.

Parameters
pktThe packet from the outside world
static_latencyStatic latency to add before sending the packet

Definition at line 639 of file mem_ctrl.cc.

References gem5::memory::AbstractMemory::access(), gem5::AddrRange::contains(), gem5::curTick(), DPRINTF, dram, gem5::Packet::getAddr(), gem5::memory::AbstractMemory::getAddrRange(), gem5::Packet::headerDelay, gem5::Packet::isResponse(), gem5::Packet::needsResponse(), nvm, panic, gem5::Packet::payloadDelay, pendingDelete, port, gem5::Packet::print(), and gem5::QueuedResponsePort::schedTimingResp().

Referenced by addToReadQueue(), addToWriteQueue(), and processRespondEvent().

◆ addToReadQueue()

void gem5::memory::MemCtrl::addToReadQueue ( PacketPtr  pkt,
unsigned int  pkt_count,
bool  is_dram 
)
private

When a new read comes in, first check if the write q has a pending request to the same address. If not, decode the address to populate rank/bank/row, create one or mutliple "mem_pkt", and push them to the back of the read queue.

\ If this is the only read request in the system, schedule an event to start servicing it.

Parameters
pktThe request packet from the outside world
pkt_countThe number of memory bursts the pkt
is_dramDoes this packet access DRAM? translate to. If pkt size is larger then one full burst, then pkt_count is greater than one.

Definition at line 197 of file mem_ctrl.cc.

References accessAndRespond(), gem5::X86ISA::addr, gem5::memory::MemPacket::addr, gem5::memory::MemCtrl::CtrlStats::avgRdQLen, burstAlign(), gem5::memory::MemPacket::burstHelper, gem5::memory::BurstHelper::burstsServiced, gem5::memory::MemInterface::bytesPerBurst(), gem5::memory::MemCtrl::CtrlStats::bytesReadWrQ, gem5::ceilLog2(), gem5::curTick(), gem5::memory::MemInterface::decodePacket(), DPRINTF, dram, frontendLatency, gem5::Packet::getAddr(), gem5::Packet::getSize(), isInWriteQueue, gem5::Packet::isWrite(), gem5::memory::qos::MemCtrl::logRequest(), gem5::MaxTick, nextReqEvent, nvm, gem5::MipsISA::p, gem5::memory::MemPacket::qosValue(), gem5::Packet::qosValue(), gem5::memory::MemPacket::rank, gem5::memory::MemCtrl::CtrlStats::rdQLenPdf, gem5::memory::qos::MemCtrl::READ, gem5::memory::MemCtrl::CtrlStats::readBursts, gem5::memory::MemCtrl::CtrlStats::readPktSize, readQueue, readQueueFull(), gem5::memory::MemPacket::readyTime, gem5::Packet::requestorId(), gem5::memory::MemCtrl::CtrlStats::requestorReadAccesses, respQueue, gem5::memory::qos::MemCtrl::schedule(), gem5::Event::scheduled(), gem5::memory::MemCtrl::CtrlStats::servicedByWrQ, gem5::memory::DRAMInterface::setupRank(), gem5::memory::NVMInterface::setupRank(), stats, gem5::memory::qos::MemCtrl::totalReadQueueSize, gem5::PowerISA::vec, and writeQueue.

Referenced by recvTimingReq().

◆ addToWriteQueue()

void gem5::memory::MemCtrl::addToWriteQueue ( PacketPtr  pkt,
unsigned int  pkt_count,
bool  is_dram 
)
private

Decode the incoming pkt, create a mem_pkt and push to the back of the write queue.

\If the write q length is more than the threshold specified by the user, ie the queue is beginning to get full, stop reads, and start draining writes.

Parameters
pktThe request packet from the outside world
pkt_countThe number of memory bursts the pkt
is_dramDoes this packet access DRAM? translate to. If pkt size is larger then one full burst, then pkt_count is greater than one.

Definition at line 316 of file mem_ctrl.cc.

References accessAndRespond(), gem5::X86ISA::addr, gem5::memory::MemPacket::addr, gem5::memory::MemCtrl::CtrlStats::avgWrQLen, burstAlign(), gem5::memory::MemInterface::bytesPerBurst(), gem5::ceilLog2(), gem5::curTick(), gem5::memory::MemInterface::decodePacket(), DPRINTF, dram, frontendLatency, gem5::Packet::getAddr(), gem5::Packet::getSize(), isInWriteQueue, gem5::Packet::isWrite(), gem5::memory::qos::MemCtrl::logRequest(), gem5::memory::MemCtrl::CtrlStats::mergedWrBursts, nextReqEvent, nvm, gem5::memory::MemPacket::qosValue(), gem5::Packet::qosValue(), gem5::memory::MemPacket::rank, gem5::Packet::requestorId(), gem5::memory::MemCtrl::CtrlStats::requestorWriteAccesses, gem5::memory::qos::MemCtrl::schedule(), gem5::Event::scheduled(), gem5::memory::DRAMInterface::setupRank(), gem5::memory::NVMInterface::setupRank(), stats, gem5::memory::qos::MemCtrl::totalWriteQueueSize, gem5::memory::qos::MemCtrl::WRITE, writeBufferSize, gem5::memory::MemCtrl::CtrlStats::writeBursts, gem5::memory::MemCtrl::CtrlStats::writePktSize, writeQueue, and gem5::memory::MemCtrl::CtrlStats::wrQLenPdf.

Referenced by recvTimingReq().

◆ allIntfDrained()

bool gem5::memory::MemCtrl::allIntfDrained ( ) const

Ensure that all interfaced have drained commands.

Returns
bool flag, set once drain complete

Definition at line 1409 of file mem_ctrl.cc.

References gem5::memory::DRAMInterface::allRanksDrained(), gem5::memory::NVMInterface::allRanksDrained(), dram, and nvm.

Referenced by drain(), processNextReqEvent(), and processRespondEvent().

◆ burstAlign()

Addr gem5::memory::MemCtrl::burstAlign ( Addr  addr,
bool  is_dram 
) const
private

Burst-align an address.

Parameters
addrThe potentially unaligned address
is_dramDoes this packet access DRAM?
Returns
An address aligned to a memory burst

Definition at line 1183 of file mem_ctrl.cc.

References gem5::X86ISA::addr, gem5::memory::MemInterface::bytesPerBurst(), dram, and nvm.

Referenced by addToReadQueue(), addToWriteQueue(), and processNextReqEvent().

◆ chooseNext()

MemPacketQueue::iterator gem5::memory::MemCtrl::chooseNext ( MemPacketQueue queue,
Tick  extra_col_delay 
)
private

The memory schduler/arbiter - picks which request needs to go next, based on the specified policy such as FCFS or FR-FCFS and moves it to the head of the queue.

Prioritizes accesses to the same rank as previous burst unless controller is switching command type.

Parameters
queueQueued requests to consider
extra_col_delayAny extra delay due to a read/write switch
Returns
an iterator to the selected packet, else queue.end()

Definition at line 562 of file mem_ctrl.cc.

References chooseNextFRFCFS(), DPRINTF, gem5::ArmISA::i, memSchedPolicy, packetReady(), and panic.

Referenced by processNextReqEvent().

◆ chooseNextFRFCFS()

MemPacketQueue::iterator gem5::memory::MemCtrl::chooseNextFRFCFS ( MemPacketQueue queue,
Tick  extra_col_delay 
)
private

For FR-FCFS policy reorder the read/write queue depending on row buffer hits and earliest bursts available in memory.

Parameters
queueQueued requests to consider
extra_col_delayAny extra delay due to a read/write switch
Returns
an iterator to the selected packet, else queue.end()

Definition at line 597 of file mem_ctrl.cc.

References gem5::memory::DRAMInterface::chooseNextFRFCFS(), gem5::memory::NVMInterface::chooseNextFRFCFS(), gem5::curTick(), DPRINTF, dram, gem5::MaxTick, nextBurstAt, and nvm.

Referenced by chooseNext().

◆ doBurstAccess()

void gem5::memory::MemCtrl::doBurstAccess ( MemPacket mem_pkt)
private

◆ drain()

DrainState gem5::memory::MemCtrl::drain ( )
overridevirtual

Draining is the process of clearing out the states of SimObjects.These are the SimObjects that are partially executed or are partially in flight.

Draining is mostly used before forking and creating a check point.

This function notifies an object that it needs to drain its state.

If the object does not need further simulation to drain internal buffers, it returns DrainState::Drained and automatically switches to the Drained state. If the object needs more simulation, it returns DrainState::Draining and automatically enters the Draining state. Other return values are invalid.

Note
An object that has entered the Drained state can be disturbed by other objects in the system and consequently stop being drained. These perturbations are not visible in the drain state. The simulator therefore repeats the draining process until all objects return DrainState::Drained on the first call to drain().
Returns
DrainState::Drained if the object is drained at this point in time, DrainState::Draining if it needs further simulation.

Implements gem5::Drainable.

Definition at line 1420 of file mem_ctrl.cc.

References allIntfDrained(), gem5::curTick(), DPRINTF, gem5::Drained, gem5::Draining, gem5::memory::DRAMInterface::drainRanks(), dram, nextReqEvent, respQueue, gem5::memory::qos::MemCtrl::schedule(), gem5::Event::scheduled(), gem5::memory::qos::MemCtrl::totalReadQueueSize, and gem5::memory::qos::MemCtrl::totalWriteQueueSize.

◆ drainResume()

void gem5::memory::MemCtrl::drainResume ( )
overridevirtual

◆ getBurstWindow()

Tick gem5::memory::MemCtrl::getBurstWindow ( Tick  cmd_tick)
private

Calculate burst window aligned tick.

Parameters
cmd_tickInitial tick of command
Returns
burst window aligned tick

Definition at line 696 of file mem_ctrl.cc.

References commandWindow.

Referenced by verifyMultiCmd(), and verifySingleCmd().

◆ getPort()

Port & gem5::memory::MemCtrl::getPort ( const std::string &  if_name,
PortID  idx = InvalidPortID 
)
overridevirtual

Get a port with a given name and index.

This is used at binding time and returns a reference to a protocol-agnostic port.

gem5 has a request and response port interface. All memory objects are connected together via ports. These ports provide a rigid interface between these memory objects. These ports implement three different memory system modes: timing, atomic, and functional. The most important mode is the timing mode and here timing mode is used for conducting cycle-level timing experiments. The other modes are only used in special circumstances and should not be used to conduct cycle-level timing experiments. The other modes are only used in special circumstances. These ports allow SimObjects to communicate with each other.

Parameters
if_namePort name
idxIndex in the case of a VectorPort
Returns
A reference to the given port

Reimplemented from gem5::SimObject.

Definition at line 1399 of file mem_ctrl.cc.

References gem5::SimObject::getPort(), and port.

◆ init()

void gem5::memory::MemCtrl::init ( )
overridevirtual

init() is called after all C++ SimObjects have been created and all ports are connected.

Initializations that are independent of unserialization but rely on a fully instantiated and connected SimObject graph should be done here.

Reimplemented from gem5::SimObject.

Definition at line 101 of file mem_ctrl.cc.

References fatal, gem5::Port::isConnected(), gem5::Named::name(), port, and gem5::ResponsePort::sendRangeChange().

◆ inReadBusState()

bool gem5::memory::MemCtrl::inReadBusState ( bool  next_state) const

Check the current direction of the memory channel.

Parameters
next_stateCheck either the current or next bus state
Returns
True when bus is currently in a read state

Definition at line 791 of file mem_ctrl.cc.

References gem5::memory::qos::MemCtrl::busState, gem5::memory::qos::MemCtrl::busStateNext, and gem5::memory::qos::MemCtrl::READ.

Referenced by gem5::memory::NVMInterface::burstReady(), gem5::memory::NVMInterface::isBusy(), and gem5::memory::DRAMInterface::minBankPrep().

◆ inWriteBusState()

bool gem5::memory::MemCtrl::inWriteBusState ( bool  next_state) const

Check the current direction of the memory channel.

Parameters
next_stateCheck either the current or next bus state
Returns
True when bus is currently in a write state

Definition at line 804 of file mem_ctrl.cc.

References gem5::memory::qos::MemCtrl::busState, gem5::memory::qos::MemCtrl::busStateNext, and gem5::memory::qos::MemCtrl::WRITE.

◆ minReadToWriteDataGap()

Tick gem5::memory::MemCtrl::minReadToWriteDataGap ( )
private

Calculate the minimum delay used when scheduling a read-to-write transision.

Parameters
returnminimum delay

Definition at line 1167 of file mem_ctrl.cc.

References dram, gem5::MaxTick, gem5::memory::MemInterface::minReadToWriteDataGap(), and nvm.

Referenced by processNextReqEvent().

◆ minWriteToReadDataGap()

Tick gem5::memory::MemCtrl::minWriteToReadDataGap ( )
private

Calculate the minimum delay used when scheduling a write-to-read transision.

Parameters
returnminimum delay

Definition at line 1175 of file mem_ctrl.cc.

References dram, gem5::MaxTick, gem5::memory::MemInterface::minWriteToReadDataGap(), and nvm.

Referenced by processNextReqEvent().

◆ packetReady()

bool gem5::memory::MemCtrl::packetReady ( MemPacket pkt)
private

Determine if there is a packet that can issue.

Parameters
pktThe packet to evaluate

Definition at line 1160 of file mem_ctrl.cc.

References gem5::memory::DRAMInterface::burstReady(), gem5::memory::NVMInterface::burstReady(), dram, gem5::memory::MemPacket::isDram(), and nvm.

Referenced by chooseNext().

◆ printQs()

void gem5::memory::MemCtrl::printQs ( ) const
private

Used for debugging to observe the contents of the queues.

Definition at line 397 of file mem_ctrl.cc.

References DPRINTF, readQueue, respQueue, and writeQueue.

◆ processNextReqEvent()

void gem5::memory::MemCtrl::processNextReqEvent ( )
private

Bunch of things requires to setup "events" in gem5 When event "respondEvent" occurs for example, the method processRespondEvent is called; no parameters are allowed in these methods.

Definition at line 874 of file mem_ctrl.cc.

References allIntfDrained(), burstAlign(), gem5::memory::qos::MemCtrl::busState, gem5::memory::qos::MemCtrl::busStateNext, gem5::memory::MemInterface::bytesPerBurst(), chooseNext(), gem5::memory::NVMInterface::chooseRead(), gem5::curTick(), doBurstAccess(), DPRINTF, gem5::Draining, gem5::Drainable::drainState(), dram, gem5::memory::DRAMInterface::isBusy(), gem5::memory::NVMInterface::isBusy(), isInWriteQueue, gem5::memory::qos::MemCtrl::logResponse(), minReadToWriteDataGap(), minWritesPerSwitch, minWriteToReadDataGap(), nextReqEvent, nextReqTime, gem5::memory::qos::MemCtrl::numPriorities(), gem5::memory::NVMInterface::numWritesQueued, nvm, port, gem5::memory::MemCtrl::CtrlStats::rdPerTurnAround, gem5::memory::qos::MemCtrl::READ, readQueue, readsThisTime, gem5::memory::NVMInterface::readsWaitingToIssue(), gem5::memory::qos::MemCtrl::recordTurnaroundStats(), respondEvent, respQueue, retryWrReq, gem5::statistics::DistBase< Derived, Stor >::sample(), gem5::memory::qos::MemCtrl::schedule(), gem5::Event::scheduled(), gem5::memory::qos::MemCtrl::selectNextBusState(), gem5::ResponsePort::sendRetryReq(), gem5::Drainable::signalDrainDone(), stats, gem5::memory::qos::MemCtrl::totalReadQueueSize, gem5::memory::qos::MemCtrl::totalWriteQueueSize, gem5::memory::qos::MemCtrl::turnPolicy, gem5::memory::qos::MemCtrl::WRITE, writeBufferSize, writeHighThreshold, writeLowThreshold, writeQueue, gem5::memory::NVMInterface::writeRespQueueFull(), writesThisTime, and gem5::memory::MemCtrl::CtrlStats::wrPerTurnAround.

Referenced by MemCtrl().

◆ processRespondEvent()

void gem5::memory::MemCtrl::processRespondEvent ( )
private

◆ pruneBurstTick()

void gem5::memory::MemCtrl::pruneBurstTick ( )
private

Remove commands that have already issued from burstTicks.

Definition at line 683 of file mem_ctrl.cc.

References burstTicks, gem5::curTick(), and DPRINTF.

Referenced by doBurstAccess().

◆ readQueueFull()

bool gem5::memory::MemCtrl::readQueueFull ( unsigned int  pkt_count) const
private

Check if the read queue has room for more entries.

Parameters
pkt_countThe number of entries needed in the read queue
Returns
true if read queue is full, false otherwise

Definition at line 174 of file mem_ctrl.cc.

References DPRINTF, readBufferSize, respQueue, and gem5::memory::qos::MemCtrl::totalReadQueueSize.

Referenced by addToReadQueue(), and recvTimingReq().

◆ recvAtomic()

Tick gem5::memory::MemCtrl::recvAtomic ( PacketPtr  pkt)
protected

◆ recvAtomicBackdoor()

Tick gem5::memory::MemCtrl::recvAtomicBackdoor ( PacketPtr  pkt,
MemBackdoorPtr backdoor 
)
protected

Definition at line 162 of file mem_ctrl.cc.

References dram, gem5::memory::AbstractMemory::getBackdoor(), nvm, and recvAtomic().

◆ recvFunctional()

void gem5::memory::MemCtrl::recvFunctional ( PacketPtr  pkt)
protected

◆ recvTimingReq()

bool gem5::memory::MemCtrl::recvTimingReq ( PacketPtr  pkt)
protected

◆ requestEventScheduled()

bool gem5::memory::MemCtrl::requestEventScheduled ( ) const
inline

Is there a read/write burst Event scheduled?

Returns
true if event is scheduled

Definition at line 675 of file mem_ctrl.hh.

References nextReqEvent, and gem5::Event::scheduled().

Referenced by gem5::memory::NVMInterface::processReadReadyEvent(), and gem5::memory::NVMInterface::processWriteRespondEvent().

◆ respondEventScheduled()

bool gem5::memory::MemCtrl::respondEventScheduled ( ) const
inline

Is there a respondEvent scheduled?

Returns
true if event is scheduled

Definition at line 668 of file mem_ctrl.hh.

References respondEvent, and gem5::Event::scheduled().

◆ restartScheduler()

void gem5::memory::MemCtrl::restartScheduler ( Tick  tick)
inline

restart the controller This can be used by interfaces to restart the scheduler after maintainence commands complete

Parameters
Tickto schedule next event

Definition at line 684 of file mem_ctrl.hh.

References nextReqEvent, gem5::memory::qos::MemCtrl::schedule(), and gem5::Clocked::tick.

Referenced by gem5::memory::NVMInterface::processReadReadyEvent(), and gem5::memory::NVMInterface::processWriteRespondEvent().

◆ selQueue()

std::vector<MemPacketQueue>& gem5::memory::MemCtrl::selQueue ( bool  is_read)
inlineprivate

Select either the read or write queue.

Parameters
is_readThe current burst is a read, select read queue
Returns
a reference to the appropriate queue

Definition at line 608 of file mem_ctrl.hh.

References readQueue, and writeQueue.

Referenced by doBurstAccess().

◆ startup()

void gem5::memory::MemCtrl::startup ( )
overridevirtual

startup() is the final initialization call before simulation.

All state is initialized (including unserialized state, if any, such as the curTick() value), so this is the appropriate place to schedule initial event(s) for objects that need them.

Reimplemented from gem5::SimObject.

Definition at line 111 of file mem_ctrl.cc.

References gem5::memory::DRAMInterface::commandOffset(), gem5::memory::NVMInterface::commandOffset(), gem5::curTick(), dram, gem5::System::isTimingMode(), isTimingMode, nextBurstAt, nvm, and gem5::memory::qos::MemCtrl::system().

Referenced by drainResume().

◆ verifyMultiCmd()

Tick gem5::memory::MemCtrl::verifyMultiCmd ( Tick  cmd_tick,
Tick  max_cmds_per_burst,
Tick  max_multi_cmd_split = 0 
)

Check for command bus contention for multi-cycle (2 currently) command.

If there is contention, shift command(s) to next burst. Check verifies that the commands issued per burst is less than a defined max number, maxCommandsPerWindow. Therefore, contention per cycle is not verified and instead is done based on a burst window.

Parameters
cmd_tickInitial tick of command, to be verified
max_multi_cmd_splitMaximum delay between commands
max_cmds_per_burstNumber of commands that can issue in a burst window
Returns
tick for command issue without contention

Definition at line 727 of file mem_ctrl.cc.

References burstTicks, commandWindow, DPRINTF, and getBurstWindow().

Referenced by gem5::memory::DRAMInterface::activateBank(), gem5::memory::NVMInterface::chooseRead(), gem5::memory::DRAMInterface::doBurstAccess(), and gem5::memory::NVMInterface::doBurstAccess().

◆ verifySingleCmd()

Tick gem5::memory::MemCtrl::verifySingleCmd ( Tick  cmd_tick,
Tick  max_cmds_per_burst 
)

Check for command bus contention for single cycle command.

If there is contention, shift command to next burst. Check verifies that the commands issued per burst is less than a defined max number, maxCommandsPerWindow. Therefore, contention per cycle is not verified and instead is done based on a burst window.

Parameters
cmd_tickInitial tick of command, to be verified
max_cmds_per_burstNumber of commands that can issue in a burst window
Returns
tick for command issue without contention

Definition at line 704 of file mem_ctrl.cc.

References burstTicks, commandWindow, DPRINTF, and getBurstWindow().

Referenced by gem5::memory::DRAMInterface::activateBank(), gem5::memory::NVMInterface::chooseRead(), gem5::memory::DRAMInterface::doBurstAccess(), gem5::memory::NVMInterface::doBurstAccess(), and gem5::memory::DRAMInterface::prechargeBank().

◆ writeQueueFull()

bool gem5::memory::MemCtrl::writeQueueFull ( unsigned int  pkt_count) const
private

Check if the write queue has room for more entries.

Parameters
pkt_countThe number of entries needed in the write queue
Returns
true if write queue is full, false otherwise

Definition at line 186 of file mem_ctrl.cc.

References DPRINTF, gem5::memory::qos::MemCtrl::totalWriteQueueSize, and writeBufferSize.

Referenced by recvTimingReq().

Member Data Documentation

◆ backendLatency

const Tick gem5::memory::MemCtrl::backendLatency
private

Pipeline latency of the backend and PHY.

Along with the frontend contribution, this latency is added to reads serviced by the memory.

Definition at line 511 of file mem_ctrl.hh.

Referenced by processRespondEvent().

◆ burstTicks

std::unordered_multiset<Tick> gem5::memory::MemCtrl::burstTicks
private

Holds count of commands issued in burst window starting at defined Tick.

This is used to ensure that the command bandwidth does not exceed the allowable media constraints.

Definition at line 467 of file mem_ctrl.hh.

Referenced by pruneBurstTick(), verifyMultiCmd(), and verifySingleCmd().

◆ commandWindow

const Tick gem5::memory::MemCtrl::commandWindow
private

Length of a command window, used to check command bandwidth.

Definition at line 517 of file mem_ctrl.hh.

Referenced by getBurstWindow(), verifyMultiCmd(), and verifySingleCmd().

◆ dram

DRAMInterface* const gem5::memory::MemCtrl::dram
private

◆ frontendLatency

const Tick gem5::memory::MemCtrl::frontendLatency
private

Pipeline latency of the controller frontend.

The frontend contribution is added to writes (that complete when they are in the write buffer) and reads that are serviced the write buffer.

Definition at line 504 of file mem_ctrl.hh.

Referenced by addToReadQueue(), addToWriteQueue(), and processRespondEvent().

◆ isInWriteQueue

std::unordered_set<Addr> gem5::memory::MemCtrl::isInWriteQueue
private

To avoid iterating over the write queue to check for overlapping transactions, maintain a set of burst addresses that are currently queued.

Since we merge writes to the same location we never have more than one address to the same burst address.

Definition at line 450 of file mem_ctrl.hh.

Referenced by addToReadQueue(), addToWriteQueue(), and processNextReqEvent().

◆ isTimingMode

bool gem5::memory::MemCtrl::isTimingMode
private

Remember if the memory system is in timing mode.

Definition at line 281 of file mem_ctrl.hh.

Referenced by drainResume(), and startup().

◆ memSchedPolicy

enums::MemSched gem5::memory::MemCtrl::memSchedPolicy
private

Memory controller configuration initialized based on parameter values.

Definition at line 497 of file mem_ctrl.hh.

Referenced by chooseNext().

◆ minWritesPerSwitch

const uint32_t gem5::memory::MemCtrl::minWritesPerSwitch
private

Definition at line 489 of file mem_ctrl.hh.

Referenced by processNextReqEvent().

◆ nextBurstAt

Tick gem5::memory::MemCtrl::nextBurstAt
private

Till when must we wait before issuing next RD/WR burst?

Definition at line 522 of file mem_ctrl.hh.

Referenced by chooseNextFRFCFS(), doBurstAccess(), and startup().

◆ nextReqEvent

EventFunctionWrapper gem5::memory::MemCtrl::nextReqEvent
private

◆ nextReqTime

Tick gem5::memory::MemCtrl::nextReqTime
private

The soonest you have to start thinking about the next request is the longest access time that can occur before nextBurstAt.

Assuming you need to precharge, open a new row, and access, it is tRP + tRCD + tCL.

Definition at line 532 of file mem_ctrl.hh.

Referenced by doBurstAccess(), and processNextReqEvent().

◆ nvm

NVMInterface* const gem5::memory::MemCtrl::nvm
private

◆ pendingDelete

std::unique_ptr<Packet> gem5::memory::MemCtrl::pendingDelete
private

Upstream caches need this packet until true is returned, so hold it for deletion until a subsequent call.

Definition at line 600 of file mem_ctrl.hh.

Referenced by accessAndRespond().

◆ port

MemoryPort gem5::memory::MemCtrl::port
private

Our incoming port, for a multi-ported controller add a crossbar in front of it.

Definition at line 276 of file mem_ctrl.hh.

Referenced by accessAndRespond(), getPort(), init(), processNextReqEvent(), and processRespondEvent().

◆ prevArrival

Tick gem5::memory::MemCtrl::prevArrival
private

Definition at line 524 of file mem_ctrl.hh.

Referenced by recvTimingReq().

◆ readBufferSize

const uint32_t gem5::memory::MemCtrl::readBufferSize
private

The following are basic design parameters of the memory controller, and are initialized based on parameter values.

The rowsPerBank is determined based on the capacity, number of ranks and banks, the burst size, and the row buffer size.

Definition at line 485 of file mem_ctrl.hh.

Referenced by readQueueFull().

◆ readQueue

std::vector<MemPacketQueue> gem5::memory::MemCtrl::readQueue
private

The controller's main read and write queues, with support for QoS reordering.

Definition at line 440 of file mem_ctrl.hh.

Referenced by addToReadQueue(), printQs(), processNextReqEvent(), recvTimingReq(), and selQueue().

◆ readsThisTime

uint32_t gem5::memory::MemCtrl::readsThisTime
private

Definition at line 491 of file mem_ctrl.hh.

Referenced by doBurstAccess(), and processNextReqEvent().

◆ respondEvent

EventFunctionWrapper gem5::memory::MemCtrl::respondEvent
private

Definition at line 299 of file mem_ctrl.hh.

Referenced by processNextReqEvent(), processRespondEvent(), and respondEventScheduled().

◆ respQueue

std::deque<MemPacket*> gem5::memory::MemCtrl::respQueue
private

Response queue where read packets wait after we're done working with them, but it's not time to send the response yet.

The responses are stored separately mostly to keep the code clean and help with events scheduling. For all logical purposes such as sizing the read queue, this and the main read queue need to be added together.

Definition at line 460 of file mem_ctrl.hh.

Referenced by addToReadQueue(), drain(), printQs(), processNextReqEvent(), processRespondEvent(), and readQueueFull().

◆ retryRdReq

bool gem5::memory::MemCtrl::retryRdReq
private

Remember if we have to retry a request when available.

Definition at line 286 of file mem_ctrl.hh.

Referenced by processRespondEvent(), and recvTimingReq().

◆ retryWrReq

bool gem5::memory::MemCtrl::retryWrReq
private

Definition at line 287 of file mem_ctrl.hh.

Referenced by processNextReqEvent(), and recvTimingReq().

◆ stats

CtrlStats gem5::memory::MemCtrl::stats
private

◆ writeBufferSize

const uint32_t gem5::memory::MemCtrl::writeBufferSize
private

Definition at line 486 of file mem_ctrl.hh.

Referenced by addToWriteQueue(), processNextReqEvent(), and writeQueueFull().

◆ writeHighThreshold

const uint32_t gem5::memory::MemCtrl::writeHighThreshold
private

Definition at line 487 of file mem_ctrl.hh.

Referenced by processNextReqEvent().

◆ writeLowThreshold

const uint32_t gem5::memory::MemCtrl::writeLowThreshold
private

Definition at line 488 of file mem_ctrl.hh.

Referenced by processNextReqEvent().

◆ writeQueue

std::vector<MemPacketQueue> gem5::memory::MemCtrl::writeQueue
private

◆ writesThisTime

uint32_t gem5::memory::MemCtrl::writesThisTime
private

Definition at line 490 of file mem_ctrl.hh.

Referenced by doBurstAccess(), and processNextReqEvent().


The documentation for this class was generated from the following files:

Generated on Tue Sep 21 2021 12:31:28 for gem5 by doxygen 1.8.17