gem5 v24.0.0.0
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mem_interface.cc
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1/*
2 * Copyright (c) 2010-2020 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2013 Amin Farmahini-Farahani
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
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25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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39 */
40
41#include "mem/mem_interface.hh"
42
43#include "base/bitfield.hh"
44#include "base/cprintf.hh"
45#include "base/trace.hh"
46#include "sim/system.hh"
47
48namespace gem5
49{
50
51namespace memory
52{
53
54MemInterface::MemInterface(const MemInterfaceParams &_p)
55 : AbstractMemory(_p),
56 addrMapping(_p.addr_mapping),
57 burstSize((_p.devices_per_rank * _p.burst_length *
58 _p.device_bus_width) / 8),
59 deviceSize(_p.device_size),
60 deviceRowBufferSize(_p.device_rowbuffer_size),
61 devicesPerRank(_p.devices_per_rank),
62 rowBufferSize(devicesPerRank * deviceRowBufferSize),
63 burstsPerRowBuffer(rowBufferSize / burstSize),
64 burstsPerStripe(range.interleaved() ?
65 range.granularity() / burstSize : 1),
66 ranksPerChannel(_p.ranks_per_channel),
67 banksPerRank(_p.banks_per_rank), rowsPerBank(0),
68 tCK(_p.tCK), tCS(_p.tCS), tBURST(_p.tBURST),
69 tRTW(_p.tRTW),
70 tWTR(_p.tWTR),
71 readBufferSize(_p.read_buffer_size),
72 writeBufferSize(_p.write_buffer_size),
73 numWritesQueued(0)
74{}
75
76void
77MemInterface::setCtrl(MemCtrl* _ctrl, unsigned int command_window,
78 uint8_t pseudo_channel)
79{
80 ctrl = _ctrl;
81 maxCommandsPerWindow = command_window / tCK;
82 // setting the pseudo channel number for this interface
83 pseudoChannel = pseudo_channel;
84}
85
86} // namespace memory
87} // namespace gem5
An abstract memory represents a contiguous block of physical memory, with an associated address range...
The memory controller is a single-channel memory controller capturing the most important timing const...
Definition mem_ctrl.hh:247
MemCtrl * ctrl
A pointer to the parent memory controller instance.
uint8_t pseudoChannel
pseudo channel number used for HBM modeling
unsigned int maxCommandsPerWindow
Number of commands that can issue in the defined controller command window, used to verify command ba...
void setCtrl(MemCtrl *_ctrl, unsigned int command_window, uint8_t pseudo_channel=0)
Set a pointer to the controller and initialize interface based on controller parameters.
GEM5_CLASS_VAR_USED const Tick tCK
General timing requirements.
MemInterface(const Params &_p)
MemInterface declaration.
Bitfield< 6 > granularity
Definition misc.hh:1026
Copyright (c) 2024 - Pranith Kumar Copyright (c) 2020 Inria All rights reserved.
Definition binary32.hh:36
Definition mem.h:38

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