gem5  v21.1.0.2
mem_interface.hh
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40 
46 #ifndef __MEM_INTERFACE_HH__
47 #define __MEM_INTERFACE_HH__
48 
49 #include <deque>
50 #include <string>
51 #include <unordered_set>
52 #include <utility>
53 #include <vector>
54 
55 #include "base/compiler.hh"
56 #include "base/statistics.hh"
57 #include "enums/AddrMap.hh"
58 #include "enums/PageManage.hh"
59 #include "mem/abstract_mem.hh"
60 #include "mem/drampower.hh"
61 #include "mem/mem_ctrl.hh"
62 #include "params/DRAMInterface.hh"
63 #include "params/MemInterface.hh"
64 #include "params/NVMInterface.hh"
65 #include "sim/eventq.hh"
66 
67 namespace gem5
68 {
69 
70 namespace memory
71 {
72 
78 {
79  protected:
89  class Bank
90  {
91 
92  public:
93  static const uint32_t NO_ROW = -1;
94 
95  uint32_t openRow;
96  uint8_t bank;
97  uint8_t bankgr;
98 
103 
104  uint32_t rowAccesses;
105  uint32_t bytesAccessed;
106 
107  Bank() :
108  openRow(NO_ROW), bank(0), bankgr(0),
111  { }
112  };
113 
118 
123  unsigned int maxCommandsPerWindow;
124 
129  enums::AddrMap addrMapping;
130 
136  const uint32_t burstSize;
137  const uint32_t deviceSize;
138  const uint32_t deviceRowBufferSize;
139  const uint32_t devicesPerRank;
140  const uint32_t rowBufferSize;
141  const uint32_t burstsPerRowBuffer;
142  const uint32_t burstsPerStripe;
143  const uint32_t ranksPerChannel;
144  const uint32_t banksPerRank;
145  uint32_t rowsPerBank;
146 
151  const Tick tCS;
152  const Tick tBURST;
153  const Tick tRTW;
154  const Tick tWTR;
155 
156  /*
157  * @return delay between write and read commands
158  */
159  virtual Tick writeToReadDelay() const { return tBURST + tWTR; }
160 
161  /*
162  * @return delay between write and read commands
163  */
164  Tick readToWriteDelay() const { return tBURST + tRTW; }
165 
166  /*
167  * @return delay between accesses to different ranks
168  */
169  Tick rankToRankDelay() const { return tBURST + tCS; }
170 
171 
172  public:
173 
180  const uint32_t readBufferSize;
181  const uint32_t writeBufferSize;
182 
189  void setCtrl(MemCtrl* _ctrl, unsigned int command_window);
190 
201 
208  virtual void setupRank(const uint8_t rank, const bool is_read) = 0;
209 
216  virtual bool allRanksDrained() const = 0;
217 
230  chooseNextFRFCFS(MemPacketQueue& queue, Tick min_col_at) const = 0;
231 
232  /*
233  * Function to calulate unloaded latency
234  */
235  virtual Tick accessLatency() const = 0;
236 
240  uint32_t bytesPerBurst() const { return burstSize; }
241 
242  /*
243  * @return time to offset next command
244  */
245  virtual Tick commandOffset() const = 0;
246 
252  virtual bool burstReady(MemPacket* pkt) const = 0;
253 
259  Tick rankDelay() const { return tCS; }
260 
265  Tick minReadToWriteDataGap() const { return std::min(tRTW, tCS); }
266 
271  Tick minWriteToReadDataGap() const { return std::min(tWTR, tCS); }
272 
286  MemPacket* decodePacket(const PacketPtr pkt, Addr pkt_addr,
287  unsigned int size, bool is_read, bool is_dram);
288 
296  virtual void addRankToRankDelay(Tick cmd_at) = 0;
297 
298  typedef MemInterfaceParams Params;
299  MemInterface(const Params &_p);
300 };
301 
309 {
310  private:
315  struct Command
316  {
317  Data::MemCommand::cmds type;
318  uint8_t bank;
320 
321  constexpr Command(Data::MemCommand::cmds _type, uint8_t _bank,
322  Tick time_stamp)
323  : type(_type), bank(_bank), timeStamp(time_stamp)
324  { }
325  };
326 
355  {
356  PWR_IDLE = 0,
362  };
363 
395  {
396  REF_IDLE = 0,
403  };
404 
405  class Rank;
406  struct RankStats : public statistics::Group
407  {
408  RankStats(DRAMInterface &dram, Rank &rank);
409 
410  void regStats() override;
411  void resetStats() override;
412  void preDumpStats() override;
413 
415 
416  /*
417  * Command energies
418  */
424 
425  /*
426  * Active Background Energy
427  */
429 
430  /*
431  * Precharge Background Energy
432  */
434 
435  /*
436  * Active Power-Down Energy
437  */
439 
440  /*
441  * Precharge Power-Down Energy
442  */
444 
445  /*
446  * self Refresh Energy
447  */
449 
452 
458 
463  };
464 
472  class Rank : public EventManager
473  {
474  private:
475 
480 
486 
491 
496 
501 
505  void updatePowerStats();
506 
514  void schedulePowerEvent(PowerState pwr_state, Tick tick);
515 
516  public:
517 
522 
527 
532 
536  uint8_t rank;
537 
541  uint32_t readEntries;
542 
546  uint32_t writeEntries;
547 
554 
559 
564 
572 
578 
583  unsigned int numBanksActive;
584 
587 
592 
593  Rank(const DRAMInterfaceParams &_p, int _rank,
594  DRAMInterface& _dram);
595 
596  const std::string name() const { return csprintf("%d", rank); }
597 
604  void startup(Tick ref_tick);
605 
609  void suspend();
610 
617  bool inRefIdleState() const { return refreshState == REF_IDLE; }
618 
626  bool inPwrIdleState() const { return pwrState == PWR_IDLE; }
627 
638  bool forceSelfRefreshExit() const;
639 
646  bool isQueueEmpty() const;
647 
652  void checkDrainDone();
653 
660  void flushCmdList();
661 
665  void computeStats();
666 
670  void resetStats();
671 
678  void powerDownSleep(PowerState pwr_state, Tick tick);
679 
687  void scheduleWakeUpEvent(Tick exit_delay);
688 
689  void processWriteDoneEvent();
691 
692  void processActivateEvent();
694 
695  void processPrechargeEvent();
697 
698  void processRefreshEvent();
700 
701  void processPowerEvent();
703 
704  void processWakeUpEvent();
706 
707  protected:
709  };
710 
718  static bool
719  sortTime(const Command& cmd, const Command& cmd_next)
720  {
721  return cmd.timeStamp < cmd_next.timeStamp;
722  }
723 
727  const uint32_t bankGroupsPerRank;
728  const bool bankGroupArch;
729 
733  const Tick tCL;
737  const Tick tCCD_L;
738  const Tick tRCD;
739  const Tick tRP;
740  const Tick tRAS;
741  const Tick tWR;
742  const Tick tRTP;
743  const Tick tRFC;
744  const Tick tREFI;
745  const Tick tRRD;
746  const Tick tRRD_L;
747  const Tick tPPD;
748  const Tick tAAD;
749  const Tick tXAW;
750  const Tick tXP;
751  const Tick tXS;
753  const bool dataClockSync;
754  const bool burstInterleave;
755  const uint8_t twoCycleActivate;
756  const uint32_t activationLimit;
759 
760 
761  enums::PageManage pageMgmt;
766  const uint32_t maxAccessesPerRow;
767 
768  // timestamp offset
769  uint64_t timeStampOffset;
770 
771  // Holds the value of the DRAM rank of burst issued
772  uint8_t activeRank;
773 
776 
779 
791  void activateBank(Rank& rank_ref, Bank& bank_ref, Tick act_tick,
792  uint32_t row);
793 
805  void prechargeBank(Rank& rank_ref, Bank& bank_ref,
806  Tick pre_tick, bool auto_or_preall = false,
807  bool trace = true);
808 
809  struct DRAMStats : public statistics::Group
810  {
812 
813  void regStats() override;
814  void resetStats() override;
815 
817 
821 
825 
826  // Latencies summed over all requests
830 
831  // Average latencies per request
835 
836  // Row hit count and rate
842  // Number of bytes transferred to/from DRAM
845 
846  // Average bandwidth
850  // bus utilization
855  };
856 
858 
863 
864  /*
865  * @return delay between write and read commands
866  */
867  Tick writeToReadDelay() const override { return tBURST + tWTR + tCL; }
868 
880  minBankPrep(const MemPacketQueue& queue, Tick min_col_at) const;
881 
882  /*
883  * @return time to send a burst of data without gaps
884  */
885  Tick
886  burstDelay() const
887  {
888  return (burstInterleave ? tBURST_MAX / 2 : tBURST);
889  }
890 
891  public:
895  void init() override;
896 
900  void startup() override;
901 
908  void setupRank(const uint8_t rank, const bool is_read) override;
909 
913  void drainRanks();
914 
924  bool allRanksDrained() const override;
925 
929  void suspend();
930 
931  /*
932  * @return time to offset next command
933  */
934  Tick commandOffset() const override { return (tRP + tRCD); }
935 
936  /*
937  * Function to calulate unloaded, closed bank access latency
938  */
939  Tick accessLatency() const override { return (tRP + tRCD + tCL); }
940 
950  chooseNextFRFCFS(MemPacketQueue& queue, Tick min_col_at) const override;
951 
967  doBurstAccess(MemPacket* mem_pkt, Tick next_burst_at,
968  const std::vector<MemPacketQueue>& queue);
969 
977  bool
978  burstReady(MemPacket* pkt) const override
979  {
980  return ranks[pkt->rank]->inRefIdleState();
981  }
982 
991  bool isBusy();
992 
1000  void addRankToRankDelay(Tick cmd_at) override;
1001 
1009  void respondEvent(uint8_t rank);
1010 
1017  void checkRefreshState(uint8_t rank);
1018 
1019  DRAMInterface(const DRAMInterfaceParams &_p);
1020 };
1021 
1029 {
1030  private:
1034  class Rank : public EventManager
1035  {
1036  public:
1037 
1041  uint8_t rank;
1042 
1048 
1049  Rank(const NVMInterfaceParams &_p, int _rank,
1050  NVMInterface& _nvm);
1051  };
1052 
1056  const uint32_t maxPendingWrites;
1057  const uint32_t maxPendingReads;
1058  const bool twoCycleRdWr;
1059 
1063  const Tick tREAD;
1064  const Tick tWRITE;
1065  const Tick tSEND;
1066 
1067  struct NVMStats : public statistics::Group
1068  {
1070 
1071  void regStats() override;
1072 
1074 
1078 
1081 
1082  // Latencies summed over all requests
1086 
1087  // Average latencies per request
1091 
1094 
1095  // Average bandwidth
1102 
1107  };
1109 
1110  void processWriteRespondEvent();
1112 
1113  void processReadReadyEvent();
1115 
1120 
1130 
1132 
1138  bool writeRespQueueEmpty() const { return writeRespQueue.empty(); }
1139 
1144 
1145  // keep track of reads that have issued for which data is either
1146  // not yet ready or has not yet been transferred to the ctrl
1149 
1150  public:
1151  // keep track of the number of reads that have yet to be issued
1153 
1154  // number of writes in the writeQueue for the NVM interface
1156 
1160  void init() override;
1161 
1168  void setupRank(const uint8_t rank, const bool is_read) override;
1169 
1176  bool allRanksDrained() const override { return writeRespQueueEmpty(); }
1177 
1178  /*
1179  * @return time to offset next command
1180  */
1181  Tick commandOffset() const override { return tBURST; }
1182 
1191  bool burstReady(MemPacket* pkt) const override;
1192 
1204  bool isBusy(bool read_queue_empty, bool all_writes_nvm);
1215  chooseNextFRFCFS(MemPacketQueue& queue, Tick min_col_at) const override;
1216 
1224  void addRankToRankDelay(Tick cmd_at) override;
1225 
1226 
1230  void chooseRead(MemPacketQueue& queue);
1231 
1232  /*
1233  * Function to calulate unloaded access latency
1234  */
1235  Tick accessLatency() const override { return (tREAD + tSEND); }
1236 
1242  bool
1244  {
1245  return writeRespQueue.size() == maxPendingWrites;
1246  }
1247 
1248  bool
1250  {
1251  return ((numReadsToIssue != 0) &&
1253  }
1254 
1264  doBurstAccess(MemPacket* pkt, Tick next_burst_at);
1265 
1266  NVMInterface(const NVMInterfaceParams &_p);
1267 };
1268 
1269 } // namespace memory
1270 } // namespace gem5
1271 
1272 #endif //__MEM_INTERFACE_HH__
gem5::memory::DRAMInterface::Rank::suspend
void suspend()
Stop the refresh events.
Definition: mem_interface.cc:1178
gem5::statistics::Scalar
This is a simple scalar statistic, like a counter.
Definition: statistics.hh:1927
gem5::memory::DRAMInterface::tRRD_L
const Tick tRRD_L
Definition: mem_interface.hh:746
gem5::memory::DRAMInterface::DRAMStats::avgWrBW
statistics::Formula avgWrBW
Definition: mem_interface.hh:848
gem5::memory::DRAMInterface::enableDRAMPowerdown
bool enableDRAMPowerdown
Enable or disable DRAM powerdown states.
Definition: mem_interface.hh:775
gem5::memory::NVMInterface::chooseNextFRFCFS
std::pair< MemPacketQueue::iterator, Tick > chooseNextFRFCFS(MemPacketQueue &queue, Tick min_col_at) const override
For FR-FCFS policy, find first NVM command that can issue default to first command to prepped region.
Definition: mem_interface.cc:2107
gem5::memory::MemInterface::rowsPerBank
uint32_t rowsPerBank
Definition: mem_interface.hh:145
gem5::memory::NVMInterface
Interface to NVM devices with media specific parameters, statistics, and functions.
Definition: mem_interface.hh:1028
gem5::memory::DRAMInterface::DRAMStats::perBankRdBursts
statistics::Vector perBankRdBursts
DRAM per bank stats.
Definition: mem_interface.hh:823
gem5::memory::MemInterface::Bank::bank
uint8_t bank
Definition: mem_interface.hh:96
gem5::memory::DRAMInterface::burstReady
bool burstReady(MemPacket *pkt) const override
Check if a burst operation can be issued to the DRAM.
Definition: mem_interface.hh:978
gem5::memory::DRAMInterface::tWR
const Tick tWR
Definition: mem_interface.hh:741
gem5::memory::DRAMInterface::burstDelay
Tick burstDelay() const
Definition: mem_interface.hh:886
gem5::memory::DRAMInterface::Rank::computeStats
void computeStats()
Computes stats just prior to dump event.
Definition: mem_interface.cc:1820
gem5::memory::NVMInterface::maxPendingReads
const uint32_t maxPendingReads
Definition: mem_interface.hh:1057
gem5::memory::DRAMInterface::Rank::processPrechargeEvent
void processPrechargeEvent()
Definition: mem_interface.cc:1254
gem5::memory::DRAMInterface::respondEvent
void respondEvent(uint8_t rank)
Complete response process for DRAM when read burst is complete This will update the counters and chec...
Definition: mem_interface.cc:946
gem5::memory::NVMInterface::NVMStats::busUtilWrite
statistics::Formula busUtilWrite
Definition: mem_interface.hh:1101
gem5::memory::DRAMInterface::Rank::writeEntries
uint32_t writeEntries
Track number of packets in write queue going to this rank.
Definition: mem_interface.hh:546
gem5::memory::DRAMInterface::PowerState
PowerState
The power state captures the different operational states of the DRAM and interacts with the bus read...
Definition: mem_interface.hh:354
gem5::memory::DRAMInterface::Rank::processPowerEvent
void processPowerEvent()
Definition: mem_interface.cc:1644
gem5::memory::MemInterface::readToWriteDelay
Tick readToWriteDelay() const
Definition: mem_interface.hh:164
gem5::memory::NVMInterface::NVMStats::busUtilRead
statistics::Formula busUtilRead
Definition: mem_interface.hh:1100
gem5::memory::NVMInterface::accessLatency
Tick accessLatency() const override
Definition: mem_interface.hh:1235
gem5::memory::DRAMInterface::RefreshState
RefreshState
The refresh state is used to control the progress of the refresh scheduling.
Definition: mem_interface.hh:394
gem5::memory::DRAMInterface::DRAMStats::writeRowHits
statistics::Scalar writeRowHits
Definition: mem_interface.hh:838
gem5::memory::DRAMInterface::DRAMStats::writeBursts
statistics::Scalar writeBursts
Definition: mem_interface.hh:820
gem5::memory::NVMInterface::numWritesQueued
uint32_t numWritesQueued
Definition: mem_interface.hh:1155
gem5::memory::MemInterface::Bank::Bank
Bank()
Definition: mem_interface.hh:107
gem5::memory::DRAMInterface::activeRank
uint8_t activeRank
Definition: mem_interface.hh:772
gem5::memory::DRAMInterface::DRAMStats::avgQLat
statistics::Formula avgQLat
Definition: mem_interface.hh:832
gem5::memory::MemInterface::tBURST
const Tick tBURST
Definition: mem_interface.hh:152
gem5::memory::DRAMInterface::Rank::pwrStateTrans
PowerState pwrStateTrans
Since we are taking decisions out of order, we need to keep track of what power transition is happeni...
Definition: mem_interface.hh:485
gem5::memory::DRAMInterface::PWR_PRE_PDN
@ PWR_PRE_PDN
Definition: mem_interface.hh:359
gem5::memory::DRAMInterface::DRAMStats::totQLat
statistics::Scalar totQLat
Definition: mem_interface.hh:827
memory
Definition: mem.h:38
gem5::memory::DRAMInterface::Rank::writeDoneEvent
EventFunctionWrapper writeDoneEvent
Definition: mem_interface.hh:690
gem5::memory::NVMInterface::isBusy
bool isBusy(bool read_queue_empty, bool all_writes_nvm)
This function checks if ranks are busy.
Definition: mem_interface.cc:2503
drampower.hh
abstract_mem.hh
gem5::memory::DRAMInterface::RankStats::readEnergy
statistics::Scalar readEnergy
Definition: mem_interface.hh:421
gem5::memory::NVMInterface::NVMInterface
NVMInterface(const NVMInterfaceParams &_p)
Definition: mem_interface.cc:2039
gem5::memory::DRAMInterface::RankStats::preBackEnergy
statistics::Scalar preBackEnergy
Definition: mem_interface.hh:433
gem5::memory::DRAMInterface::DRAMStats::readBursts
statistics::Scalar readBursts
total number of DRAM bursts serviced
Definition: mem_interface.hh:819
gem5::memory::NVMInterface::readReadyEvent
EventFunctionWrapper readReadyEvent
Definition: mem_interface.hh:1114
gem5::memory::DRAMInterface::tREFI
const Tick tREFI
Definition: mem_interface.hh:744
gem5::memory::DRAMInterface::tBURST_MAX
const Tick tBURST_MAX
Definition: mem_interface.hh:735
gem5::memory::DRAMInterface::addRankToRankDelay
void addRankToRankDelay(Tick cmd_at) override
Add rank to rank delay to bus timing to all DRAM banks in alli ranks when access to an alternate inte...
Definition: mem_interface.cc:723
gem5::memory::DRAMInterface::Rank::processWakeUpEvent
void processWakeUpEvent()
Definition: mem_interface.cc:1626
gem5::memory::DRAMInterface::DRAMStats::totBusLat
statistics::Scalar totBusLat
Definition: mem_interface.hh:828
gem5::memory::DRAMInterface::RankStats::refreshEnergy
statistics::Scalar refreshEnergy
Definition: mem_interface.hh:423
gem5::memory::DRAMInterface::DRAMStats
Definition: mem_interface.hh:809
gem5::memory::DRAMInterface::Rank::prechargeEvent
EventFunctionWrapper prechargeEvent
Definition: mem_interface.hh:696
gem5::memory::MemInterface::setCtrl
void setCtrl(MemCtrl *_ctrl, unsigned int command_window)
Set a pointer to the controller and initialize interface based on controller parameters.
Definition: mem_interface.cc:82
gem5::memory::DRAMInterface::Rank::inLowPowerState
bool inLowPowerState
rank is in or transitioning to power-down or self-refresh
Definition: mem_interface.hh:531
gem5::memory::DRAMInterface::Rank::scheduleWakeUpEvent
void scheduleWakeUpEvent(Tick exit_delay)
schedule and event to wake-up from power-down or self-refresh and update bank timing parameters
Definition: mem_interface.cc:1574
gem5::memory::NVMInterface::Rank::banks
std::vector< Bank > banks
Vector of NVM banks.
Definition: mem_interface.hh:1047
gem5::memory::DRAMInterface::Command
Simple structure to hold the values needed to keep track of commands for DRAMPower.
Definition: mem_interface.hh:315
gem5::memory::DRAMInterface::PWR_REF
@ PWR_REF
Definition: mem_interface.hh:357
gem5::memory::DRAMInterface::chooseNextFRFCFS
std::pair< MemPacketQueue::iterator, Tick > chooseNextFRFCFS(MemPacketQueue &queue, Tick min_col_at) const override
For FR-FCFS policy, find first DRAM command that can issue.
Definition: mem_interface.cc:175
gem5::memory::DRAMInterface::ranks
std::vector< Rank * > ranks
Vector of dram ranks.
Definition: mem_interface.hh:862
gem5::memory::NVMInterface::Rank::Rank
Rank(const NVMInterfaceParams &_p, int _rank, NVMInterface &_nvm)
Definition: mem_interface.cc:2078
gem5::memory::MemInterface::allRanksDrained
virtual bool allRanksDrained() const =0
Check drain state of interface.
gem5::memory::MemInterface::deviceSize
const uint32_t deviceSize
Definition: mem_interface.hh:137
gem5::memory::MemInterface::Bank
A basic class to track the bank state, i.e.
Definition: mem_interface.hh:89
gem5::memory::DRAMInterface::tXP
const Tick tXP
Definition: mem_interface.hh:750
gem5::memory::DRAMInterface::RankStats::pwrStateTime
statistics::Vector pwrStateTime
Track time spent in each power state.
Definition: mem_interface.hh:462
gem5::memory::DRAMInterface::activateBank
void activateBank(Rank &rank_ref, Bank &bank_ref, Tick act_tick, uint32_t row)
Keep track of when row activations happen, in order to enforce the maximum number of activations in t...
Definition: mem_interface.cc:290
gem5::memory::MemCtrl
The memory controller is a single-channel memory controller capturing the most important timing const...
Definition: mem_ctrl.hh:242
gem5::memory::NVMInterface::addRankToRankDelay
void addRankToRankDelay(Tick cmd_at) override
Add rank to rank delay to bus timing to all NVM banks in alli ranks when access to an alternate inter...
Definition: mem_interface.cc:2486
gem5::memory::DRAMInterface::REF_DRAIN
@ REF_DRAIN
Definition: mem_interface.hh:397
gem5::memory::MemInterface::burstsPerStripe
const uint32_t burstsPerStripe
Definition: mem_interface.hh:142
gem5::memory::NVMInterface::readsWaitingToIssue
bool readsWaitingToIssue() const
Definition: mem_interface.hh:1249
gem5::memory::DRAMInterface::tRCD
const Tick tRCD
Definition: mem_interface.hh:738
gem5::memory::MemInterface::addRankToRankDelay
virtual void addRankToRankDelay(Tick cmd_at)=0
Add rank to rank delay to bus timing to all banks in all ranks when access to an alternate interface ...
gem5::memory::NVMInterface::allRanksDrained
bool allRanksDrained() const override
Check drain state of NVM interface.
Definition: mem_interface.hh:1176
gem5::memory::DRAMInterface::allRanksDrained
bool allRanksDrained() const override
Return true once refresh is complete for all ranks and there are no additional commands enqueued.
Definition: mem_interface.cc:1020
gem5::memory::DRAMInterface::Rank::processWriteDoneEvent
void processWriteDoneEvent()
Definition: mem_interface.cc:1285
gem5::memory::DRAMInterface::bankGroupArch
const bool bankGroupArch
Definition: mem_interface.hh:728
gem5::DRAMPower
DRAMPower is a standalone tool which calculates the power consumed by a DRAM in the system.
Definition: drampower.hh:56
gem5::memory::MemInterface::Bank::wrAllowedAt
Tick wrAllowedAt
Definition: mem_interface.hh:100
gem5::memory::DRAMInterface::Rank::resetStats
void resetStats()
Reset stats on a stats event.
Definition: mem_interface.cc:1833
gem5::memory::DRAMInterface::maxAccessesPerRow
const uint32_t maxAccessesPerRow
Max column accesses (read and write) per row, before forefully closing it.
Definition: mem_interface.hh:766
gem5::memory::NVMInterface::processWriteRespondEvent
void processWriteRespondEvent()
Definition: mem_interface.cc:2457
gem5::memory::NVMInterface::setupRank
void setupRank(const uint8_t rank, const bool is_read) override
Setup the rank based on packet received.
Definition: mem_interface.cc:2095
gem5::memory::DRAMInterface::DRAMStats::avgBusLat
statistics::Formula avgBusLat
Definition: mem_interface.hh:833
gem5::memory::NVMInterface::numReadsToIssue
uint16_t numReadsToIssue
Definition: mem_interface.hh:1152
gem5::statistics::Vector
A vector of scalar stats.
Definition: statistics.hh:2003
gem5::memory::NVMInterface::NVMStats::pendingReads
statistics::Histogram pendingReads
NVM stats.
Definition: mem_interface.hh:1104
gem5::memory::DRAMInterface::PWR_ACT
@ PWR_ACT
Definition: mem_interface.hh:360
gem5::memory::DRAMInterface::Rank::refreshEvent
EventFunctionWrapper refreshEvent
Definition: mem_interface.hh:699
gem5::memory::MemInterface::tCS
const Tick tCS
Definition: mem_interface.hh:151
gem5::statistics::Formula
A formula for statistics that is calculated when printed.
Definition: statistics.hh:2536
gem5::memory::DRAMInterface::DRAMStats::bytesPerActivate
statistics::Histogram bytesPerActivate
Definition: mem_interface.hh:841
gem5::memory::DRAMInterface::Rank::outstandingEvents
uint8_t outstandingEvents
Number of ACT, RD, and WR events currently scheduled Incremented when a refresh event is started as w...
Definition: mem_interface.hh:553
std::vector
STL vector class.
Definition: stl.hh:37
gem5::memory::DRAMInterface::Rank::activateEvent
EventFunctionWrapper activateEvent
Definition: mem_interface.hh:693
gem5::memory::NVMInterface::tREAD
const Tick tREAD
NVM specific timing requirements.
Definition: mem_interface.hh:1063
gem5::memory::NVMInterface::Rank
NVM rank class simply includes a vector of banks.
Definition: mem_interface.hh:1034
gem5::memory::DRAMInterface::PWR_IDLE
@ PWR_IDLE
Definition: mem_interface.hh:356
gem5::csprintf
std::string csprintf(const char *format, const Args &...args)
Definition: cprintf.hh:161
gem5::memory::DRAMInterface::Rank::Rank
Rank(const DRAMInterfaceParams &_p, int _rank, DRAMInterface &_dram)
Definition: mem_interface.cc:1127
gem5::memory::DRAMInterface::RankStats::prePowerDownEnergy
statistics::Scalar prePowerDownEnergy
Definition: mem_interface.hh:443
gem5::memory::DRAMInterface::tRTP
const Tick tRTP
Definition: mem_interface.hh:742
gem5::memory::DRAMInterface::Rank::checkDrainDone
void checkDrainDone()
Let the rank check if it was waiting for requests to drain to allow it to transition states.
Definition: mem_interface.cc:1201
gem5::memory::NVMInterface::NVMStats::avgQLat
statistics::Formula avgQLat
Definition: mem_interface.hh:1088
gem5::memory::DRAMInterface::rdToWrDlySameBG
const Tick rdToWrDlySameBG
Definition: mem_interface.hh:758
gem5::memory::NVMInterface::writeRespQueueFull
bool writeRespQueueFull() const
Check if the write response queue has reached defined threshold.
Definition: mem_interface.hh:1243
gem5::memory::MemInterface::Bank::rowAccesses
uint32_t rowAccesses
Definition: mem_interface.hh:104
gem5::memory::DRAMInterface::Rank::powerDownSleep
void powerDownSleep(PowerState pwr_state, Tick tick)
Schedule a transition to power-down (sleep)
Definition: mem_interface.cc:1523
gem5::memory::DRAMInterface::Rank::pwrStateTick
Tick pwrStateTick
Track when we transitioned to the current power state.
Definition: mem_interface.hh:495
gem5::memory::DRAMInterface::Command::Command
constexpr Command(Data::MemCommand::cmds _type, uint8_t _bank, Tick time_stamp)
Definition: mem_interface.hh:321
gem5::memory::NVMInterface::twoCycleRdWr
const bool twoCycleRdWr
Definition: mem_interface.hh:1058
gem5::memory::DRAMInterface::RankStats::totalEnergy
statistics::Scalar totalEnergy
Definition: mem_interface.hh:450
gem5::memory::DRAMInterface::drainRanks
void drainRanks()
Iterate through dram ranks to exit self-refresh in order to drain.
Definition: mem_interface.cc:1006
gem5::memory::DRAMInterface::accessLatency
Tick accessLatency() const override
Definition: mem_interface.hh:939
gem5::memory::DRAMInterface::Rank::readEntries
uint32_t readEntries
Track number of packets in read queue going to this rank.
Definition: mem_interface.hh:541
gem5::memory::MemInterface::Bank::preAllowedAt
Tick preAllowedAt
Definition: mem_interface.hh:101
gem5::memory::DRAMInterface::RankStats::regStats
void regStats() override
Callback to set stat parameters.
Definition: mem_interface.cc:2009
GEM5_CLASS_VAR_USED
#define GEM5_CLASS_VAR_USED
Definition: compiler.hh:189
gem5::memory::DRAMInterface::RankStats::rank
Rank & rank
Definition: mem_interface.hh:414
gem5::memory::MemInterface::burstsPerRowBuffer
const uint32_t burstsPerRowBuffer
Definition: mem_interface.hh:141
gem5::memory::NVMInterface::tWRITE
const Tick tWRITE
Definition: mem_interface.hh:1064
gem5::memory::MemInterface::readBufferSize
const uint32_t readBufferSize
Buffer sizes for read and write queues in the controller These are passed to the controller on instan...
Definition: mem_interface.hh:180
gem5::memory::DRAMInterface::Rank::processRefreshEvent
void processRefreshEvent()
Definition: mem_interface.cc:1296
gem5::memory::DRAMInterface::bankGroupsPerRank
const uint32_t bankGroupsPerRank
DRAM specific device characteristics.
Definition: mem_interface.hh:727
gem5::memory::DRAMInterface::RankStats::actEnergy
statistics::Scalar actEnergy
Definition: mem_interface.hh:419
gem5::memory::NVMInterface::NVMStats::avgBusLat
statistics::Formula avgBusLat
Definition: mem_interface.hh:1089
gem5::memory::DRAMInterface::setupRank
void setupRank(const uint8_t rank, const bool is_read) override
Setup the rank based on packet received.
Definition: mem_interface.cc:935
gem5::memory::DRAMInterface::suspend
void suspend()
Iterate through DRAM ranks and suspend them.
Definition: mem_interface.cc:1035
gem5::memory::NVMInterface::readReadyQueue
std::deque< Tick > readReadyQueue
Definition: mem_interface.hh:1131
gem5::memory::DRAMInterface::PWR_SREF
@ PWR_SREF
Definition: mem_interface.hh:358
gem5::memory::DRAMInterface::Rank::processActivateEvent
void processActivateEvent()
Definition: mem_interface.cc:1244
gem5::memory::NVMInterface::NVMStats::peakBW
statistics::Formula peakBW
Definition: mem_interface.hh:1098
gem5::memory::MemInterface::MemInterface
MemInterface(const Params &_p)
Definition: mem_interface.cc:60
gem5::memory::NVMInterface::NVMStats::totBusLat
statistics::Scalar totBusLat
Definition: mem_interface.hh:1084
gem5::memory::DRAMInterface
Interface to DRAM devices with media specific parameters, statistics, and functions.
Definition: mem_interface.hh:308
gem5::memory::DRAMInterface::Command::type
Data::MemCommand::cmds type
Definition: mem_interface.hh:317
gem5::memory::DRAMInterface::lastStatsResetTick
Tick lastStatsResetTick
The time when stats were last reset used to calculate average power.
Definition: mem_interface.hh:778
gem5::memory::MemInterface::minWriteToReadDataGap
Tick minWriteToReadDataGap() const
Definition: mem_interface.hh:271
gem5::memory::DRAMInterface::REF_PRE
@ REF_PRE
Definition: mem_interface.hh:400
gem5::memory::DRAMInterface::RankStats::averagePower
statistics::Scalar averagePower
Definition: mem_interface.hh:451
gem5::memory::MemInterface::addrMapping
enums::AddrMap addrMapping
Memory controller configuration initialized based on parameter values.
Definition: mem_interface.hh:129
gem5::memory::DRAMInterface::Rank::rank
uint8_t rank
Current Rank index.
Definition: mem_interface.hh:536
gem5::memory::NVMInterface::maxPendingWrites
const uint32_t maxPendingWrites
NVM specific device and channel characteristics.
Definition: mem_interface.hh:1056
gem5::statistics::Histogram
A simple histogram stat.
Definition: statistics.hh:2123
gem5::EventManager
Definition: eventq.hh:987
gem5::memory::NVMInterface::NVMStats::totMemAccLat
statistics::Scalar totMemAccLat
Definition: mem_interface.hh:1085
gem5::memory::MemInterface::Bank::bytesAccessed
uint32_t bytesAccessed
Definition: mem_interface.hh:105
gem5::memory::DRAMInterface::REF_RUN
@ REF_RUN
Definition: mem_interface.hh:402
gem5::memory::DRAMInterface::stats
DRAMStats stats
Definition: mem_interface.hh:857
gem5::memory::DRAMInterface::DRAMStats::peakBW
statistics::Formula peakBW
Definition: mem_interface.hh:849
gem5::memory::DRAMInterface::Rank::name
const std::string name() const
Definition: mem_interface.hh:596
gem5::memory::DRAMInterface::tPPD
const Tick tPPD
Definition: mem_interface.hh:747
gem5::memory::MemInterface::deviceRowBufferSize
const uint32_t deviceRowBufferSize
Definition: mem_interface.hh:138
gem5::memory::DRAMInterface::DRAMInterface
DRAMInterface(const DRAMInterfaceParams &_p)
Definition: mem_interface.cc:739
gem5::memory::MemInterface::Bank::rdAllowedAt
Tick rdAllowedAt
Definition: mem_interface.hh:99
gem5::memory::DRAMInterface::isBusy
bool isBusy()
This function checks if ranks are actively refreshing and therefore busy.
Definition: mem_interface.cc:898
gem5::memory::DRAMInterface::DRAMStats::avgMemAccLat
statistics::Formula avgMemAccLat
Definition: mem_interface.hh:834
gem5::memory::DRAMInterface::DRAMStats::regStats
void regStats() override
Callback to set stat parameters.
Definition: mem_interface.cc:1924
gem5::memory::DRAMInterface::DRAMStats::DRAMStats
DRAMStats(DRAMInterface &dram)
Definition: mem_interface.cc:1854
gem5::memory::MemInterface
General interface to memory device Includes functions and parameters shared across media types.
Definition: mem_interface.hh:77
gem5::memory::MemInterface::setupRank
virtual void setupRank(const uint8_t rank, const bool is_read)=0
Setup the rank based on packet received.
gem5::memory::NVMInterface::NVMStats::bytesRead
statistics::Scalar bytesRead
Definition: mem_interface.hh:1092
gem5::memory::NVMInterface::numPendingReads
uint16_t numPendingReads
Definition: mem_interface.hh:1147
gem5::memory::DRAMInterface::DRAMStats::busUtil
statistics::Formula busUtil
Definition: mem_interface.hh:851
gem5::memory::DRAMInterface::Rank::dram
DRAMInterface & dram
A reference to the parent DRAMInterface instance.
Definition: mem_interface.hh:479
gem5::memory::MemInterface::banksPerRank
const uint32_t banksPerRank
Definition: mem_interface.hh:144
gem5::memory::DRAMInterface::DRAMStats::busUtilWrite
statistics::Formula busUtilWrite
Definition: mem_interface.hh:853
gem5::memory::DRAMInterface::DRAMStats::avgRdBW
statistics::Formula avgRdBW
Definition: mem_interface.hh:847
gem5::memory::MemInterface::Bank::bankgr
uint8_t bankgr
Definition: mem_interface.hh:97
gem5::memory::DRAMInterface::Rank::banks
std::vector< Bank > banks
Vector of Banks.
Definition: mem_interface.hh:577
gem5::memory::DRAMInterface::DRAMStats::dram
DRAMInterface & dram
Definition: mem_interface.hh:816
gem5::memory::DRAMInterface::tCL
const Tick tCL
DRAM specific timing requirements.
Definition: mem_interface.hh:733
gem5::memory::DRAMInterface::tRP
const Tick tRP
Definition: mem_interface.hh:739
gem5::memory::DRAMInterface::Rank::inPwrIdleState
bool inPwrIdleState() const
Check if the current rank has all banks closed and is not in a low power state.
Definition: mem_interface.hh:626
gem5::Packet
A Packet is used to encapsulate a transfer between two objects in the memory system (e....
Definition: packet.hh:283
gem5::memory::DRAMInterface::PWR_ACT_PDN
@ PWR_ACT_PDN
Definition: mem_interface.hh:361
gem5::memory::NVMInterface::writeRespondEvent
EventFunctionWrapper writeRespondEvent
Definition: mem_interface.hh:1111
gem5::memory::DRAMInterface::Rank::refreshState
RefreshState refreshState
current refresh state
Definition: mem_interface.hh:526
gem5::memory::DRAMInterface::tXAW
const Tick tXAW
Definition: mem_interface.hh:749
gem5::memory::DRAMInterface::minBankPrep
std::pair< std::vector< uint32_t >, bool > minBankPrep(const MemPacketQueue &queue, Tick min_col_at) const
Find which are the earliest banks ready to issue an activate for the enqueued requests.
Definition: mem_interface.cc:1043
gem5::memory::DRAMInterface::DRAMStats::pageHitRate
statistics::Formula pageHitRate
Definition: mem_interface.hh:854
gem5::memory::DRAMInterface::activationLimit
const uint32_t activationLimit
Definition: mem_interface.hh:756
statistics.hh
gem5::memory::AbstractMemory
An abstract memory represents a contiguous block of physical memory, with an associated address range...
Definition: abstract_mem.hh:110
gem5::Tick
uint64_t Tick
Tick count type.
Definition: types.hh:58
gem5::memory::DRAMInterface::commandOffset
Tick commandOffset() const override
Definition: mem_interface.hh:934
gem5::memory::DRAMInterface::RankStats::actBackEnergy
statistics::Scalar actBackEnergy
Definition: mem_interface.hh:428
gem5::memory::DRAMInterface::Rank::flushCmdList
void flushCmdList()
Push command out of cmdList queue that are scheduled at or before curTick() to DRAMPower library All ...
Definition: mem_interface.cc:1216
gem5::memory::MemPacket
A memory packet stores packets along with the timestamp of when the packet entered the queue,...
Definition: mem_ctrl.hh:97
gem5::memory::MemInterface::commandOffset
virtual Tick commandOffset() const =0
gem5::memory::NVMInterface::tSEND
const Tick tSEND
Definition: mem_interface.hh:1065
gem5::memory::DRAMInterface::Rank::power
DRAMPower power
One DRAMPower instance per rank.
Definition: mem_interface.hh:563
gem5::memory::MemInterface::burstReady
virtual bool burstReady(MemPacket *pkt) const =0
Check if a burst operation can be issued to the interface.
gem5::memory::DRAMInterface::Rank::actTicks
std::deque< Tick > actTicks
List to keep track of activate ticks.
Definition: mem_interface.hh:586
gem5::memory::NVMInterface::NVMStats::totQLat
statistics::Scalar totQLat
Definition: mem_interface.hh:1083
gem5::memory::DRAMInterface::tRRD
const Tick tRRD
Definition: mem_interface.hh:745
gem5::memory::DRAMInterface::Rank::isQueueEmpty
bool isQueueEmpty() const
Check if the command queue of current rank is idle.
Definition: mem_interface.cc:1190
gem5::memory::DRAMInterface::DRAMStats::readRowHits
statistics::Scalar readRowHits
Definition: mem_interface.hh:837
gem5::memory::MemInterface::rankDelay
Tick rankDelay() const
Determine the required delay for an access to a different rank.
Definition: mem_interface.hh:259
gem5::memory::DRAMInterface::checkRefreshState
void checkRefreshState(uint8_t rank)
Check the refresh state to determine if refresh needs to be kicked back into action after a read resp...
Definition: mem_interface.cc:993
gem5::memory::NVMInterface::NVMStats::NVMStats
NVMStats(NVMInterface &nvm)
Definition: mem_interface.cc:2521
gem5::memory::NVMInterface::processReadReadyEvent
void processReadReadyEvent()
Definition: mem_interface.cc:2258
gem5::memory::MemInterface::writeBufferSize
const uint32_t writeBufferSize
Definition: mem_interface.hh:181
gem5::memory::DRAMInterface::tXS
const Tick tXS
Definition: mem_interface.hh:751
gem5::memory::MemInterface::devicesPerRank
const uint32_t devicesPerRank
Definition: mem_interface.hh:139
compiler.hh
mem_ctrl.hh
gem5::memory::DRAMInterface::RankStats::writeEnergy
statistics::Scalar writeEnergy
Definition: mem_interface.hh:422
gem5::memory::DRAMInterface::writeToReadDelay
Tick writeToReadDelay() const override
Definition: mem_interface.hh:867
gem5::memory::MemInterface::minReadToWriteDataGap
Tick minReadToWriteDataGap() const
Definition: mem_interface.hh:265
gem5::memory::DRAMInterface::REF_IDLE
@ REF_IDLE
Definition: mem_interface.hh:396
gem5::memory::DRAMInterface::tAAD
const Tick tAAD
Definition: mem_interface.hh:748
std::pair
STL pair class.
Definition: stl.hh:58
gem5::memory::NVMInterface::NVMStats::avgWrBW
statistics::Formula avgWrBW
Definition: mem_interface.hh:1097
gem5::memory::MemInterface::ctrl
MemCtrl * ctrl
A pointer to the parent MemCtrl instance.
Definition: mem_interface.hh:117
gem5::memory::DRAMInterface::Rank::wakeUpEvent
EventFunctionWrapper wakeUpEvent
Definition: mem_interface.hh:705
gem5::memory::MemInterface::tWTR
const Tick tWTR
Definition: mem_interface.hh:154
gem5::memory::AbstractMemory::range
AddrRange range
Definition: abstract_mem.hh:115
gem5::memory::DRAMInterface::RankStats::selfRefreshEnergy
statistics::Scalar selfRefreshEnergy
Definition: mem_interface.hh:448
gem5::memory::NVMInterface::NVMStats::avgMemAccLat
statistics::Formula avgMemAccLat
Definition: mem_interface.hh:1090
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::memory::DRAMInterface::Rank::updatePowerStats
void updatePowerStats()
Function to update Power Stats.
Definition: mem_interface.cc:1777
gem5::memory::MemInterface::Params
MemInterfaceParams Params
Definition: mem_interface.hh:298
gem5::memory::DRAMInterface::tCCD_L
const Tick tCCD_L
Definition: mem_interface.hh:737
gem5::memory::MemInterface::rankToRankDelay
Tick rankToRankDelay() const
Definition: mem_interface.hh:169
gem5::memory::MemInterface::writeToReadDelay
virtual Tick writeToReadDelay() const
Definition: mem_interface.hh:159
gem5::memory::DRAMInterface::wrToRdDlySameBG
const Tick wrToRdDlySameBG
Definition: mem_interface.hh:757
gem5::memory::NVMInterface::init
void init() override
Initialize the NVM interface and verify parameters.
Definition: mem_interface.cc:2090
gem5::memory::NVMInterface::NVMStats::writeBursts
statistics::Scalar writeBursts
Definition: mem_interface.hh:1077
gem5::memory::NVMInterface::burstReady
bool burstReady(MemPacket *pkt) const override
Check if a burst operation can be issued to the NVM.
Definition: mem_interface.cc:2303
gem5::memory::DRAMInterface::DRAMStats::totMemAccLat
statistics::Scalar totMemAccLat
Definition: mem_interface.hh:829
gem5::memory::NVMInterface::chooseRead
void chooseRead(MemPacketQueue &queue)
Select read command to issue asynchronously.
Definition: mem_interface.cc:2163
gem5::memory::DRAMInterface::Rank::lastBurstTick
Tick lastBurstTick
Track when we issued the last read/write burst.
Definition: mem_interface.hh:591
gem5::memory::MemInterface::Bank::openRow
uint32_t openRow
Definition: mem_interface.hh:95
gem5::memory::MemInterface::tRTW
const Tick tRTW
Definition: mem_interface.hh:153
gem5::memory::NVMInterface::NVMStats::avgRdBW
statistics::Formula avgRdBW
Definition: mem_interface.hh:1096
gem5::EventFunctionWrapper
Definition: eventq.hh:1115
gem5::memory::AbstractMemory::size
uint64_t size() const
Get the memory size.
Definition: abstract_mem.hh:301
gem5::memory::DRAMInterface::twoCycleActivate
const uint8_t twoCycleActivate
Definition: mem_interface.hh:755
gem5::memory::NVMInterface::NVMStats::bytesPerBank
statistics::Histogram bytesPerBank
Definition: mem_interface.hh:1106
gem5::memory::DRAMInterface::REF_START
@ REF_START
Definition: mem_interface.hh:401
gem5::memory::DRAMInterface::Rank::stats
RankStats stats
Definition: mem_interface.hh:708
gem5::memory::MemInterface::ranksPerChannel
const uint32_t ranksPerChannel
Definition: mem_interface.hh:143
gem5::memory::NVMInterface::commandOffset
Tick commandOffset() const override
Definition: mem_interface.hh:1181
gem5::memory::DRAMInterface::RankStats
Definition: mem_interface.hh:406
gem5::memory::DRAMInterface::Rank::inRefIdleState
bool inRefIdleState() const
Check if there is no refresh and no preparation of refresh ongoing i.e.
Definition: mem_interface.hh:617
gem5::memory::NVMInterface::doBurstAccess
std::pair< Tick, Tick > doBurstAccess(MemPacket *pkt, Tick next_burst_at)
Actually do the burst and update stats.
Definition: mem_interface.cc:2312
gem5::memory::DRAMInterface::doBurstAccess
std::pair< Tick, Tick > doBurstAccess(MemPacket *mem_pkt, Tick next_burst_at, const std::vector< MemPacketQueue > &queue)
Actually do the burst - figure out the latency it will take to service the req based on bank state,...
Definition: mem_interface.cc:462
gem5::memory::DRAMInterface::REF_PD_EXIT
@ REF_PD_EXIT
Definition: mem_interface.hh:398
gem5::memory::NVMInterface::ranks
std::vector< Rank * > ranks
Vector of nvm ranks.
Definition: mem_interface.hh:1119
gem5::memory::DRAMInterface::Rank::numBanksActive
unsigned int numBanksActive
To track number of banks which are currently active for this rank.
Definition: mem_interface.hh:583
gem5::memory::DRAMInterface::init
void init() override
Initialize the DRAM interface and verify parameters.
Definition: mem_interface.cc:843
gem5::AddrRange::getOffset
Addr getOffset(const Addr &a) const
Determine the offset of an address within the range.
Definition: addr_range.hh:575
gem5::memory::NVMInterface::NVMStats::perBankWrBursts
statistics::Vector perBankWrBursts
Definition: mem_interface.hh:1080
gem5::memory::NVMInterface::NVMStats::regStats
void regStats() override
Callback to set stat parameters.
Definition: mem_interface.cc:2582
gem5::memory::MemPacket::rank
const uint8_t rank
Will be populated by address decoder.
Definition: mem_ctrl.hh:119
gem5::memory::DRAMInterface::tBURST_MIN
const Tick tBURST_MIN
Definition: mem_interface.hh:734
gem5::memory::NVMInterface::Rank::rank
uint8_t rank
Current Rank index.
Definition: mem_interface.hh:1041
gem5::memory::DRAMInterface::tCCD_L_WR
const Tick tCCD_L_WR
Definition: mem_interface.hh:736
gem5::memory::DRAMInterface::REF_SREF_EXIT
@ REF_SREF_EXIT
Definition: mem_interface.hh:399
std::deque
STL deque class.
Definition: stl.hh:44
gem5::memory::NVMInterface::NVMStats::readBursts
statistics::Scalar readBursts
NVM stats.
Definition: mem_interface.hh:1076
gem5::memory::DRAMInterface::dataClockSync
const bool dataClockSync
Definition: mem_interface.hh:753
gem5::memory::DRAMInterface::DRAMStats::perBankWrBursts
statistics::Vector perBankWrBursts
Definition: mem_interface.hh:824
gem5::memory::MemInterface::chooseNextFRFCFS
virtual std::pair< MemPacketQueue::iterator, Tick > chooseNextFRFCFS(MemPacketQueue &queue, Tick min_col_at) const =0
For FR-FCFS policy, find first command that can issue Function will be overriden by interface to sele...
gem5::memory::DRAMInterface::Rank::refreshDueAt
Tick refreshDueAt
Keep track of when a refresh is due.
Definition: mem_interface.hh:500
gem5::memory::DRAMInterface::burstInterleave
const bool burstInterleave
Definition: mem_interface.hh:754
gem5::Clocked::tick
Tick tick
Definition: clocked_object.hh:68
gem5::memory::DRAMInterface::DRAMStats::bytesRead
statistics::Scalar bytesRead
Definition: mem_interface.hh:843
gem5::memory::NVMInterface::stats
NVMStats stats
Definition: mem_interface.hh:1108
gem5::memory::NVMInterface::NVMStats::busUtil
statistics::Formula busUtil
Definition: mem_interface.hh:1099
gem5::memory::NVMInterface::NVMStats
Definition: mem_interface.hh:1067
gem5::memory::DRAMInterface::clkResyncDelay
const Tick clkResyncDelay
Definition: mem_interface.hh:752
gem5::statistics::Group
Statistics container.
Definition: group.hh:93
gem5::memory::NVMInterface::NVMStats::perBankRdBursts
statistics::Vector perBankRdBursts
Definition: mem_interface.hh:1079
gem5::memory::DRAMInterface::Command::timeStamp
Tick timeStamp
Definition: mem_interface.hh:319
gem5::memory::DRAMInterface::prechargeBank
void prechargeBank(Rank &rank_ref, Bank &bank_ref, Tick pre_tick, bool auto_or_preall=false, bool trace=true)
Precharge a given bank and also update when the precharge is done.
Definition: mem_interface.cc:399
gem5::memory::DRAMInterface::RankStats::actPowerDownEnergy
statistics::Scalar actPowerDownEnergy
Definition: mem_interface.hh:438
gem5::memory::DRAMInterface::DRAMStats::bytesWritten
statistics::Scalar bytesWritten
Definition: mem_interface.hh:844
gem5::memory::NVMInterface::NVMStats::nvm
NVMInterface & nvm
Definition: mem_interface.hh:1073
gem5::memory::NVMInterface::NVMStats::pendingWrites
statistics::Histogram pendingWrites
Definition: mem_interface.hh:1105
gem5::memory::MemInterface::rowBufferSize
const uint32_t rowBufferSize
Definition: mem_interface.hh:140
gem5::memory::MemInterface::getCtrlAddr
Addr getCtrlAddr(Addr addr)
Get an address in a dense range which starts from 0.
Definition: mem_interface.hh:200
gem5::memory::NVMInterface::nextReadAt
Tick nextReadAt
Till when must we wait before issuing next read command?
Definition: mem_interface.hh:1143
gem5::memory::DRAMInterface::RankStats::preEnergy
statistics::Scalar preEnergy
Definition: mem_interface.hh:420
gem5::memory::DRAMInterface::DRAMStats::writeRowHitRate
statistics::Formula writeRowHitRate
Definition: mem_interface.hh:840
gem5::memory::DRAMInterface::Rank::powerEvent
EventFunctionWrapper powerEvent
Definition: mem_interface.hh:702
gem5::memory::MemInterface::Bank::NO_ROW
static const uint32_t NO_ROW
Definition: mem_interface.hh:93
gem5::memory::DRAMInterface::Rank::cmdList
std::vector< Command > cmdList
List of commands issued, to be sent to DRAMPpower at refresh and stats dump.
Definition: mem_interface.hh:571
gem5::memory::MemInterface::decodePacket
MemPacket * decodePacket(const PacketPtr pkt, Addr pkt_addr, unsigned int size, bool is_read, bool is_dram)
Address decoder to figure out physical mapping onto ranks, banks, and rows.
Definition: mem_interface.cc:89
gem5::memory::DRAMInterface::tRFC
const Tick tRFC
Definition: mem_interface.hh:743
gem5::memory::MemInterface::bytesPerBurst
uint32_t bytesPerBurst() const
Definition: mem_interface.hh:240
std::list< Tick >
gem5::memory::DRAMInterface::Rank::wakeUpAllowedAt
Tick wakeUpAllowedAt
delay low-power exit until this requirement is met
Definition: mem_interface.hh:558
gem5::memory::NVMInterface::writeRespQueue
std::list< Tick > writeRespQueue
Holding queue for non-deterministic write commands, which maintains writes that have been issued but ...
Definition: mem_interface.hh:1129
gem5::memory::DRAMInterface::Rank
Rank class includes a vector of banks.
Definition: mem_interface.hh:472
gem5::memory::MemInterface::Bank::actAllowedAt
Tick actAllowedAt
Definition: mem_interface.hh:102
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40
gem5::memory::MemInterface::maxCommandsPerWindow
unsigned int maxCommandsPerWindow
Number of commands that can issue in the defined controller command window, used to verify command ba...
Definition: mem_interface.hh:123
gem5::memory::MemInterface::accessLatency
virtual Tick accessLatency() const =0
gem5::memory::DRAMInterface::DRAMStats::readRowHitRate
statistics::Formula readRowHitRate
Definition: mem_interface.hh:839
gem5::memory::DRAMInterface::RankStats::totalIdleTime
statistics::Scalar totalIdleTime
Stat to track total DRAM idle time.
Definition: mem_interface.hh:457
gem5::memory::DRAMInterface::pageMgmt
enums::PageManage pageMgmt
Definition: mem_interface.hh:761
gem5::memory::DRAMInterface::Rank::schedulePowerEvent
void schedulePowerEvent(PowerState pwr_state, Tick tick)
Schedule a power state transition in the future, and potentially override an already scheduled transi...
Definition: mem_interface.cc:1502
gem5::memory::DRAMInterface::DRAMStats::resetStats
void resetStats() override
Callback to reset stats.
Definition: mem_interface.cc:1849
gem5::memory::NVMInterface::numReadDataReady
uint16_t numReadDataReady
Definition: mem_interface.hh:1148
gem5::memory::DRAMInterface::Rank::startup
void startup(Tick ref_tick)
Kick off accounting for power and refresh states and schedule initial refresh.
Definition: mem_interface.cc:1166
gem5::memory::NVMInterface::NVMStats::bytesWritten
statistics::Scalar bytesWritten
Definition: mem_interface.hh:1093
gem5::memory::MemInterface::burstSize
const uint32_t burstSize
General device and channel characteristics The rowsPerBank is determined based on the capacity,...
Definition: mem_interface.hh:136
gem5::memory::NVMInterface::writeRespQueueEmpty
bool writeRespQueueEmpty() const
Check if the write response queue is empty.
Definition: mem_interface.hh:1138
gem5::memory::DRAMInterface::timeStampOffset
uint64_t timeStampOffset
Definition: mem_interface.hh:769
gem5::memory::DRAMInterface::RankStats::preDumpStats
void preDumpStats() override
Callback before stats are dumped.
Definition: mem_interface.cc:2032
gem5::memory::DRAMInterface::Command::bank
uint8_t bank
Definition: mem_interface.hh:318
gem5::memory::DRAMInterface::Rank::pwrStatePostRefresh
PowerState pwrStatePostRefresh
Previous low-power state, which will be re-entered after refresh.
Definition: mem_interface.hh:490
gem5::memory::MemInterface::tCK
const GEM5_CLASS_VAR_USED Tick tCK
General timing requirements.
Definition: mem_interface.hh:150
gem5::memory::DRAMInterface::sortTime
static bool sortTime(const Command &cmd, const Command &cmd_next)
Function for sorting Command structures based on timeStamp.
Definition: mem_interface.hh:719
gem5::memory::DRAMInterface::tRAS
const Tick tRAS
Definition: mem_interface.hh:740
gem5::memory::DRAMInterface::Rank::pwrState
PowerState pwrState
Current power state.
Definition: mem_interface.hh:521
gem5::memory::DRAMInterface::startup
void startup() override
Iterate through dram ranks and instantiate per rank startup routine.
Definition: mem_interface.cc:885
gem5::memory::DRAMInterface::DRAMStats::busUtilRead
statistics::Formula busUtilRead
Definition: mem_interface.hh:852
gem5::memory::DRAMInterface::RankStats::RankStats
RankStats(DRAMInterface &dram, Rank &rank)
Definition: mem_interface.cc:1971
gem5::X86ISA::addr
Bitfield< 3 > addr
Definition: types.hh:84
gem5::memory::DRAMInterface::RankStats::resetStats
void resetStats() override
Callback to reset stats.
Definition: mem_interface.cc:2024
gem5::memory::DRAMInterface::Rank::forceSelfRefreshExit
bool forceSelfRefreshExit() const
Trigger a self-refresh exit if there are entries enqueued Exit if there are any read entries regardle...
Definition: mem_interface.cc:1843
eventq.hh

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