gem5  v22.0.0.2
mem_interface.hh
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40 
46 #ifndef __MEM_INTERFACE_HH__
47 #define __MEM_INTERFACE_HH__
48 
49 #include <deque>
50 #include <string>
51 #include <unordered_set>
52 #include <utility>
53 #include <vector>
54 
55 #include "base/compiler.hh"
56 #include "base/statistics.hh"
57 #include "enums/AddrMap.hh"
58 #include "enums/PageManage.hh"
59 #include "mem/abstract_mem.hh"
60 #include "mem/mem_ctrl.hh"
61 #include "params/MemInterface.hh"
62 #include "sim/eventq.hh"
63 
64 namespace gem5
65 {
66 
67 namespace memory
68 {
69 
75 {
76  protected:
86  class Bank
87  {
88 
89  public:
90  static const uint32_t NO_ROW = -1;
91 
92  uint32_t openRow;
93  uint8_t bank;
94  uint8_t bankgr;
95 
100 
101  uint32_t rowAccesses;
102  uint32_t bytesAccessed;
103 
104  Bank() :
105  openRow(NO_ROW), bank(0), bankgr(0),
108  { }
109  };
110 
115 
120  unsigned int maxCommandsPerWindow;
121 
126  enums::AddrMap addrMapping;
127 
133  const uint32_t burstSize;
134  const uint32_t deviceSize;
135  const uint32_t deviceRowBufferSize;
136  const uint32_t devicesPerRank;
137  const uint32_t rowBufferSize;
138  const uint32_t burstsPerRowBuffer;
139  const uint32_t burstsPerStripe;
140  const uint32_t ranksPerChannel;
141  const uint32_t banksPerRank;
142  uint32_t rowsPerBank;
143 
148  const Tick tCS;
149  const Tick tBURST;
150  const Tick tRTW;
151  const Tick tWTR;
152 
153  /*
154  * @return delay between write and read commands
155  */
156  virtual Tick writeToReadDelay() const { return tBURST + tWTR; }
157 
158  /*
159  * @return delay between write and read commands
160  */
161  Tick readToWriteDelay() const { return tBURST + tRTW; }
162 
163  /*
164  * @return delay between accesses to different ranks
165  */
166  Tick rankToRankDelay() const { return tBURST + tCS; }
167 
168  public:
169 
176  const uint32_t readBufferSize;
177  const uint32_t writeBufferSize;
178 
184  uint32_t numWritesQueued;
185 
191 
195  uint8_t pseudoChannel;
196 
204  void setCtrl(MemCtrl* _ctrl, unsigned int command_window,
205  uint8_t pseudo_channel = 0);
206 
217 
224  virtual void setupRank(const uint8_t rank, const bool is_read) = 0;
225 
232  virtual bool allRanksDrained() const = 0;
233 
246  chooseNextFRFCFS(MemPacketQueue& queue, Tick min_col_at) const = 0;
247 
248  /*
249  * Function to calulate unloaded latency
250  */
251  virtual Tick accessLatency() const = 0;
252 
256  uint32_t bytesPerBurst() const { return burstSize; }
257 
258  /*
259  * @return time to offset next command
260  */
261  virtual Tick commandOffset() const = 0;
262 
268  virtual bool burstReady(MemPacket* pkt) const = 0;
269 
275  Tick rankDelay() const { return tCS; }
276 
281  Tick minReadToWriteDataGap() const { return std::min(tRTW, tCS); }
282 
287  Tick minWriteToReadDataGap() const { return std::min(tWTR, tCS); }
288 
302  virtual MemPacket* decodePacket(const PacketPtr pkt, Addr pkt_addr,
303  unsigned int size, bool is_read,
304  uint8_t pseudo_channel = 0)
305  {
306  panic("MemInterface decodePacket should not be executed from here.\n");
307  return nullptr;
308  }
309 
317  virtual void addRankToRankDelay(Tick cmd_at) = 0;
318 
322  virtual bool isBusy(bool read_queue_empty, bool all_writes_nvm) = 0;
323 
327  virtual std::pair<Tick, Tick>
328  doBurstAccess(MemPacket* mem_pkt, Tick next_burst_at,
329  const std::vector<MemPacketQueue>& queue) = 0;
330 
334  virtual void respondEvent(uint8_t rank)
335  {
336  panic("MemInterface respondEvent should not be executed from here.\n");
337  };
338 
342  virtual void checkRefreshState(uint8_t rank)
343  {
344  panic("MemInterface checkRefreshState (DRAM) should "
345  "not be executed from here.\n");
346  };
347 
351  virtual void drainRanks()
352  {
353  panic("MemInterface drainRanks (DRAM) should "
354  "not be executed from here.\n");
355  }
356 
360  virtual void suspend()
361  {
362  panic("MemInterface suspend (DRAM) should "
363  "not be executed from here.\n");
364  }
365 
369  virtual bool readsWaitingToIssue() const
370  {
371  panic("MemInterface readsWaitingToIssue (NVM) "
372  "should not be executed from here.\n");
373  };
374 
378  virtual void chooseRead(MemPacketQueue& queue)
379  {
380  panic("MemInterface chooseRead (NVM) should "
381  "not be executed from here.\n");
382  };
383 
387  virtual bool writeRespQueueFull() const
388  {
389  panic("MemInterface writeRespQueueFull (NVM) "
390  "should not be executed from here.\n");
391  }
392 
393  typedef MemInterfaceParams Params;
394  MemInterface(const Params &_p);
395 };
396 
397 
398 } // namespace memory
399 } // namespace gem5
400 
401 #endif //__MEM_INTERFACE_HH__
gem5::memory::MemInterface::rowsPerBank
uint32_t rowsPerBank
Definition: mem_interface.hh:142
gem5::memory::MemInterface::Bank::bank
uint8_t bank
Definition: mem_interface.hh:93
gem5::memory::MemInterface::respondEvent
virtual void respondEvent(uint8_t rank)
This function is DRAM specific.
Definition: mem_interface.hh:334
gem5::memory::MemInterface::readToWriteDelay
Tick readToWriteDelay() const
Definition: mem_interface.hh:161
gem5::memory::MemInterface::readsWaitingToIssue
virtual bool readsWaitingToIssue() const
This function is NVM specific.
Definition: mem_interface.hh:369
gem5::memory::MemInterface::Bank::Bank
Bank()
Definition: mem_interface.hh:104
gem5::memory::MemInterface::numWritesQueued
uint32_t numWritesQueued
NVM specific variable, but declaring it here allows treating different interfaces in a more genral wa...
Definition: mem_interface.hh:184
gem5::memory::MemInterface::suspend
virtual void suspend()
This function is DRAM specific.
Definition: mem_interface.hh:360
gem5::memory::MemInterface::tBURST
const Tick tBURST
Definition: mem_interface.hh:149
memory
Definition: mem.h:38
abstract_mem.hh
gem5::memory::MemInterface::allRanksDrained
virtual bool allRanksDrained() const =0
Check drain state of interface.
gem5::memory::MemInterface::deviceSize
const uint32_t deviceSize
Definition: mem_interface.hh:134
gem5::memory::MemInterface::Bank
A basic class to track the bank state, i.e.
Definition: mem_interface.hh:86
gem5::memory::MemCtrl
The memory controller is a single-channel memory controller capturing the most important timing const...
Definition: mem_ctrl.hh:246
gem5::memory::MemInterface::burstsPerStripe
const uint32_t burstsPerStripe
Definition: mem_interface.hh:139
gem5::memory::MemInterface::addRankToRankDelay
virtual void addRankToRankDelay(Tick cmd_at)=0
Add rank to rank delay to bus timing to all banks in all ranks when access to an alternate interface ...
gem5::memory::MemInterface::Bank::wrAllowedAt
Tick wrAllowedAt
Definition: mem_interface.hh:97
gem5::memory::MemInterface::tCS
const Tick tCS
Definition: mem_interface.hh:148
std::vector
STL vector class.
Definition: stl.hh:37
gem5::memory::MemInterface::Bank::rowAccesses
uint32_t rowAccesses
Definition: mem_interface.hh:101
gem5::memory::MemInterface::Bank::preAllowedAt
Tick preAllowedAt
Definition: mem_interface.hh:98
GEM5_CLASS_VAR_USED
#define GEM5_CLASS_VAR_USED
Definition: compiler.hh:141
gem5::memory::MemInterface::burstsPerRowBuffer
const uint32_t burstsPerRowBuffer
Definition: mem_interface.hh:138
gem5::memory::MemInterface::chooseRead
virtual void chooseRead(MemPacketQueue &queue)
This function is NVM specific.
Definition: mem_interface.hh:378
gem5::memory::MemInterface::readBufferSize
const uint32_t readBufferSize
Buffer sizes for read and write queues in the controller These are passed to the controller on instan...
Definition: mem_interface.hh:176
gem5::memory::MemInterface::MemInterface
MemInterface(const Params &_p)
Definition: mem_interface.cc:54
gem5::memory::MemInterface::minWriteToReadDataGap
Tick minWriteToReadDataGap() const
Definition: mem_interface.hh:287
gem5::memory::MemInterface::addrMapping
enums::AddrMap addrMapping
Memory controller configuration initialized based on parameter values.
Definition: mem_interface.hh:126
gem5::memory::MemInterface::drainRanks
virtual void drainRanks()
This function is DRAM specific.
Definition: mem_interface.hh:351
gem5::memory::MemInterface::Bank::bytesAccessed
uint32_t bytesAccessed
Definition: mem_interface.hh:102
gem5::memory::MemInterface::doBurstAccess
virtual std::pair< Tick, Tick > doBurstAccess(MemPacket *mem_pkt, Tick next_burst_at, const std::vector< MemPacketQueue > &queue)=0
This function performs the burst and update stats.
gem5::memory::MemInterface::deviceRowBufferSize
const uint32_t deviceRowBufferSize
Definition: mem_interface.hh:135
gem5::memory::MemInterface::Bank::rdAllowedAt
Tick rdAllowedAt
Definition: mem_interface.hh:96
gem5::memory::MemInterface
General interface to memory device Includes functions and parameters shared across media types.
Definition: mem_interface.hh:74
gem5::memory::MemInterface::isBusy
virtual bool isBusy(bool read_queue_empty, bool all_writes_nvm)=0
This function checks if ranks are busy.
gem5::memory::MemInterface::setupRank
virtual void setupRank(const uint8_t rank, const bool is_read)=0
Setup the rank based on packet received.
gem5::memory::MemInterface::banksPerRank
const uint32_t banksPerRank
Definition: mem_interface.hh:141
gem5::memory::MemInterface::Bank::bankgr
uint8_t bankgr
Definition: mem_interface.hh:94
gem5::Packet
A Packet is used to encapsulate a transfer between two objects in the memory system (e....
Definition: packet.hh:291
statistics.hh
gem5::memory::AbstractMemory
An abstract memory represents a contiguous block of physical memory, with an associated address range...
Definition: abstract_mem.hh:110
gem5::Tick
uint64_t Tick
Tick count type.
Definition: types.hh:58
gem5::memory::MemPacket
A memory packet stores packets along with the timestamp of when the packet entered the queue,...
Definition: mem_ctrl.hh:98
gem5::memory::MemInterface::commandOffset
virtual Tick commandOffset() const =0
gem5::memory::MemInterface::burstReady
virtual bool burstReady(MemPacket *pkt) const =0
Check if a burst operation can be issued to the interface.
gem5::memory::MemInterface::rankDelay
Tick rankDelay() const
Determine the required delay for an access to a different rank.
Definition: mem_interface.hh:275
gem5::memory::MemInterface::checkRefreshState
virtual void checkRefreshState(uint8_t rank)
This function is DRAM specific.
Definition: mem_interface.hh:342
gem5::memory::MemInterface::writeBufferSize
const uint32_t writeBufferSize
Definition: mem_interface.hh:177
gem5::memory::MemInterface::devicesPerRank
const uint32_t devicesPerRank
Definition: mem_interface.hh:136
compiler.hh
mem_ctrl.hh
gem5::memory::MemInterface::minReadToWriteDataGap
Tick minReadToWriteDataGap() const
Definition: mem_interface.hh:281
std::pair
STL pair class.
Definition: stl.hh:58
gem5::memory::MemInterface::ctrl
MemCtrl * ctrl
A pointer to the parent memory controller instance.
Definition: mem_interface.hh:114
gem5::memory::MemInterface::tWTR
const Tick tWTR
Definition: mem_interface.hh:151
gem5::memory::AbstractMemory::range
AddrRange range
Definition: abstract_mem.hh:115
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::memory::MemInterface::Params
MemInterfaceParams Params
Definition: mem_interface.hh:393
gem5::memory::MemInterface::rankToRankDelay
Tick rankToRankDelay() const
Definition: mem_interface.hh:166
gem5::memory::MemInterface::writeToReadDelay
virtual Tick writeToReadDelay() const
Definition: mem_interface.hh:156
gem5::memory::MemInterface::nextBurstAt
Tick nextBurstAt
Till when the controller must wait before issuing next RD/WR burst?
Definition: mem_interface.hh:189
gem5::memory::MemInterface::Bank::openRow
uint32_t openRow
Definition: mem_interface.hh:92
gem5::memory::MemInterface::tRTW
const Tick tRTW
Definition: mem_interface.hh:150
gem5::memory::AbstractMemory::size
uint64_t size() const
Get the memory size.
Definition: abstract_mem.hh:301
gem5::memory::MemInterface::ranksPerChannel
const uint32_t ranksPerChannel
Definition: mem_interface.hh:140
gem5::memory::MemInterface::setCtrl
void setCtrl(MemCtrl *_ctrl, unsigned int command_window, uint8_t pseudo_channel=0)
Set a pointer to the controller and initialize interface based on controller parameters.
Definition: mem_interface.cc:77
gem5::AddrRange::getOffset
Addr getOffset(const Addr &a) const
Determine the offset of an address within the range.
Definition: addr_range.hh:611
std::deque
STL deque class.
Definition: stl.hh:44
gem5::memory::MemInterface::nextReqTime
Tick nextReqTime
Definition: mem_interface.hh:190
gem5::memory::MemInterface::chooseNextFRFCFS
virtual std::pair< MemPacketQueue::iterator, Tick > chooseNextFRFCFS(MemPacketQueue &queue, Tick min_col_at) const =0
For FR-FCFS policy, find first command that can issue Function will be overriden by interface to sele...
gem5::memory::MemInterface::rowBufferSize
const uint32_t rowBufferSize
Definition: mem_interface.hh:137
gem5::memory::MemInterface::getCtrlAddr
Addr getCtrlAddr(Addr addr)
Get an address in a dense range which starts from 0.
Definition: mem_interface.hh:216
gem5::memory::MemInterface::pseudoChannel
uint8_t pseudoChannel
pseudo channel number used for HBM modeling
Definition: mem_interface.hh:195
gem5::memory::MemInterface::Bank::NO_ROW
static const uint32_t NO_ROW
Definition: mem_interface.hh:90
gem5::memory::MemInterface::bytesPerBurst
uint32_t bytesPerBurst() const
Definition: mem_interface.hh:256
gem5::memory::MemInterface::Bank::actAllowedAt
Tick actAllowedAt
Definition: mem_interface.hh:99
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: gpu_translation_state.hh:37
gem5::memory::MemInterface::writeRespQueueFull
virtual bool writeRespQueueFull() const
This function is NVM specific.
Definition: mem_interface.hh:387
gem5::memory::MemInterface::maxCommandsPerWindow
unsigned int maxCommandsPerWindow
Number of commands that can issue in the defined controller command window, used to verify command ba...
Definition: mem_interface.hh:120
gem5::memory::MemInterface::accessLatency
virtual Tick accessLatency() const =0
gem5::memory::MemInterface::burstSize
const uint32_t burstSize
General device and channel characteristics The rowsPerBank is determined based on the capacity,...
Definition: mem_interface.hh:133
gem5::memory::MemInterface::tCK
const GEM5_CLASS_VAR_USED Tick tCK
General timing requirements.
Definition: mem_interface.hh:147
gem5::memory::MemInterface::decodePacket
virtual MemPacket * decodePacket(const PacketPtr pkt, Addr pkt_addr, unsigned int size, bool is_read, uint8_t pseudo_channel=0)
Address decoder to figure out physical mapping onto ranks, banks, and rows.
Definition: mem_interface.hh:302
panic
#define panic(...)
This implements a cprintf based panic() function.
Definition: logging.hh:178
gem5::X86ISA::addr
Bitfield< 3 > addr
Definition: types.hh:84
eventq.hh

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