gem5  v21.1.0.2
thread_context.cc
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27 
29 
31 #include "arch/arm/utility.hh"
32 #include "iris/detail/IrisCppAdapter.h"
33 #include "iris/detail/IrisObjects.h"
34 
35 namespace gem5
36 {
37 
38 GEM5_DEPRECATED_NAMESPACE(FastModel, fastmodel);
39 namespace fastmodel
40 {
41 
43  gem5::BaseCPU *cpu, int id, System *system, gem5::BaseMMU *mmu,
44  gem5::BaseISA *isa, iris::IrisConnectionInterface *iris_if,
45  const std::string &iris_path) :
46  ThreadContext(cpu, id, system, mmu, isa, iris_if, iris_path)
47 {}
48 
49 bool
51 {
52  // Determine what memory spaces are currently active.
53  Iris::CanonicalMsn in_msn;
54  switch (ArmISA::currEL(this)) {
55  case ArmISA::EL3:
56  in_msn = Iris::SecureMonitorMsn;
57  break;
58  case ArmISA::EL2:
59  in_msn = Iris::NsHypMsn;
60  break;
61  default:
62  in_msn = Iris::GuestMsn;
63  break;
64  }
65 
66  Iris::CanonicalMsn out_msn = ArmISA::isSecure(this) ?
68 
69  // Figure out what memory spaces match the canonical numbers we need.
70  iris::MemorySpaceId in = iris::IRIS_UINT64_MAX;
71  iris::MemorySpaceId out = iris::IRIS_UINT64_MAX;
72 
73  for (auto &space: memorySpaces) {
74  if (space.canonicalMsn == in_msn)
75  in = space.spaceId;
76  else if (space.canonicalMsn == out_msn)
77  out = space.spaceId;
78  }
79 
80  panic_if(in == iris::IRIS_UINT64_MAX || out == iris::IRIS_UINT64_MAX,
81  "Canonical IRIS memory space numbers not found.");
82 
83  return ThreadContext::translateAddress(paddr, out, vaddr, in);
84 }
85 
86 void
88 {
89  ThreadContext::initFromIrisInstance(resources);
90 
91  pcRscId = extractResourceId(resources, "R15");
92 
95 }
96 
97 RegVal
99 {
100  iris::ResourceReadResult result;
101  call().resource_read(_instId, result, intReg32Ids.at(reg_idx));
102  return result.data.at(0);
103 }
104 
105 void
107 {
108  iris::ResourceWriteResult result;
109  call().resource_write(_instId, result, intReg32Ids.at(reg_idx), val);
110 }
111 
112 RegVal
114 {
116  switch (idx) {
117  case ArmISA::CCREG_NZ:
118  result = ((ArmISA::CPSR)result).nz;
119  break;
120  case ArmISA::CCREG_FP:
121  result = bits(result, 31, 28);
122  break;
123  default:
124  break;
125  }
126  return result;
127 }
128 
129 void
131 {
132  switch (idx) {
133  case ArmISA::CCREG_NZ:
134  {
135  ArmISA::CPSR cpsr = readMiscRegNoEffect(ArmISA::MISCREG_CPSR);
136  cpsr.nz = val;
137  val = cpsr;
138  }
139  break;
140  case ArmISA::CCREG_FP:
141  {
142  ArmISA::FPSCR fpscr = readMiscRegNoEffect(ArmISA::MISCREG_FPSCR);
143  val = insertBits(fpscr, 31, 28, val);
144  }
145  break;
146  default:
147  break;
148  }
150 }
151 
154 {
155  if (bpSpaceIds.empty()) {
156  for (auto &space: memorySpaces) {
157  auto cmsn = space.canonicalMsn;
158  if (cmsn == Iris::SecureMonitorMsn ||
159  cmsn == Iris::GuestMsn ||
160  cmsn == Iris::NsHypMsn ||
161  cmsn == Iris::HypAppMsn) {
162  bpSpaceIds.push_back(space.spaceId);
163  }
164  }
165  panic_if(bpSpaceIds.empty(),
166  "Unable to find address space(s) for breakpoints.");
167  }
168  return bpSpaceIds;
169 }
170 
172  { ArmISA::INTREG_R0, "R0" },
173  { ArmISA::INTREG_R1, "R1" },
174  { ArmISA::INTREG_R2, "R2" },
175  { ArmISA::INTREG_R3, "R3" },
176  { ArmISA::INTREG_R4, "R4" },
177  { ArmISA::INTREG_R5, "R5" },
178  { ArmISA::INTREG_R6, "R6" },
179  { ArmISA::INTREG_R7, "R7" },
180  { ArmISA::INTREG_R8, "R8" },
181  { ArmISA::INTREG_R9, "R9" },
182  { ArmISA::INTREG_R10, "R10" },
183  { ArmISA::INTREG_R11, "R11" },
184  { ArmISA::INTREG_R12, "R12" },
185  { ArmISA::INTREG_R13, "R13" },
186  { ArmISA::INTREG_R14, "R14" },
187  { ArmISA::INTREG_R15, "R15" }
188 });
189 
191  { ArmISA::CCREG_NZ, "CPSR" },
192  { ArmISA::CCREG_C, "CPSR.C" },
193  { ArmISA::CCREG_V, "CPSR.V" },
194  { ArmISA::CCREG_GE, "CPSR.GE" },
195  { ArmISA::CCREG_FP, "FPSCR" },
196 });
197 
199 
200 } // namespace fastmodel
201 } // namespace gem5
gem5::ArmISA::MISCREG_CPSR
@ MISCREG_CPSR
Definition: misc.hh:61
gem5::fastmodel::CortexR52TC::intReg32IdxNameMap
static IdxNameMap intReg32IdxNameMap
Definition: thread_context.hh:45
gem5::ArmISA::CCREG_C
@ CCREG_C
Definition: cc.hh:50
gem5::Iris::ThreadContext::IdxNameMap
std::map< int, std::string > IdxNameMap
Definition: thread_context.hh:57
gem5::Iris::PhysicalMemoryNonSecureMsn
@ PhysicalMemoryNonSecureMsn
Definition: memory_spaces.hh:48
gem5::fastmodel::CortexR52TC::readIntReg
RegVal readIntReg(RegIndex reg_idx) const override
Definition: thread_context.cc:98
gem5::Iris::PhysicalMemorySecureMsn
@ PhysicalMemorySecureMsn
Definition: memory_spaces.hh:47
gem5::RegVal
uint64_t RegVal
Definition: types.hh:173
memory_spaces.hh
gem5::ArmISA::CCREG_NZ
@ CCREG_NZ
Definition: cc.hh:49
gem5::fastmodel::CortexR52TC::translateAddress
bool translateAddress(Addr &paddr, Addr vaddr) override
Definition: thread_context.cc:50
gem5::Iris::ThreadContext::call
iris::IrisCppAdapter & call() const
Definition: thread_context.hh:165
gem5::ArmISA::currEL
static ExceptionLevel currEL(const ThreadContext *tc)
Definition: utility.hh:119
gem5::X86ISA::val
Bitfield< 63 > val
Definition: misc.hh:775
gem5::fastmodel::CortexR52TC::ccRegIdxNameMap
static IdxNameMap ccRegIdxNameMap
Definition: thread_context.hh:46
gem5::Iris::SecureMonitorMsn
@ SecureMonitorMsn
Definition: memory_spaces.hh:39
gem5::X86ISA::system
Bitfield< 15 > system
Definition: misc.hh:1003
std::vector< iris::MemorySpaceId >
gem5::fastmodel::CortexR52TC::CortexR52TC
CortexR52TC(gem5::BaseCPU *cpu, int id, System *system, gem5::BaseMMU *mmu, gem5::BaseISA *isa, iris::IrisConnectionInterface *iris_if, const std::string &iris_path)
Definition: thread_context.cc:42
gem5::Iris::HypAppMsn
@ HypAppMsn
Definition: memory_spaces.hh:43
gem5::Iris::ThreadContext::memorySpaces
std::vector< iris::MemorySpaceInfo > memorySpaces
Definition: thread_context.hh:98
gem5::BaseMMU
Definition: mmu.hh:50
gem5::Iris::GuestMsn
@ GuestMsn
Definition: memory_spaces.hh:40
gem5::System
Definition: system.hh:77
gem5::fastmodel::CortexR52TC::bpSpaceIds
static std::vector< iris::MemorySpaceId > bpSpaceIds
Definition: thread_context.hh:47
gem5::ThreadContext
ThreadContext is the external interface to all thread state for anything outside of the CPU.
Definition: thread_context.hh:93
gem5::ArmISA::EL2
@ EL2
Definition: types.hh:268
gem5::Iris::ThreadContext::readCCRegFlat
RegVal readCCRegFlat(RegIndex idx) const override
Definition: thread_context.cc:641
thread_context.hh
gem5::fastmodel::CortexR52TC::readCCRegFlat
RegVal readCCRegFlat(RegIndex idx) const override
Definition: thread_context.cc:113
gem5::BaseCPU
Definition: base.hh:107
gem5::Iris::ThreadContext::extractResourceMap
void extractResourceMap(ResourceIds &ids, const ResourceMap &resources, const IdxNameMap &idx_names)
Definition: thread_context.cc:104
gem5::Iris::ThreadContext::ccRegIds
ResourceIds ccRegIds
Definition: thread_context.hh:90
gem5::insertBits
constexpr T insertBits(T val, unsigned first, unsigned last, B bit_val)
Returns val with bits first to last set to the LSBs of bit_val.
Definition: bitfield.hh:166
gem5::bits
constexpr T bits(T val, unsigned first, unsigned last)
Extract the bitfield from position 'first' to 'last' (inclusive) from 'val' and right justify it.
Definition: bitfield.hh:76
gem5::ArmISA::EL3
@ EL3
Definition: types.hh:269
gem5::fastmodel::CortexR52TC::readMiscRegNoEffect
RegVal readMiscRegNoEffect(RegIndex) const override
Definition: thread_context.hh:77
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::GEM5_DEPRECATED_NAMESPACE
GEM5_DEPRECATED_NAMESPACE(GuestABI, guest_abi)
gem5::fastmodel::CortexR52TC::getBpSpaceIds
const std::vector< iris::MemorySpaceId > & getBpSpaceIds() const override
Definition: thread_context.cc:153
gem5::Iris::ThreadContext::extractResourceId
iris::ResourceId extractResourceId(const ResourceMap &resources, const std::string &name)
Definition: thread_context.cc:97
gem5::ArmISA::isSecure
bool isSecure(ThreadContext *tc)
Definition: utility.cc:72
gem5::ArmISA::CCREG_GE
@ CCREG_GE
Definition: cc.hh:52
utility.hh
gem5::fastmodel::CortexR52TC::setIntReg
void setIntReg(RegIndex reg_idx, RegVal val) override
Definition: thread_context.cc:106
gem5::Iris::ThreadContext::setCCRegFlat
void setCCRegFlat(RegIndex idx, RegVal val) override
Definition: thread_context.cc:651
gem5::ArmISA::CCREG_FP
@ CCREG_FP
Definition: cc.hh:53
panic_if
#define panic_if(cond,...)
Conditional panic macro that checks the supplied condition and only panics if the condition is true a...
Definition: logging.hh:203
gem5::Iris::ThreadContext::intReg32Ids
ResourceIds intReg32Ids
Definition: thread_context.hh:87
gem5::fastmodel::CortexR52TC::initFromIrisInstance
void initFromIrisInstance(const ResourceMap &resources) override
Definition: thread_context.cc:87
gem5::Iris::ThreadContext::ResourceMap
std::map< std::string, iris::ResourceInfo > ResourceMap
Definition: thread_context.hh:54
gem5::ArmISA::MISCREG_FPSCR
@ MISCREG_FPSCR
Definition: misc.hh:72
gem5::Iris::NsHypMsn
@ NsHypMsn
Definition: memory_spaces.hh:41
gem5::ArmISA::id
Bitfield< 33 > id
Definition: misc_types.hh:250
gem5::fastmodel::CortexR52TC::setCCRegFlat
void setCCRegFlat(RegIndex idx, RegVal val) override
Definition: thread_context.cc:130
gem5::Iris::ThreadContext::pcRscId
iris::ResourceId pcRscId
Definition: thread_context.hh:92
gem5::MipsISA::vaddr
vaddr
Definition: pra_constants.hh:278
gem5::BaseISA
Definition: isa.hh:54
gem5::RegIndex
uint16_t RegIndex
Definition: types.hh:176
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40
gem5::ArmISA::CCREG_V
@ CCREG_V
Definition: cc.hh:51
gem5::Iris::CanonicalMsn
CanonicalMsn
Definition: memory_spaces.hh:37
gem5::Iris::ThreadContext::_instId
iris::InstanceId _instId
Definition: thread_context.hh:68

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