gem5  v22.0.0.2
armv8_cpu.cc
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37 
39 
40 #include <linux/kvm.h>
41 
42 #include "debug/KvmContext.hh"
43 #include "params/ArmV8KvmCPU.hh"
44 
45 namespace gem5
46 {
47 
48 using namespace ArmISA;
49 
50 // Unlike gem5, kvm doesn't count the SP as a normal integer register,
51 // which means we only have 31 normal integer registers.
52 constexpr static unsigned NUM_XREGS = int_reg::NumArchRegs - 1;
53 static_assert(NUM_XREGS == 31, "Unexpected number of aarch64 int. regs.");
54 
55 // The KVM interface accesses vector registers of 4 single precision
56 // floats instead of individual registers.
57 constexpr static unsigned NUM_QREGS = NumVecV8ArchRegs;
58 static_assert(NUM_QREGS == 32, "Unexpected number of aarch64 vector regs.");
59 
60 #define EXTRACT_FIELD(v, name) \
61  (((v) & name ## _MASK) >> name ## _SHIFT)
62 
63 #define CORE_REG(name, size) \
64  (KVM_REG_ARM64 | KVM_REG_ARM_CORE | \
65  KVM_REG_SIZE_ ## size | \
66  KVM_REG_ARM_CORE_REG(name))
67 
68 #define INT_REG(name) CORE_REG(name, U64)
69 #define SIMD_REG(name) CORE_REG(name, U128)
70 
71 #define SYS_MPIDR_EL1 ARM64_SYS_REG(0b11, 0b000, 0b0000, 0b0000, 0b101)
72 
73 constexpr uint64_t
74 kvmXReg(const int num)
75 {
76  return INT_REG(regs.regs[0]) +
77  (INT_REG(regs.regs[1]) - INT_REG(regs.regs[0])) * num;
78 }
79 
80 constexpr uint64_t
81 kvmFPReg(const int num)
82 {
83  return SIMD_REG(fp_regs.vregs[0]) +
84  (SIMD_REG(fp_regs.vregs[1]) - SIMD_REG(fp_regs.vregs[0])) * num;
85 }
86 
87 union KvmFPReg
88 {
89  union
90  {
91  uint32_t i;
92  float f;
93  } s[4];
94 
95  union
96  {
97  uint64_t i;
98  double f;
99  } d[2];
100 
101  uint8_t data[32];
102 };
103 
104 #define FP_REGS_PER_VFP_REG 4
105 
107  { INT_REG(regs.sp), int_reg::Sp0, "SP(EL0)" },
108  { INT_REG(sp_el1), int_reg::Sp1, "SP(EL1)" },
109 };
110 
112  MiscRegInfo(INT_REG(elr_el1), MISCREG_ELR_EL1, "ELR(EL1)"),
113  MiscRegInfo(INT_REG(spsr[KVM_SPSR_EL1]), MISCREG_SPSR_EL1, "SPSR(EL1)"),
114  MiscRegInfo(INT_REG(spsr[KVM_SPSR_ABT]), MISCREG_SPSR_ABT, "SPSR(ABT)"),
115  MiscRegInfo(INT_REG(spsr[KVM_SPSR_UND]), MISCREG_SPSR_UND, "SPSR(UND)"),
116  MiscRegInfo(INT_REG(spsr[KVM_SPSR_IRQ]), MISCREG_SPSR_IRQ, "SPSR(IRQ)"),
117  MiscRegInfo(INT_REG(spsr[KVM_SPSR_FIQ]), MISCREG_SPSR_FIQ, "SPSR(FIQ)"),
118  MiscRegInfo(CORE_REG(fp_regs.fpsr, U32), MISCREG_FPSR, "FPSR"),
119  MiscRegInfo(CORE_REG(fp_regs.fpcr, U32), MISCREG_FPCR, "FPCR"),
120 };
121 
122 const std::set<MiscRegIndex> ArmV8KvmCPU::deviceRegSet = {
126 };
127 
130 };
131 
132 ArmV8KvmCPU::ArmV8KvmCPU(const ArmV8KvmCPUParams &params)
133  : BaseArmKvmCPU(params)
134 {
135 }
136 
138 {
139 }
140 
141 void
143 {
145 
146  // Override ID registers that KVM should "inherit" from gem5.
147  for (const auto &ri : miscRegIdMap) {
148  const uint64_t value(tc->readMiscReg(ri.idx));
149  DPRINTF(KvmContext, " %s := 0x%x\n", ri.name, value);
150  setOneReg(ri.kvm, value);
151  }
152 }
153 
154 void
156 {
157  inform("Integer registers:\n");
158  inform(" PC: %s\n", getAndFormatOneReg(INT_REG(regs.pc)));
159  for (int i = 0; i < NUM_XREGS; ++i)
160  inform(" X%i: %s\n", i, getAndFormatOneReg(kvmXReg(i)));
161 
162  for (int i = 0; i < NUM_QREGS; ++i)
163  inform(" Q%i: %s\n", i, getAndFormatOneReg(kvmFPReg(i)));
164 
165  for (const auto &ri : intRegMap)
166  inform(" %s: %s\n", ri.name, getAndFormatOneReg(ri.kvm));
167 
168  inform(" %s: %s\n", "PSTATE", getAndFormatOneReg(INT_REG(regs.pstate)));
169 
170  for (const auto &ri : miscRegMap)
171  inform(" %s: %s\n", ri.name, getAndFormatOneReg(ri.kvm));
172 
173  for (const auto &ri : miscRegIdMap)
174  inform(" %s: %s\n", ri.name, getAndFormatOneReg(ri.kvm));
175 
176  for (const auto &reg : getRegList()) {
177  const uint64_t arch(reg & KVM_REG_ARCH_MASK);
178  if (arch != KVM_REG_ARM64) {
179  inform("0x%x: %s\n", reg, getAndFormatOneReg(reg));
180  continue;
181  }
182 
183  const uint64_t type(reg & KVM_REG_ARM_COPROC_MASK);
184  switch (type) {
185  case KVM_REG_ARM_CORE:
186  // These have already been printed
187  break;
188 
189  case KVM_REG_ARM64_SYSREG: {
190  const uint64_t op0(EXTRACT_FIELD(reg, KVM_REG_ARM64_SYSREG_OP0));
191  const uint64_t op1(EXTRACT_FIELD(reg, KVM_REG_ARM64_SYSREG_OP1));
192  const uint64_t crn(EXTRACT_FIELD(reg, KVM_REG_ARM64_SYSREG_CRN));
193  const uint64_t crm(EXTRACT_FIELD(reg, KVM_REG_ARM64_SYSREG_CRM));
194  const uint64_t op2(EXTRACT_FIELD(reg, KVM_REG_ARM64_SYSREG_OP2));
195  const MiscRegIndex idx(
196  decodeAArch64SysReg(op0, op1, crn, crm, op2));
197 
198  inform(" %s (op0: %i, op1: %i, crn: %i, crm: %i, op2: %i): %s",
199  miscRegName[idx], op0, op1, crn, crm, op2,
201  } break;
202 
203  case KVM_REG_ARM_DEMUX: {
204  const uint64_t id(EXTRACT_FIELD(reg, KVM_REG_ARM_DEMUX_ID));
205  const uint64_t val(EXTRACT_FIELD(reg, KVM_REG_ARM_DEMUX_VAL));
206  if (id == KVM_REG_ARM_DEMUX_ID_CCSIDR) {
207  inform(" CSSIDR[%i]: %s\n", val,
209  } else {
210  inform(" UNKNOWN[%i:%i]: %s\n", id, val,
212  }
213  } break;
214 
215  default:
216  inform("0x%x: %s\n", reg, getAndFormatOneReg(reg));
217  }
218  }
219 }
220 
221 void
223 {
224  DPRINTF(KvmContext, "In updateKvmState():\n");
225 
226  // update pstate register state
227  CPSR cpsr(tc->readMiscReg(MISCREG_CPSR));
228  cpsr.nz = tc->getReg(cc_reg::Nz);
229  cpsr.c = tc->getReg(cc_reg::C);
230  cpsr.v = tc->getReg(cc_reg::V);
231  if (cpsr.width) {
232  cpsr.ge = tc->getReg(cc_reg::Ge);
233  } else {
234  cpsr.ge = 0;
235  }
236  DPRINTF(KvmContext, " %s := 0x%x\n", "PSTATE", cpsr);
237  setOneReg(INT_REG(regs.pstate), static_cast<uint64_t>(cpsr));
238 
239  for (const auto &ri : miscRegMap) {
240  const uint64_t value(tc->readMiscReg(ri.idx));
241  DPRINTF(KvmContext, " %s := 0x%x\n", ri.name, value);
242  setOneReg(ri.kvm, value);
243  }
244 
245  for (int i = 0; i < NUM_XREGS; ++i) {
246  const uint64_t value = tc->getReg(int_reg::x(i));
247  DPRINTF(KvmContext, " X%i := 0x%x\n", i, value);
248  setOneReg(kvmXReg(i), value);
249  }
250 
251  for (const auto &ri : intRegMap) {
252  const uint64_t value = tc->getReg(RegId(IntRegClass, ri.idx));
253  DPRINTF(KvmContext, " %s := 0x%x\n", ri.name, value);
254  setOneReg(ri.kvm, value);
255  }
256 
257  for (int i = 0; i < NUM_QREGS; ++i) {
258  KvmFPReg reg;
259  if (!inAArch64(tc))
262  tc->getReg(RegId(VecRegClass, i), &vc);
263  auto v = vc.as<VecElem>();
264  for (int j = 0; j < FP_REGS_PER_VFP_REG; j++)
265  reg.s[j].i = v[j];
266 
267  setOneReg(kvmFPReg(i), reg.data);
268  DPRINTF(KvmContext, " Q%i: %s\n", i, getAndFormatOneReg(kvmFPReg(i)));
269  }
270 
271  for (const auto &ri : getSysRegMap()) {
272  uint64_t value;
273  if (ri.is_device) {
274  // This system register is backed by a device. This means
275  // we need to lock the device event queue.
277 
278  value = tc->readMiscReg(ri.idx);
279  } else {
280  value = tc->readMiscReg(ri.idx);
281  }
282 
283  DPRINTF(KvmContext, " %s := 0x%x\n", ri.name, value);
284  setOneReg(ri.kvm, value);
285  }
286 
287  setOneReg(INT_REG(regs.pc), tc->pcState().instAddr());
288  DPRINTF(KvmContext, " PC := 0x%x\n", tc->pcState().instAddr());
289 }
290 
291 void
293 {
294  DPRINTF(KvmContext, "In updateThreadContext():\n");
295 
296  // Update pstate thread context
297  const CPSR cpsr(getOneRegU64(INT_REG(regs.pstate)));
298  DPRINTF(KvmContext, " %s := 0x%x\n", "PSTATE", cpsr);
300  tc->setReg(cc_reg::Nz, cpsr.nz);
301  tc->setReg(cc_reg::C, cpsr.c);
302  tc->setReg(cc_reg::V, cpsr.v);
303  if (cpsr.width) {
304  tc->setReg(cc_reg::Ge, cpsr.ge);
305  }
306 
307  // Update core misc regs first as they
308  // affect how other registers are mapped.
309  for (const auto &ri : miscRegMap) {
310  const auto value(getOneRegU64(ri.kvm));
311  DPRINTF(KvmContext, " %s := 0x%x\n", ri.name, value);
312  tc->setMiscRegNoEffect(ri.idx, value);
313  }
314 
315  for (int i = 0; i < NUM_XREGS; ++i) {
316  const auto value(getOneRegU64(kvmXReg(i)));
317  DPRINTF(KvmContext, " X%i := 0x%x\n", i, value);
318  // KVM64 returns registers in 64-bit layout. If we are in aarch32
319  // mode, we need to map these to banked ARM32 registers.
320  if (inAArch64(tc)) {
321  tc->setReg(int_reg::x(i), value);
322  } else {
323  tc->setRegFlat(int_reg::x(i), value);
324  }
325  }
326 
327  for (const auto &ri : intRegMap) {
328  const auto value(getOneRegU64(ri.kvm));
329  DPRINTF(KvmContext, " %s := 0x%x\n", ri.name, value);
330  tc->setReg(RegId(IntRegClass, ri.idx), value);
331  }
332 
333  for (int i = 0; i < NUM_QREGS; ++i) {
334  KvmFPReg reg;
335  DPRINTF(KvmContext, " Q%i: %s\n", i, getAndFormatOneReg(kvmFPReg(i)));
336  getOneReg(kvmFPReg(i), reg.data);
337  auto v = tc->getWritableVecReg(RegId(VecRegClass, i)).as<VecElem>();
338  for (int j = 0; j < FP_REGS_PER_VFP_REG; j++)
339  v[j] = reg.s[j].i;
340  if (!inAArch64(tc))
342  }
343 
344  for (const auto &ri : getSysRegMap()) {
345  const auto value(getOneRegU64(ri.kvm));
346  DPRINTF(KvmContext, " %s := 0x%x\n", ri.name, value);
347  if (ri.is_device) {
348  // This system register is backed by a device. This means
349  // we need to lock the device event queue.
351 
352  tc->setMiscReg(ri.idx, value);
353  } else {
354  tc->setMiscRegNoEffect(ri.idx, value);
355  }
356  }
357 
358  PCState pc(getOneRegU64(INT_REG(regs.pc)));
359  pc.aarch64(inAArch64(tc));
360  pc.thumb(cpsr.t);
361  pc.nextAArch64(inAArch64(tc));
362  // TODO: This is a massive assumption that will break when
363  // switching to thumb.
364  pc.nextThumb(cpsr.t);
365  DPRINTF(KvmContext, " PC := 0x%x (t: %i, a64: %i)\n",
366  pc.instAddr(), pc.thumb(), pc.aarch64());
367  tc->pcState(pc);
368 }
369 
372 {
373  // Try to use the cached map
374  if (!sysRegMap.empty())
375  return sysRegMap;
376 
377  for (const auto &reg : getRegList()) {
378  const uint64_t arch(reg & KVM_REG_ARCH_MASK);
379  if (arch != KVM_REG_ARM64)
380  continue;
381 
382  const uint64_t type(reg & KVM_REG_ARM_COPROC_MASK);
383  if (type != KVM_REG_ARM64_SYSREG)
384  continue;
385 
386  const uint64_t op0(EXTRACT_FIELD(reg, KVM_REG_ARM64_SYSREG_OP0));
387  const uint64_t op1(EXTRACT_FIELD(reg, KVM_REG_ARM64_SYSREG_OP1));
388  const uint64_t crn(EXTRACT_FIELD(reg, KVM_REG_ARM64_SYSREG_CRN));
389  const uint64_t crm(EXTRACT_FIELD(reg, KVM_REG_ARM64_SYSREG_CRM));
390  const uint64_t op2(EXTRACT_FIELD(reg, KVM_REG_ARM64_SYSREG_OP2));
391  const MiscRegIndex idx(decodeAArch64SysReg(op0, op1, crn, crm, op2));
392  const auto &info(miscRegInfo[idx]);
393  const bool writeable(
394  info[MISCREG_USR_NS_WR] || info[MISCREG_USR_S_WR] ||
395  info[MISCREG_PRI_S_WR] || info[MISCREG_PRI_NS_WR] ||
396  info[MISCREG_HYP_NS_WR] ||
397  info[MISCREG_MON_NS0_WR] || info[MISCREG_MON_NS1_WR]);
398  const bool implemented(
400 
401  // Only add implemented registers that we are going to be able
402  // to write.
403  if (implemented && writeable)
404  sysRegMap.emplace_back(reg, idx, miscRegName[idx],
405  deviceRegSet.find(idx) != deviceRegSet.end());
406  }
407 
408  return sysRegMap;
409 }
410 
411 } // namespace gem5
gem5::ArmISA::MISCREG_PRI_S_WR
@ MISCREG_PRI_S_WR
Definition: misc.hh:1129
gem5::ArmISA::MISCREG_CPSR
@ MISCREG_CPSR
Definition: misc.hh:61
gem5::ArmISA::MISCREG_USR_NS_WR
@ MISCREG_USR_NS_WR
Definition: misc.hh:1122
gem5::PCStateBase::instAddr
Addr instAddr() const
Returns the memory address of the instruction this PC points to.
Definition: pcstate.hh:107
gem5::ThreadContext::readMiscReg
virtual RegVal readMiscReg(RegIndex misc_reg)=0
gem5::ArmV8KvmCPU::startup
void startup() override
Definition: armv8_cpu.cc:142
INT_REG
#define INT_REG(name)
Definition: armv8_cpu.cc:68
gem5::ArmV8KvmCPU::miscRegMap
static const std::vector< ArmV8KvmCPU::MiscRegInfo > miscRegMap
Mapping between gem5 misc registers and registers in kvm.
Definition: armv8_cpu.hh:143
data
const char data[]
Definition: circlebuf.test.cc:48
gem5::ArmISA::MISCREG_CNTV_CTL_EL0
@ MISCREG_CNTV_CTL_EL0
Definition: misc.hh:760
gem5::ArmISA::MISCREG_SPSR_FIQ
@ MISCREG_SPSR_FIQ
Definition: misc.hh:63
gem5::ThreadContext::getReg
virtual RegVal getReg(const RegId &reg) const
Definition: thread_context.cc:171
gem5::BaseKvmCPU::deviceEventQueue
EventQueue * deviceEventQueue()
Get a pointer to the event queue owning devices.
Definition: base.hh:447
gem5::KvmFPReg
Definition: armv8_cpu.cc:87
gem5::ArmISA::MISCREG_MON_NS0_WR
@ MISCREG_MON_NS0_WR
Definition: misc.hh:1142
gem5::ThreadContext::pcState
virtual const PCStateBase & pcState() const =0
gem5::ArmISA::MISCREG_PRI_NS_WR
@ MISCREG_PRI_NS_WR
Definition: misc.hh:1127
gem5::ArmV8KvmCPU::updateThreadContext
void updateThreadContext() override
Update the current thread context with the KVM state.
Definition: armv8_cpu.cc:292
gem5::X86ISA::val
Bitfield< 63 > val
Definition: misc.hh:769
SYS_MPIDR_EL1
#define SYS_MPIDR_EL1
Definition: armv8_cpu.cc:71
gem5::ArmISA::decodeAArch64SysReg
MiscRegIndex decodeAArch64SysReg(unsigned op0, unsigned op1, unsigned crn, unsigned crm, unsigned op2)
Definition: misc.cc:1295
gem5::ArmISA::miscRegName
const char *const miscRegName[]
Definition: misc.hh:1273
gem5::ArmV8KvmCPU::miscRegIdMap
static const std::vector< ArmV8KvmCPU::MiscRegInfo > miscRegIdMap
Mapping between gem5 ID misc registers and registers in kvm.
Definition: armv8_cpu.hh:147
gem5::BaseKvmCPU::getAndFormatOneReg
std::string getAndFormatOneReg(uint64_t id) const
Get and format one register for printout.
Definition: base.cc:889
std::vector
STL vector class.
Definition: stl.hh:37
gem5::ArmISA::inAArch64
bool inAArch64(ThreadContext *tc)
Definition: utility.cc:122
gem5::BaseKvmCPU::getOneReg
void getOneReg(uint64_t id, void *addr) const
Definition: base.cc:872
gem5::ArmISA::MISCREG_IMPLEMENTED
@ MISCREG_IMPLEMENTED
Definition: misc.hh:1101
gem5::ArmISA::i
Bitfield< 7 > i
Definition: misc_types.hh:67
gem5::ArmISA::MISCREG_USR_S_WR
@ MISCREG_USR_S_WR
Definition: misc.hh:1124
gem5::PowerISA::PCState
Definition: pcstate.hh:42
gem5::ArmISA::miscRegInfo
std::bitset< NUM_MISCREG_INFOS > miscRegInfo[NUM_MISCREGS]
Definition: misc.cc:806
gem5::kvmFPReg
constexpr uint64_t kvmFPReg(const int num)
Definition: armv8_cpu.cc:81
armv8_cpu.hh
gem5::ArmISA::MISCREG_CNTKCTL_EL1
@ MISCREG_CNTKCTL_EL1
Definition: misc.hh:769
gem5::kvmXReg
constexpr uint64_t kvmXReg(const int num)
Definition: armv8_cpu.cc:74
gem5::ArmISA::cc_reg::Nz
constexpr RegId Nz(CCRegClass, _NzIdx)
gem5::ArmISA::MiscRegInfo
MiscRegInfo
Definition: misc.hh:1099
gem5::ArmISA::j
Bitfield< 24 > j
Definition: misc_types.hh:57
gem5::ArmISA::MISCREG_ELR_EL1
@ MISCREG_ELR_EL1
Definition: misc.hh:615
gem5::VecRegContainer
Vector Register Abstraction This generic class is the model in a particularization of MVC,...
Definition: vec_reg.hh:123
gem5::VecRegContainer::as
VecElem * as()
View interposers.
Definition: vec_reg.hh:189
gem5::ArmISA::cc_reg::V
constexpr RegId V(CCRegClass, _VIdx)
gem5::PowerISA::ri
Bitfield< 1 > ri
Definition: misc.hh:120
gem5::ThreadContext::getWritableVecReg
TheISA::VecRegContainer & getWritableVecReg(const RegId &reg)
Definition: thread_context.hh:223
DPRINTF
#define DPRINTF(x,...)
Definition: trace.hh:186
gem5::ArmISA::d
Bitfield< 9 > d
Definition: misc_types.hh:64
gem5::BaseKvmCPU::tc
ThreadContext * tc
ThreadContext object, provides an interface for external objects to modify this thread's state.
Definition: base.hh:158
gem5::BaseArmKvmCPU
Definition: base_cpu.hh:55
gem5::ArmISA::MISCREG_SPSR_IRQ
@ MISCREG_SPSR_IRQ
Definition: misc.hh:64
FP_REGS_PER_VFP_REG
#define FP_REGS_PER_VFP_REG
Definition: armv8_cpu.cc:104
gem5::VegaISA::x
Bitfield< 4 > x
Definition: pagetable.hh:61
gem5::ArmV8KvmCPU::intRegMap
static const std::vector< ArmV8KvmCPU::IntRegInfo > intRegMap
Mapping between gem5 integer registers and integer registers in kvm.
Definition: armv8_cpu.hh:141
gem5::X86ISA::type
type
Definition: misc.hh:727
gem5::ArmISA::syncVecElemsToRegs
void syncVecElemsToRegs(ThreadContext *tc)
Definition: utility.cc:1354
gem5::ArmISA::s
Bitfield< 4 > s
Definition: misc_types.hh:562
gem5::ArmISA::MISCREG_MON_NS1_WR
@ MISCREG_MON_NS1_WR
Definition: misc.hh:1145
gem5::BaseKvmCPU::setOneReg
void setOneReg(uint64_t id, const void *addr)
Get/Set single register using the KVM_(SET|GET)_ONE_REG API.
Definition: base.cc:855
gem5::EventQueue::ScopedMigration
Definition: eventq.hh:672
gem5::ArmISA::MISCREG_MPIDR_EL1
@ MISCREG_MPIDR_EL1
Definition: misc.hh:541
SIMD_REG
#define SIMD_REG(name)
Definition: armv8_cpu.cc:69
gem5::ArmV8KvmCPU::getSysRegMap
const std::vector< ArmV8KvmCPU::MiscRegInfo > & getSysRegMap() const
Get a map between system registers in kvm and gem5 registers.
Definition: armv8_cpu.cc:371
gem5::ThreadContext::setRegFlat
virtual void setRegFlat(const RegId &reg, RegVal val)
Definition: thread_context.cc:209
gem5::ArmISA::MISCREG_CNTV_CVAL_EL0
@ MISCREG_CNTV_CVAL_EL0
Definition: misc.hh:761
gem5::ArmISA::MISCREG_SPSR_EL1
@ MISCREG_SPSR_EL1
Definition: misc.hh:613
gem5::ArmV8KvmCPU::updateKvmState
void updateKvmState() override
Update the KVM state from the current thread context.
Definition: armv8_cpu.cc:222
gem5::KvmFPReg::i
uint64_t i
Definition: armv8_cpu.cc:97
gem5::NUM_XREGS
constexpr static unsigned NUM_XREGS
Definition: armv8_cpu.cc:52
gem5::ArmISA::cc_reg::C
constexpr RegId C(CCRegClass, _CIdx)
gem5::ArmV8KvmCPU::dump
void dump() const override
Dump the internal state to the terminal.
Definition: armv8_cpu.cc:155
gem5::ArmISA::MiscRegIndex
MiscRegIndex
Definition: misc.hh:59
gem5::ArmV8KvmCPU::ArmV8KvmCPU
ArmV8KvmCPU(const ArmV8KvmCPUParams &params)
Definition: armv8_cpu.cc:132
gem5::X86ISA::reg
Bitfield< 5, 3 > reg
Definition: types.hh:92
gem5::ArmISA::cc_reg::Ge
constexpr RegId Ge(CCRegClass, _GeIdx)
gem5::IntRegClass
@ IntRegClass
Integer register.
Definition: reg_class.hh:58
gem5::VegaISA::v
Bitfield< 0 > v
Definition: pagetable.hh:65
gem5::KvmFPReg::f
double f
Definition: armv8_cpu.cc:98
gem5::ArmV8KvmCPU::~ArmV8KvmCPU
virtual ~ArmV8KvmCPU()
Definition: armv8_cpu.cc:137
inform
#define inform(...)
Definition: logging.hh:247
gem5::ArmISA::syncVecRegsToElems
void syncVecRegsToElems(ThreadContext *tc)
Definition: utility.cc:1339
gem5::NUM_QREGS
constexpr static unsigned NUM_QREGS
Definition: armv8_cpu.cc:57
gem5::ArmISA::VecElem
uint32_t VecElem
Definition: vec.hh:60
gem5::BaseKvmCPU::getOneRegU64
uint64_t getOneRegU64(uint64_t id) const
Definition: base.hh:390
gem5::PowerISA::float_reg::NumArchRegs
const int NumArchRegs
Definition: float.hh:41
gem5::ThreadContext::setMiscReg
virtual void setMiscReg(RegIndex misc_reg, RegVal val)=0
gem5::MipsISA::pc
Bitfield< 4 > pc
Definition: pra_constants.hh:243
gem5::KvmFPReg::f
float f
Definition: armv8_cpu.cc:92
gem5::ArmISA::NumVecV8ArchRegs
const int NumVecV8ArchRegs
Definition: vec.hh:77
gem5::BaseArmKvmCPU::getRegList
const RegIndexVector & getRegList() const
Get a list of registers supported by getOneReg() and setOneReg().
Definition: base_cpu.cc:191
gem5::ArmISA::id
Bitfield< 33 > id
Definition: misc_types.hh:251
gem5::ArmISA::MISCREG_SPSR_ABT
@ MISCREG_SPSR_ABT
Definition: misc.hh:67
gem5::ArmISA::MISCREG_FPSR
@ MISCREG_FPSR
Definition: misc.hh:623
gem5::ArmV8KvmCPU::sysRegMap
std::vector< ArmV8KvmCPU::MiscRegInfo > sysRegMap
Cached mapping between system registers in kvm and misc regs in gem5.
Definition: armv8_cpu.hh:150
gem5::ArmISA::MISCREG_FPCR
@ MISCREG_FPCR
Definition: misc.hh:622
gem5::VecRegClass
@ VecRegClass
Vector Register.
Definition: reg_class.hh:61
EXTRACT_FIELD
#define EXTRACT_FIELD(v, name)
Definition: armv8_cpu.cc:60
gem5::KvmFPReg::i
uint32_t i
Definition: armv8_cpu.cc:91
gem5::BaseArmKvmCPU::startup
void startup() override
Definition: base_cpu.cc:94
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: gpu_translation_state.hh:37
gem5::ArmV8KvmCPU::deviceRegSet
static const std::set< ArmISA::MiscRegIndex > deviceRegSet
Device registers (needing "effectful" MiscReg writes)
Definition: armv8_cpu.hh:145
CORE_REG
#define CORE_REG(name, size)
Definition: armv8_cpu.cc:63
gem5::RegId
Register ID: describe an architectural register with its class and index.
Definition: reg_class.hh:126
gem5::ThreadContext::setMiscRegNoEffect
virtual void setMiscRegNoEffect(RegIndex misc_reg, RegVal val)=0
gem5::ArmISA::MISCREG_WARN_NOT_FAIL
@ MISCREG_WARN_NOT_FAIL
Definition: misc.hh:1104
gem5::ThreadContext::setReg
virtual void setReg(const RegId &reg, RegVal val)
Definition: thread_context.cc:183
gem5::ArmISA::MISCREG_SPSR_UND
@ MISCREG_SPSR_UND
Definition: misc.hh:69
gem5::ArmISA::MISCREG_HYP_NS_WR
@ MISCREG_HYP_NS_WR
Definition: misc.hh:1132

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