32 #include "iris/detail/IrisCppAdapter.h"
33 #include "iris/detail/IrisObjects.h"
44 iris::IrisConnectionInterface *iris_if,
45 const std::string &iris_path) :
73 panic_if(in == iris::IRIS_UINT64_MAX || out == iris::IRIS_UINT64_MAX,
74 "Canonical IRIS memory space numbers not found.");
76 return ThreadContext::translateAddress(paddr, out,
vaddr, in);
82 ThreadContext::initFromIrisInstance(resources);
101 ArmISA::CPSR orig_cpsr;
103 auto *non_const_this =
const_cast<CortexA76TC *
>(
this);
107 ArmISA::CPSR new_cpsr = orig_cpsr;
112 RegVal val = ThreadContext::readIntRegFlat(idx);
124 ArmISA::CPSR orig_cpsr;
128 ArmISA::CPSR new_cpsr = orig_cpsr;
133 ThreadContext::setIntRegFlat(idx,
val);
146 result = ((ArmISA::CPSR)result).nz;
149 result =
bits(result, 31, 28);
187 for (
auto &msn : msns) {
189 if (
id != iris::IRIS_UINT64_MAX)
193 "Unable to find address space(s) for breakpoints.");
939 { 0,
"V0" }, { 1,
"V1" }, { 2,
"V2" }, { 3,
"V3" },
940 { 4,
"V4" }, { 5,
"V5" }, { 6,
"V6" }, { 7,
"V7" },
941 { 8,
"V8" }, { 9,
"V9" }, { 10,
"V10" }, { 11,
"V11" },
942 { 12,
"V12" }, { 13,
"V13" }, { 14,
"V14" }, { 15,
"V15" },
943 { 16,
"V16" }, { 17,
"V17" }, { 18,
"V18" }, { 19,
"V19" },
944 { 20,
"V20" }, { 21,
"V21" }, { 22,
"V22" }, { 23,
"V23" },
945 { 24,
"V24" }, { 25,
"V25" }, { 26,
"V26" }, { 27,
"V27" },
946 { 28,
"V28" }, { 29,
"V29" }, { 30,
"V30" }, { 31,
"V31" }
virtual RegVal readCCRegFlat(RegIndex idx) const
ResourceIds flattenedIntIds
void extractResourceMap(ResourceIds &ids, const ResourceMap &resources, const IdxNameMap &idx_names)
void setMiscReg(RegIndex misc_reg, const RegVal val) override
std::map< std::string, iris::ResourceInfo > ResourceMap
std::map< int, std::string > IdxNameMap
iris::MemorySpaceId getMemorySpaceId(const Iris::CanonicalMsn &msn) const
RegVal readMiscRegNoEffect(RegIndex misc_reg) const override
iris::ResourceId extractResourceId(const ResourceMap &resources, const std::string &name)
virtual void setCCRegFlat(RegIndex idx, RegVal val)
ThreadContext is the external interface to all thread state for anything outside of the CPU.
static IdxNameMap intReg32IdxNameMap
static IdxNameMap vecRegIdxNameMap
const std::vector< iris::MemorySpaceId > & getBpSpaceIds() const override
CortexA76TC(gem5::BaseCPU *cpu, int id, System *system, gem5::BaseMMU *mmu, gem5::BaseISA *isa, iris::IrisConnectionInterface *iris_if, const std::string &iris_path)
void setIntRegFlat(RegIndex idx, RegVal val) override
void setCCRegFlat(RegIndex idx, RegVal val) override
RegVal readIntRegFlat(RegIndex idx) const override
static IdxNameMap flattenedIntIdxNameMap
static IdxNameMap intReg64IdxNameMap
void initFromIrisInstance(const ResourceMap &resources) override
static IdxNameMap miscRegIdxNameMap
static std::vector< iris::MemorySpaceId > bpSpaceIds
static IdxNameMap ccRegIdxNameMap
RegVal readCCRegFlat(RegIndex idx) const override
bool translateAddress(Addr &paddr, Addr vaddr) override
constexpr T bits(T val, unsigned first, unsigned last)
Extract the bitfield from position 'first' to 'last' (inclusive) from 'val' and right justify it.
constexpr T insertBits(T val, unsigned first, unsigned last, B bit_val)
Returns val with bits first to last set to the LSBs of bit_val.
#define panic_if(cond,...)
Conditional panic macro that checks the supplied condition and only panics if the condition is true a...
ExceptionLevel currEL(const ThreadContext *tc)
Returns the current Exception Level (EL) of the provided ThreadContext.
bool isSecure(ThreadContext *tc)
@ MISCREG_ID_AA64PFR0_EL1
@ MISCREG_TLBI_IPAS2E1IS_Xt
@ MISCREG_TLBI_IPAS2E1_Xt
@ MISCREG_TLBI_ASIDE1IS_Xt
@ MISCREG_ID_AA64DFR0_EL1
@ MISCREG_TLBI_VAAE1IS_Xt
@ MISCREG_ID_AA64DFR1_EL1
@ MISCREG_ID_AA64ISAR1_EL1
@ MISCREG_ID_AA64MMFR1_EL1
@ MISCREG_TLBI_VMALLS12E1
@ MISCREG_TLBI_VMALLS12E1IS
@ MISCREG_TLBI_IPAS2LE1IS_Xt
@ MISCREG_ID_AA64MMFR0_EL1
@ MISCREG_DBGCLAIMSET_EL1
@ MISCREG_TLBI_VALE3IS_Xt
@ MISCREG_DBGCLAIMCLR_EL1
@ MISCREG_ID_AA64AFR1_EL1
@ MISCREG_TLBI_VAALE1IS_Xt
@ MISCREG_ID_AA64AFR0_EL1
@ MISCREG_TLBI_VALE2IS_Xt
@ MISCREG_ID_AA64ISAR0_EL1
@ MISCREG_TLBI_VALE1IS_Xt
@ MISCREG_TLBI_IPAS2LE1_Xt
@ MISCREG_DBGAUTHSTATUS_EL1
@ MISCREG_ID_AA64PFR1_EL1
@ PhysicalMemorySecureMsn
@ PhysicalMemoryNonSecureMsn
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
GEM5_DEPRECATED_NAMESPACE(GuestABI, guest_abi)