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32 #include "iris/detail/IrisCppAdapter.h"
33 #include "iris/detail/IrisObjects.h"
44 iris::IrisConnectionInterface *iris_if,
45 const std::string &iris_path) :
73 panic_if(in == iris::IRIS_UINT64_MAX || out == iris::IRIS_UINT64_MAX,
74 "Canonical IRIS memory space numbers not found.");
76 return ThreadContext::translateAddress(paddr, out,
vaddr, in);
82 ThreadContext::initFromIrisInstance(resources);
101 ArmISA::CPSR orig_cpsr;
103 auto *non_const_this =
const_cast<CortexA76TC *
>(
this);
105 if (idx == ArmISA::INTREG_R13_MON || idx == ArmISA::INTREG_R14_MON) {
107 ArmISA::CPSR new_cpsr = orig_cpsr;
114 if (idx == ArmISA::INTREG_R13_MON || idx == ArmISA::INTREG_R14_MON) {
124 ArmISA::CPSR orig_cpsr;
126 if (idx == ArmISA::INTREG_R13_MON || idx == ArmISA::INTREG_R14_MON) {
128 ArmISA::CPSR new_cpsr = orig_cpsr;
135 if (idx == ArmISA::INTREG_R13_MON || idx == ArmISA::INTREG_R14_MON) {
146 result = ((ArmISA::CPSR)result).nz;
149 result =
bits(result, 31, 28);
187 for (
auto &msn : msns) {
189 if (
id != iris::IRIS_UINT64_MAX)
193 "Unable to find address space(s) for breakpoints.");
835 { ArmISA::INTREG_R0,
"R0" },
836 { ArmISA::INTREG_R1,
"R1" },
837 { ArmISA::INTREG_R2,
"R2" },
838 { ArmISA::INTREG_R3,
"R3" },
839 { ArmISA::INTREG_R4,
"R4" },
840 { ArmISA::INTREG_R5,
"R5" },
841 { ArmISA::INTREG_R6,
"R6" },
842 { ArmISA::INTREG_R7,
"R7" },
843 { ArmISA::INTREG_R8,
"R8" },
844 { ArmISA::INTREG_R9,
"R9" },
845 { ArmISA::INTREG_R10,
"R10" },
846 { ArmISA::INTREG_R11,
"R11" },
847 { ArmISA::INTREG_R12,
"R12" },
848 { ArmISA::INTREG_R13,
"R13" },
849 { ArmISA::INTREG_R14,
"R14" },
850 { ArmISA::INTREG_R15,
"R15" }
854 { ArmISA::INTREG_X0,
"X0" },
855 { ArmISA::INTREG_X1,
"X1" },
856 { ArmISA::INTREG_X2,
"X2" },
857 { ArmISA::INTREG_X3,
"X3" },
858 { ArmISA::INTREG_X4,
"X4" },
859 { ArmISA::INTREG_X5,
"X5" },
860 { ArmISA::INTREG_X6,
"X6" },
861 { ArmISA::INTREG_X7,
"X7" },
862 { ArmISA::INTREG_X8,
"X8" },
863 { ArmISA::INTREG_X9,
"X9" },
864 { ArmISA::INTREG_X10,
"X10" },
865 { ArmISA::INTREG_X11,
"X11" },
866 { ArmISA::INTREG_X12,
"X12" },
867 { ArmISA::INTREG_X13,
"X13" },
868 { ArmISA::INTREG_X14,
"X14" },
869 { ArmISA::INTREG_X15,
"X15" },
870 { ArmISA::INTREG_X16,
"X16" },
871 { ArmISA::INTREG_X17,
"X17" },
872 { ArmISA::INTREG_X18,
"X18" },
873 { ArmISA::INTREG_X19,
"X19" },
874 { ArmISA::INTREG_X20,
"X20" },
875 { ArmISA::INTREG_X21,
"X21" },
876 { ArmISA::INTREG_X22,
"X22" },
877 { ArmISA::INTREG_X23,
"X23" },
878 { ArmISA::INTREG_X24,
"X24" },
879 { ArmISA::INTREG_X25,
"X25" },
880 { ArmISA::INTREG_X26,
"X26" },
881 { ArmISA::INTREG_X27,
"X27" },
882 { ArmISA::INTREG_X28,
"X28" },
883 { ArmISA::INTREG_X29,
"X29" },
884 { ArmISA::INTREG_X30,
"X30" },
885 { ArmISA::INTREG_SPX,
"SP" },
889 { ArmISA::INTREG_R0,
"X0" },
890 { ArmISA::INTREG_R1,
"X1" },
891 { ArmISA::INTREG_R2,
"X2" },
892 { ArmISA::INTREG_R3,
"X3" },
893 { ArmISA::INTREG_R4,
"X4" },
894 { ArmISA::INTREG_R5,
"X5" },
895 { ArmISA::INTREG_R6,
"X6" },
896 { ArmISA::INTREG_R7,
"X7" },
897 { ArmISA::INTREG_R8,
"X8" },
898 { ArmISA::INTREG_R9,
"X9" },
899 { ArmISA::INTREG_R10,
"X10" },
900 { ArmISA::INTREG_R11,
"X11" },
901 { ArmISA::INTREG_R12,
"X12" },
902 { ArmISA::INTREG_R13,
"X13" },
903 { ArmISA::INTREG_R14,
"X14" },
905 { ArmISA::INTREG_R13_SVC,
"X19" },
906 { ArmISA::INTREG_R14_SVC,
"X18" },
907 { ArmISA::INTREG_R13_MON,
"R13" },
908 { ArmISA::INTREG_R14_MON,
"R14" },
909 { ArmISA::INTREG_R13_HYP,
"X15" },
910 { ArmISA::INTREG_R13_ABT,
"X21" },
911 { ArmISA::INTREG_R14_ABT,
"X20" },
912 { ArmISA::INTREG_R13_UND,
"X23" },
913 { ArmISA::INTREG_R14_UND,
"X22" },
914 { ArmISA::INTREG_R13_IRQ,
"X17" },
915 { ArmISA::INTREG_R14_IRQ,
"X16" },
916 { ArmISA::INTREG_R8_FIQ,
"X24" },
917 { ArmISA::INTREG_R9_FIQ,
"X25" },
918 { ArmISA::INTREG_R10_FIQ,
"X26" },
919 { ArmISA::INTREG_R11_FIQ,
"X27" },
920 { ArmISA::INTREG_R12_FIQ,
"X28" },
921 { ArmISA::INTREG_R13_FIQ,
"X29" },
922 { ArmISA::INTREG_R14_FIQ,
"X30" },
924 { ArmISA::INTREG_SP0,
"SP_EL0" },
925 { ArmISA::INTREG_SP1,
"SP_EL1" },
926 { ArmISA::INTREG_SP2,
"SP_EL2" },
927 { ArmISA::INTREG_SP3,
"SP_EL3" },
939 { 0,
"V0" }, { 1,
"V1" }, { 2,
"V2" }, { 3,
"V3" },
940 { 4,
"V4" }, { 5,
"V5" }, { 6,
"V6" }, { 7,
"V7" },
941 { 8,
"V8" }, { 9,
"V9" }, { 10,
"V10" }, { 11,
"V11" },
942 { 12,
"V12" }, { 13,
"V13" }, { 14,
"V14" }, { 15,
"V15" },
943 { 16,
"V16" }, { 17,
"V17" }, { 18,
"V18" }, { 19,
"V19" },
944 { 20,
"V20" }, { 21,
"V21" }, { 22,
"V22" }, { 23,
"V23" },
945 { 24,
"V24" }, { 25,
"V25" }, { 26,
"V26" }, { 27,
"V27" },
946 { 28,
"V28" }, { 29,
"V29" }, { 30,
"V30" }, { 31,
"V31" }
static IdxNameMap ccRegIdxNameMap
static std::vector< iris::MemorySpaceId > bpSpaceIds
std::map< int, std::string > IdxNameMap
@ PhysicalMemoryNonSecureMsn
@ PhysicalMemorySecureMsn
@ MISCREG_TLBI_VAAE1IS_Xt
const std::vector< iris::MemorySpaceId > & getBpSpaceIds() const override
@ MISCREG_TLBI_IPAS2E1IS_Xt
CortexA76TC(gem5::BaseCPU *cpu, int id, System *system, gem5::BaseMMU *mmu, gem5::BaseISA *isa, iris::IrisConnectionInterface *iris_if, const std::string &iris_path)
@ MISCREG_TLBI_IPAS2LE1IS_Xt
void initFromIrisInstance(const ResourceMap &resources) override
@ MISCREG_TLBI_VMALLS12E1IS
static IdxNameMap vecRegIdxNameMap
@ MISCREG_TLBI_VALE2IS_Xt
@ MISCREG_TLBI_VALE1IS_Xt
@ MISCREG_ID_AA64AFR1_EL1
@ MISCREG_ID_AA64MMFR0_EL1
virtual RegVal readIntRegFlat(RegIndex idx) const =0
Flat register interfaces.
@ MISCREG_ID_AA64DFR1_EL1
@ MISCREG_TLBI_VALE3IS_Xt
@ MISCREG_TLBI_VMALLS12E1
static IdxNameMap miscRegIdxNameMap
@ MISCREG_DBGCLAIMCLR_EL1
@ MISCREG_DBGAUTHSTATUS_EL1
@ MISCREG_DBGCLAIMSET_EL1
@ MISCREG_ID_AA64PFR1_EL1
ThreadContext is the external interface to all thread state for anything outside of the CPU.
@ MISCREG_ID_AA64AFR0_EL1
virtual void setIntRegFlat(RegIndex idx, RegVal val)=0
RegVal readCCRegFlat(RegIndex idx) const override
static IdxNameMap intReg32IdxNameMap
@ MISCREG_TLBI_ASIDE1IS_Xt
void extractResourceMap(ResourceIds &ids, const ResourceMap &resources, const IdxNameMap &idx_names)
constexpr T insertBits(T val, unsigned first, unsigned last, B bit_val)
Returns val with bits first to last set to the LSBs of bit_val.
constexpr T bits(T val, unsigned first, unsigned last)
Extract the bitfield from position 'first' to 'last' (inclusive) from 'val' and right justify it.
static IdxNameMap intReg64IdxNameMap
@ MISCREG_ID_AA64DFR0_EL1
ResourceIds flattenedIntIds
@ MISCREG_ID_AA64MMFR1_EL1
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
RegVal readCCRegFlat(RegIndex idx) const override
GEM5_DEPRECATED_NAMESPACE(GuestABI, guest_abi)
iris::ResourceId extractResourceId(const ResourceMap &resources, const std::string &name)
bool isSecure(ThreadContext *tc)
@ MISCREG_ID_AA64ISAR1_EL1
@ MISCREG_TLBI_IPAS2LE1_Xt
RegVal readMiscRegNoEffect(RegIndex misc_reg) const override
@ MISCREG_TLBI_VAALE1IS_Xt
ExceptionLevel currEL(const ThreadContext *tc)
Returns the current Exception Level (EL) of the provided ThreadContext.
void setCCRegFlat(RegIndex idx, RegVal val) override
#define panic_if(cond,...)
Conditional panic macro that checks the supplied condition and only panics if the condition is true a...
static IdxNameMap flattenedIntIdxNameMap
std::map< std::string, iris::ResourceInfo > ResourceMap
bool translateAddress(Addr &paddr, Addr vaddr) override
RegVal readIntRegFlat(RegIndex idx) const override
Flat register interfaces.
void setMiscReg(RegIndex misc_reg, const RegVal val) override
iris::MemorySpaceId getMemorySpaceId(const Iris::CanonicalMsn &msn) const
void setCCRegFlat(RegIndex idx, RegVal val) override
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
@ MISCREG_ID_AA64PFR0_EL1
@ MISCREG_TLBI_IPAS2E1_Xt
@ MISCREG_ID_AA64ISAR0_EL1
void setIntRegFlat(RegIndex idx, RegVal val) override
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