gem5  v21.1.0.2
thread_context.cc
Go to the documentation of this file.
1 /*
2  * Copyright 2019 Google, Inc.
3  *
4  * Redistribution and use in source and binary forms, with or without
5  * modification, are permitted provided that the following conditions are
6  * met: redistributions of source code must retain the above copyright
7  * notice, this list of conditions and the following disclaimer;
8  * redistributions in binary form must reproduce the above copyright
9  * notice, this list of conditions and the following disclaimer in the
10  * documentation and/or other materials provided with the distribution;
11  * neither the name of the copyright holders nor the names of its
12  * contributors may be used to endorse or promote products derived from
13  * this software without specific prior written permission.
14  *
15  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
16  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
17  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
18  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
19  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
20  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
21  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
22  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
23  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
25  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26  */
27 
29 
31 #include "arch/arm/utility.hh"
32 #include "iris/detail/IrisCppAdapter.h"
33 #include "iris/detail/IrisObjects.h"
34 
35 namespace gem5
36 {
37 
38 GEM5_DEPRECATED_NAMESPACE(FastModel, fastmodel);
39 namespace fastmodel
40 {
41 
43  gem5::BaseMMU *mmu, gem5::BaseISA *isa,
44  iris::IrisConnectionInterface *iris_if,
45  const std::string &iris_path) :
46  ThreadContext(cpu, id, system, mmu, isa, iris_if, iris_path)
47 {}
48 
49 bool
51 {
52  // Determine what memory spaces are currently active.
53  Iris::CanonicalMsn in_msn;
54  switch (ArmISA::currEL(this)) {
55  case ArmISA::EL3:
56  in_msn = Iris::SecureMonitorMsn;
57  break;
58  case ArmISA::EL2:
59  in_msn = Iris::NsHypMsn;
60  break;
61  default:
62  in_msn = Iris::GuestMsn;
63  break;
64  }
65 
66  Iris::CanonicalMsn out_msn = ArmISA::isSecure(this) ?
68 
69  // Figure out what memory spaces match the canonical numbers we need.
70  iris::MemorySpaceId in = iris::IRIS_UINT64_MAX;
71  iris::MemorySpaceId out = iris::IRIS_UINT64_MAX;
72 
73  for (auto &space: memorySpaces) {
74  if (space.canonicalMsn == in_msn)
75  in = space.spaceId;
76  else if (space.canonicalMsn == out_msn)
77  out = space.spaceId;
78  }
79 
80  panic_if(in == iris::IRIS_UINT64_MAX || out == iris::IRIS_UINT64_MAX,
81  "Canonical IRIS memory space numbers not found.");
82 
83  return ThreadContext::translateAddress(paddr, out, vaddr, in);
84 }
85 
86 void
88 {
89  ThreadContext::initFromIrisInstance(resources);
90 
91  pcRscId = extractResourceId(resources, "PC");
92 
94 
97 
99 
101 
103 }
104 
105 RegVal
107 {
108  ArmISA::CPSR orig_cpsr;
109 
110  auto *non_const_this = const_cast<CortexA76TC *>(this);
111 
112  if (idx == ArmISA::INTREG_R13_MON || idx == ArmISA::INTREG_R14_MON) {
114  ArmISA::CPSR new_cpsr = orig_cpsr;
115  new_cpsr.mode = ArmISA::MODE_MON;
116  non_const_this->setMiscReg(ArmISA::MISCREG_CPSR, new_cpsr);
117  }
118 
120 
121  if (idx == ArmISA::INTREG_R13_MON || idx == ArmISA::INTREG_R14_MON) {
122  non_const_this->setMiscReg(ArmISA::MISCREG_CPSR, orig_cpsr);
123  }
124 
125  return val;
126 }
127 
128 void
130 {
131  ArmISA::CPSR orig_cpsr;
132 
133  if (idx == ArmISA::INTREG_R13_MON || idx == ArmISA::INTREG_R14_MON) {
135  ArmISA::CPSR new_cpsr = orig_cpsr;
136  new_cpsr.mode = ArmISA::MODE_MON;
137  setMiscReg(ArmISA::MISCREG_CPSR, new_cpsr);
138  }
139 
141 
142  if (idx == ArmISA::INTREG_R13_MON || idx == ArmISA::INTREG_R14_MON) {
143  setMiscReg(ArmISA::MISCREG_CPSR, orig_cpsr);
144  }
145 }
146 
147 RegVal
149 {
151  switch (idx) {
152  case ArmISA::CCREG_NZ:
153  result = ((ArmISA::CPSR)result).nz;
154  break;
155  case ArmISA::CCREG_FP:
156  result = bits(result, 31, 28);
157  break;
158  default:
159  break;
160  }
161  return result;
162 }
163 
164 void
166 {
167  switch (idx) {
168  case ArmISA::CCREG_NZ:
169  {
170  ArmISA::CPSR cpsr = readMiscRegNoEffect(ArmISA::MISCREG_CPSR);
171  cpsr.nz = val;
172  val = cpsr;
173  }
174  break;
175  case ArmISA::CCREG_FP:
176  {
177  ArmISA::FPSCR fpscr = readMiscRegNoEffect(ArmISA::MISCREG_FPSCR);
178  val = insertBits(fpscr, 31, 28, val);
179  }
180  break;
181  default:
182  break;
183  }
185 }
186 
189 {
190  if (bpSpaceIds.empty()) {
191  for (auto &space: memorySpaces) {
192  auto cmsn = space.canonicalMsn;
193  if (cmsn == Iris::SecureMonitorMsn ||
194  cmsn == Iris::GuestMsn ||
195  cmsn == Iris::NsHypMsn ||
196  cmsn == Iris::HypAppMsn) {
197  bpSpaceIds.push_back(space.spaceId);
198  }
199  }
200  panic_if(bpSpaceIds.empty(),
201  "Unable to find address space(s) for breakpoints.");
202  }
203  return bpSpaceIds;
204 }
205 
207  { ArmISA::MISCREG_CPSR, "CPSR" },
208  { ArmISA::MISCREG_SPSR, "SPSR" },
209  { ArmISA::MISCREG_SPSR_FIQ, "SPSR_fiq" },
210  { ArmISA::MISCREG_SPSR_IRQ, "SPSR_irq" },
211  // ArmISA::MISCREG_SPSR_SVC?
212  // ArmISA::MISCREG_SPSR_MON?
213  { ArmISA::MISCREG_SPSR_ABT, "SPSR_abt" },
214  // ArmISA::MISCREG_SPSR_HYP?
215  { ArmISA::MISCREG_SPSR_UND, "SPSR_und" },
216  // ArmISA::MISCREG_ELR_HYP?
217  // ArmISA::MISCREG_FPSID?
218  { ArmISA::MISCREG_FPSCR, "FPSCR" },
219  { ArmISA::MISCREG_MVFR1, "MVFR1_EL1" }, //XXX verify
220  { ArmISA::MISCREG_MVFR0, "MVFR1_EL1" }, //XXX verify
221  // ArmISA::MISCREG_FPEXC?
222 
223  // Helper registers
224  { ArmISA::MISCREG_CPSR_MODE, "CPSR.MODE" },
225  { ArmISA::MISCREG_CPSR_Q, "CPSR.Q" },
226  // ArmISA::MISCREG_FPSCR_EXC?
227  { ArmISA::MISCREG_FPSCR_QC, "FPSR.QC" },
228  // ArmISA::MISCREG_LOCKADDR?
229  // ArmISA::MISCREG_LOCKFLAG?
230  // ArmISA::MISCREG_PRRR_MAIR0?
231  // ArmISA::MISCREG_PRRR_MAIR0_NS?
232  // ArmISA::MISCREG_PRRR_MAIR0_S?
233  // ArmISA::MISCREG_NMRR_MAIR1?
234  // ArmISA::MISCREG_NMRR_MAIR1_NS?
235  // ArmISA::MISCREG_NMRR_MAIR1_S?
236  // ArmISA::MISCREG_PMXEVTYPER_PMCCFILTR?
237  // ArmISA::MISCREG_SCTLR_RST?
238  { ArmISA::MISCREG_SEV_MAILBOX, "SEV_STATE" },
239 
240  // AArch32 CP14 registers (debug/trace/ThumbEE/Jazelle control)
241  // ArmISA::MISCREG_DBGDIDR?
242  // ArmISA::MISCREG_DBGDSCRint?
243  // ArmISA::MISCREG_DBGDCCINT?
244  // ArmISA::MISCREG_DBGDTRTXint?
245  // ArmISA::MISCREG_DBGDTRRXint?
246  { ArmISA::MISCREG_DBGWFAR, "DBGWFAR" },
247  // ArmISA::MISCREG_DBGVCR?
248  { ArmISA::MISCREG_DBGDTRRXext, "DBGDTRRXext" },
249  // ArmISA::MISCREG_DBGDSCRext?
250  { ArmISA::MISCREG_DBGDTRTXext, "DBGDTRTXext" },
251  // ArmISA::MISCREG_DBGOSECCR?
252  { ArmISA::MISCREG_DBGBVR0, "DBGBVR0" },
253  { ArmISA::MISCREG_DBGBVR1, "DBGBVR1" },
254  { ArmISA::MISCREG_DBGBVR2, "DBGBVR2" },
255  { ArmISA::MISCREG_DBGBVR3, "DBGBVR3" },
256  { ArmISA::MISCREG_DBGBVR4, "DBGBVR4" },
257  { ArmISA::MISCREG_DBGBVR5, "DBGBVR5" },
258  { ArmISA::MISCREG_DBGBCR0, "DBGBCR0" },
259  { ArmISA::MISCREG_DBGBCR1, "DBGBCR1" },
260  { ArmISA::MISCREG_DBGBCR2, "DBGBCR2" },
261  { ArmISA::MISCREG_DBGBCR3, "DBGBCR3" },
262  { ArmISA::MISCREG_DBGBCR4, "DBGBCR4" },
263  { ArmISA::MISCREG_DBGBCR5, "DBGBCR5" },
264  { ArmISA::MISCREG_DBGWVR0, "DBGWVR0" },
265  { ArmISA::MISCREG_DBGWVR1, "DBGWVR1" },
266  { ArmISA::MISCREG_DBGWVR2, "DBGWVR2" },
267  { ArmISA::MISCREG_DBGWVR3, "DBGWVR3" },
268  { ArmISA::MISCREG_DBGWCR0, "DBGWCR0" },
269  { ArmISA::MISCREG_DBGWCR1, "DBGWCR1" },
270  { ArmISA::MISCREG_DBGWCR2, "DBGWCR2" },
271  { ArmISA::MISCREG_DBGWCR3, "DBGWCR3" },
272  // ArmISA::MISCREG_DBGDRAR?
273  { ArmISA::MISCREG_DBGBXVR4, "DBGBXVR4" },
274  { ArmISA::MISCREG_DBGBXVR5, "DBGBXVR5" },
275  { ArmISA::MISCREG_DBGOSLAR, "DBGOSLAR" },
276  // ArmISA::MISCREG_DBGOSLSR?
277  // ArmISA::MISCREG_DBGOSDLR?
278  { ArmISA::MISCREG_DBGPRCR, "DBGPRCR_EL1" }, //XXX verify
279  // ArmISA::MISCREG_DBGDSAR?
280  { ArmISA::MISCREG_DBGCLAIMSET, "DBGCLAIMSET" },
281  { ArmISA::MISCREG_DBGCLAIMCLR, "DBGCLAIMCLR" },
282  { ArmISA::MISCREG_DBGAUTHSTATUS, "DBGAUTHSTATUS" },
283  // ArmISA::MISCREG_DBGDEVID2?
284  // ArmISA::MISCREG_DBGDEVID1?
285  // ArmISA::MISCREG_DBGDEVID0?
286  // ArmISA::MISCREG_TEECR? not in ARM DDI 0487A.b+
287  // ArmISA::MISCREG_JIDR?
288  // ArmISA::MISCREG_TEEHBR? not in ARM DDI 0487A.b+
289  // ArmISA::MISCREG_JOSCR?
290  // ArmISA::MISCREG_JMCR?
291 
292  // AArch32 CP15 registers (system control)
293  { ArmISA::MISCREG_MIDR, "MIDR" },
294  { ArmISA::MISCREG_CTR, "CTR" },
295  { ArmISA::MISCREG_TCMTR, "TCMTR" },
296  { ArmISA::MISCREG_TLBTR, "TLBTR" },
297  { ArmISA::MISCREG_MPIDR, "MPIDR" },
298  { ArmISA::MISCREG_REVIDR, "REVIDR" },
299  { ArmISA::MISCREG_ID_PFR0, "ID_PFR0" },
300  { ArmISA::MISCREG_ID_PFR1, "ID_PFR1" },
301  { ArmISA::MISCREG_ID_DFR0, "ID_DFR0" },
302  { ArmISA::MISCREG_ID_AFR0, "ID_AFR0" },
303  { ArmISA::MISCREG_ID_MMFR0, "ID_MMFR0" },
304  { ArmISA::MISCREG_ID_MMFR1, "ID_MMFR1" },
305  { ArmISA::MISCREG_ID_MMFR2, "ID_MMFR2" },
306  { ArmISA::MISCREG_ID_MMFR3, "ID_MMFR3" },
307  { ArmISA::MISCREG_ID_MMFR4, "ID_MMFR4" },
308  { ArmISA::MISCREG_ID_ISAR0, "ID_ISAR0" },
309  { ArmISA::MISCREG_ID_ISAR1, "ID_ISAR1" },
310  { ArmISA::MISCREG_ID_ISAR2, "ID_ISAR2" },
311  { ArmISA::MISCREG_ID_ISAR3, "ID_ISAR3" },
312  { ArmISA::MISCREG_ID_ISAR4, "ID_ISAR4" },
313  { ArmISA::MISCREG_ID_ISAR5, "ID_ISAR5" },
314  { ArmISA::MISCREG_ID_ISAR6, "ID_ISAR6" },
315  { ArmISA::MISCREG_CCSIDR, "CCSIDR" },
316  { ArmISA::MISCREG_CLIDR, "CLIDR" },
317  { ArmISA::MISCREG_AIDR, "AIDR" },
318  { ArmISA::MISCREG_CSSELR, "CSSELR_EL1" }, //XXX verify
319  // ArmISA::MISCREG_CSSELR_NS?
320  // ArmISA::MISCREG_CSSELR_S?
321  { ArmISA::MISCREG_VPIDR, "VPIDR" },
322  { ArmISA::MISCREG_VMPIDR, "VMPIDR" },
323  // ArmISA::MISCREG_SCTLR?
324  // ArmISA::MISCREG_SCTLR_NS?
325  // ArmISA::MISCREG_SCTLR_S?
326  // ArmISA::MISCREG_ACTLR?
327  // ArmISA::MISCREG_ACTLR_NS?
328  // ArmISA::MISCREG_ACTLR_S?
329  { ArmISA::MISCREG_CPACR, "CPACR" },
330  { ArmISA::MISCREG_SCR, "SCR" },
331  { ArmISA::MISCREG_SDER, "SDER" },
332  { ArmISA::MISCREG_NSACR, "NSACR" },
333  { ArmISA::MISCREG_HSCTLR, "HSCTLR" },
334  { ArmISA::MISCREG_HACTLR, "HACTLR" },
335  { ArmISA::MISCREG_HCR, "HCR" },
336  { ArmISA::MISCREG_HDCR, "HDCR" },
337  { ArmISA::MISCREG_HCPTR, "HCPTR" },
338  { ArmISA::MISCREG_HSTR, "HSTR_EL2" }, //XXX verify
339  { ArmISA::MISCREG_HACR, "HACR" },
340  // ArmISA::MISCREG_TTBR0?
341  { ArmISA::MISCREG_TTBR0_NS, "NS_TTBR0" }, //XXX verify
342  // ArmISA::MISCREG_TTBR0_S?
343  // ArmISA::MISCREG_TTBR1?
344  { ArmISA::MISCREG_TTBR1_NS, "NS_TTBR1" }, //XXX verify
345  // ArmISA::MISCREG_TTBR1_S?
346  // ArmISA::MISCREG_TTBCR?
347  { ArmISA::MISCREG_TTBCR_NS, "NS_TTBCR" }, //XXX verify
348  // ArmISA::MISCREG_TTBCR_S?
349  // ArmISA::MISCREG_HTCR?
350  // ArmISA::MISCREG_VTCR?
351  // ArmISA::MISCREG_DACR?
352  { ArmISA::MISCREG_DACR_NS, "NS_DACR" }, //XXX verify
353  // ArmISA::MISCREG_DACR_S?
354  // ArmISA::MISCREG_DFSR?
355  { ArmISA::MISCREG_DFSR_NS, "NS_DFSR" }, //XXX verify
356  // ArmISA::MISCREG_DFSR_S?
357  // ArmISA::MISCREG_IFSR?
358  { ArmISA::MISCREG_IFSR_NS, "NS_IFSR" },
359  // ArmISA::MISCREG_IFSR_S?
360  { ArmISA::MISCREG_ADFSR, "ADFSR" },
361  // ArmISA::MISCREG_ADFSR_NS?
362  // ArmISA::MISCREG_ADFSR_S?
363  { ArmISA::MISCREG_AIFSR, "AIFSR" },
364  // ArmISA::MISCREG_AIFSR_NS?
365  // ArmISA::MISCREG_AIFSR_S?
366  // ArmISA::MISCREG_HADFSR?
367  // ArmISA::MISCREG_HAIFSR?
368  { ArmISA::MISCREG_HSR, "HSR" },
369  // ArmISA::MISCREG_DFAR?
370  { ArmISA::MISCREG_DFAR_NS, "NS_DFAR" }, //XXX verify
371  // ArmISA::MISCREG_DFAR_S?
372  // ArmISA::MISCREG_IFAR?
373  { ArmISA::MISCREG_IFAR_NS, "NS_IFAR" }, //XXX verify
374  // ArmISA::MISCREG_IFAR_S?
375  { ArmISA::MISCREG_HDFAR, "HDFAR" },
376  { ArmISA::MISCREG_HIFAR, "HIFAR" },
377  { ArmISA::MISCREG_HPFAR, "HPFAR" },
378  { ArmISA::MISCREG_ICIALLUIS, "ICIALLUIS" },
379  // ArmISA::MISCREG_BPIALLIS?
380  // ArmISA::MISCREG_PAR?
381  { ArmISA::MISCREG_PAR_NS, "NS_PAR" }, //XXX verify
382  // ArmISA::MISCREG_PAR_S?
383  { ArmISA::MISCREG_ICIALLU, "ICIALLU" },
384  { ArmISA::MISCREG_ICIMVAU, "ICIMVAU" },
385  // ArmISA::MISCREG_CP15ISB?
386  // ArmISA::MISCREG_BPIALL?
387  // ArmISA::MISCREG_BPIMVA?
388  { ArmISA::MISCREG_DCIMVAC, "DCIMVAC" },
389  { ArmISA::MISCREG_DCISW, "DCISW" },
390  { ArmISA::MISCREG_ATS1CPR, "ATS1CPR" },
391  { ArmISA::MISCREG_ATS1CPW, "ATS1CPW" },
392  { ArmISA::MISCREG_ATS1CUR, "ATS1CUR" },
393  { ArmISA::MISCREG_ATS1CUW, "ATS1CUW" },
394  { ArmISA::MISCREG_ATS12NSOPR, "ATS12NSOPR" },
395  { ArmISA::MISCREG_ATS12NSOPW, "ATS12NSOPW" },
396  { ArmISA::MISCREG_ATS12NSOUR, "ATS12NSOUR" },
397  { ArmISA::MISCREG_ATS12NSOUW, "ATS12NSOUW" },
398  { ArmISA::MISCREG_DCCMVAC, "DCCMVAC" },
399  { ArmISA::MISCREG_DCCSW, "DCCSW" },
400  // ArmISA::MISCREG_CP15DSB?
401  // ArmISA::MISCREG_CP15DMB?
402  { ArmISA::MISCREG_DCCMVAU, "DCCMVAU" },
403  // ArmISA::MISCREG_DCCIMVAC?
404  { ArmISA::MISCREG_DCCISW, "DCCISW" },
405  { ArmISA::MISCREG_ATS1HR, "ATS1HR" },
406  { ArmISA::MISCREG_ATS1HW, "ATS1HW" },
407  // ArmISA::MISCREG_TLBIALLIS?
408  // ArmISA::MISCREG_TLBIMVAIS?
409  // ArmISA::MISCREG_TLBIASIDIS?
410  // ArmISA::MISCREG_TLBIMVAAIS?
411  // ArmISA::MISCREG_TLBIMVALIS?
412  // ArmISA::MISCREG_TLBIMVAALIS?
413  // ArmISA::MISCREG_ITLBIALL?
414  // ArmISA::MISCREG_ITLBIMVA?
415  // ArmISA::MISCREG_ITLBIASID?
416  // ArmISA::MISCREG_DTLBIALL?
417  // ArmISA::MISCREG_DTLBIMVA?
418  // ArmISA::MISCREG_DTLBIASID?
419  // ArmISA::MISCREG_TLBIALL?
420  // ArmISA::MISCREG_TLBIMVA?
421  // ArmISA::MISCREG_TLBIASID?
422  // ArmISA::MISCREG_TLBIMVAA?
423  // ArmISA::MISCREG_TLBIMVAL?
424  // ArmISA::MISCREG_TLBIMVAAL?
425  // ArmISA::MISCREG_TLBIIPAS2IS?
426  // ArmISA::MISCREG_TLBIIPAS2LIS?
427  // ArmISA::MISCREG_TLBIALLHIS?
428  // ArmISA::MISCREG_TLBIMVAHIS?
429  // ArmISA::MISCREG_TLBIALLNSNHIS?
430  // ArmISA::MISCREG_TLBIMVALHIS?
431  // ArmISA::MISCREG_TLBIIPAS2?
432  // ArmISA::MISCREG_TLBIIPAS2L?
433  // ArmISA::MISCREG_TLBIALLH?
434  // ArmISA::MISCREG_TLBIMVAH?
435  // ArmISA::MISCREG_TLBIALLNSNH?
436  // ArmISA::MISCREG_TLBIMVALH?
437  { ArmISA::MISCREG_PMCR, "PMCR" },
438  { ArmISA::MISCREG_PMCNTENSET, "PMCNTENSET" },
439  { ArmISA::MISCREG_PMCNTENCLR, "PMCNTENCLR" },
440  { ArmISA::MISCREG_PMOVSR, "PMOVSR" },
441  { ArmISA::MISCREG_PMSWINC, "PMSWINC" },
442  { ArmISA::MISCREG_PMSELR, "PMSELR" },
443  { ArmISA::MISCREG_PMCEID0, "PMCEID0" },
444  { ArmISA::MISCREG_PMCEID1, "PMCEID1" },
445  { ArmISA::MISCREG_PMCCNTR, "PMCCNTR" },
446  { ArmISA::MISCREG_PMXEVTYPER, "PMXEVTYPER" },
447  { ArmISA::MISCREG_PMCCFILTR, "PMCCFILTR" },
448  { ArmISA::MISCREG_PMXEVCNTR, "PMXEVCNTR_EL0" }, //XXX verify
449  { ArmISA::MISCREG_PMUSERENR, "PMUSERENR" },
450  { ArmISA::MISCREG_PMINTENSET, "PMINTENSET" },
451  { ArmISA::MISCREG_PMINTENCLR, "PMINTENCLR" },
452  { ArmISA::MISCREG_PMOVSSET, "PMOVSSET" },
453  // ArmISA::MISCREG_L2CTLR?
454  // ArmISA::MISCREG_L2ECTLR?
455  // ArmISA::MISCREG_PRRR?
456  { ArmISA::MISCREG_PRRR_NS, "NS_PRRR" }, //XXX verify
457  // ArmISA::MISCREG_PRRR_S?
458  // ArmISA::MISCREG_MAIR0?
459  // ArmISA::MISCREG_MAIR0_NS?
460  // ArmISA::MISCREG_MAIR0_S?
461  // ArmISA::MISCREG_NMRR?
462  { ArmISA::MISCREG_NMRR_NS, "NS_NMRR" }, //XXX verify
463  // ArmISA::MISCREG_NMRR_S?
464  // ArmISA::MISCREG_MAIR1?
465  // ArmISA::MISCREG_MAIR1_NS?
466  // ArmISA::MISCREG_MAIR1_S?
467  // ArmISA::MISCREG_AMAIR0?
468  { ArmISA::MISCREG_AMAIR0_NS, "NS_AMAIR0" }, //XXX verify
469  // ArmISA::MISCREG_AMAIR0_S?
470  // ArmISA::MISCREG_AMAIR1?
471  { ArmISA::MISCREG_AMAIR1_NS, "NS_AMAIR1" }, //XXX verify
472  // ArmISA::MISCREG_AMAIR1_S?
473  { ArmISA::MISCREG_HMAIR0, "HMAIR0" },
474  { ArmISA::MISCREG_HMAIR1, "HMAIR1" },
475  { ArmISA::MISCREG_HAMAIR0, "HAMAIR0" },
476  { ArmISA::MISCREG_HAMAIR1, "HAMAIR1" },
477  // ArmISA::MISCREG_VBAR?
478  { ArmISA::MISCREG_VBAR_NS, "NS_VBAR" }, //XXX verify
479  // ArmISA::MISCREG_VBAR_S?
480  { ArmISA::MISCREG_MVBAR, "MVBAR" },
481  { ArmISA::MISCREG_RMR, "RMR" },
482  { ArmISA::MISCREG_ISR, "ISR" },
483  { ArmISA::MISCREG_HVBAR, "HVBAR" },
484  { ArmISA::MISCREG_FCSEIDR, "FCSEIDR" },
485  // ArmISA::MISCREG_CONTEXTIDR?
486  { ArmISA::MISCREG_CONTEXTIDR_NS, "NS_CONTEXTIDR" }, //XXX verify
487  // ArmISA::MISCREG_CONTEXTIDR_S?
488  // ArmISA::MISCREG_TPIDRURW?
489  { ArmISA::MISCREG_TPIDRURW_NS, "NS_TPIDRURW" }, //XXX verify
490  // ArmISA::MISCREG_TPIDRURW_S?
491  // ArmISA::MISCREG_TPIDRURO?
492  { ArmISA::MISCREG_TPIDRURO_NS, "NS_TPIDRURO" }, //XXX verify
493  // ArmISA::MISCREG_TPIDRURO_S?
494  // ArmISA::MISCREG_TPIDRPRW?
495  { ArmISA::MISCREG_TPIDRPRW_NS, "NS_TPIDRPRW" }, //XXX verify
497  { ArmISA::MISCREG_HTPIDR, "HTPIDR" },
498  { ArmISA::MISCREG_CNTFRQ, "CNTFRQ" },
499  { ArmISA::MISCREG_CNTKCTL, "CNTKCTL" },
500  { ArmISA::MISCREG_CNTP_TVAL, "CNTP_TVAL" },
501  // ArmISA::MISCREG_CNTP_TVAL_NS?
502  // ArmISA::MISCREG_CNTP_TVAL_S?
503  { ArmISA::MISCREG_CNTP_CTL, "CNTP_CTL" },
504  // ArmISA::MISCREG_CNTP_CTL_NS?
505  // ArmISA::MISCREG_CNTP_CTL_S?
506  { ArmISA::MISCREG_CNTV_TVAL, "CNTV_TVAL" },
507  { ArmISA::MISCREG_CNTV_CTL, "CNTV_CTL" },
508  { ArmISA::MISCREG_CNTHCTL, "CNTHCTL" },
509  { ArmISA::MISCREG_CNTHP_TVAL, "CNTHP_TVAL" },
510  { ArmISA::MISCREG_CNTHP_CTL, "CNTHP_CTL" },
511  // ArmISA::MISCREG_IL1DATA0?
512  // ArmISA::MISCREG_IL1DATA1?
513  // ArmISA::MISCREG_IL1DATA2?
514  // ArmISA::MISCREG_IL1DATA3?
515  // ArmISA::MISCREG_DL1DATA0?
516  // ArmISA::MISCREG_DL1DATA1?
517  // ArmISA::MISCREG_DL1DATA2?
518  // ArmISA::MISCREG_DL1DATA3?
519  // ArmISA::MISCREG_DL1DATA4?
520  { ArmISA::MISCREG_RAMINDEX, "RAMIDX" }, //XXX verify
521  // ArmISA::MISCREG_L2ACTLR?
522  // ArmISA::MISCREG_CBAR?
523  { ArmISA::MISCREG_HTTBR, "HTTBR" },
524  { ArmISA::MISCREG_VTTBR, "VTTBR" },
525  { ArmISA::MISCREG_CNTPCT, "CNTPCT" },
526  { ArmISA::MISCREG_CNTVCT, "CNTVCT" },
527  { ArmISA::MISCREG_CNTP_CVAL, "CNTP_CVAL" },
528  // ArmISA::MISCREG_CNTP_CVAL_NS?
529  // ArmISA::MISCREG_CNTP_CVAL_S?
530  { ArmISA::MISCREG_CNTV_CVAL, "CNTV_CVAL" },
531  { ArmISA::MISCREG_CNTVOFF, "CNTVOFF" },
532  { ArmISA::MISCREG_CNTHP_CVAL, "CNTHP_CVAL" },
533  { ArmISA::MISCREG_CPUMERRSR, "CPUMERRSR" },
534  { ArmISA::MISCREG_L2MERRSR, "L2MERRSR" },
535 
536  // AArch64 registers (Op0=2)
537  { ArmISA::MISCREG_MDCCINT_EL1, "MDCCINT_EL1" },
538  { ArmISA::MISCREG_OSDTRRX_EL1, "OSDTRRX_EL1" },
539  { ArmISA::MISCREG_MDSCR_EL1, "MDSCR_EL1" },
540  { ArmISA::MISCREG_OSDTRTX_EL1, "OSDTRTX_EL1" },
541  { ArmISA::MISCREG_OSECCR_EL1, "OSECCR_EL1" },
542  { ArmISA::MISCREG_DBGBVR0_EL1, "DBGBVR0_EL1" },
543  { ArmISA::MISCREG_DBGBVR1_EL1, "DBGBVR1_EL1" },
544  { ArmISA::MISCREG_DBGBVR2_EL1, "DBGBVR2_EL1" },
545  { ArmISA::MISCREG_DBGBVR3_EL1, "DBGBVR3_EL1" },
546  { ArmISA::MISCREG_DBGBVR4_EL1, "DBGBVR4_EL1" },
547  { ArmISA::MISCREG_DBGBVR5_EL1, "DBGBVR5_EL1" },
548  { ArmISA::MISCREG_DBGBCR0_EL1, "DBGBCR0_EL1" },
549  { ArmISA::MISCREG_DBGBCR1_EL1, "DBGBCR1_EL1" },
550  { ArmISA::MISCREG_DBGBCR2_EL1, "DBGBCR2_EL1" },
551  { ArmISA::MISCREG_DBGBCR3_EL1, "DBGBCR3_EL1" },
552  { ArmISA::MISCREG_DBGBCR4_EL1, "DBGBCR4_EL1" },
553  { ArmISA::MISCREG_DBGBCR5_EL1, "DBGBCR5_EL1" },
554  { ArmISA::MISCREG_DBGWVR0_EL1, "DBGWVR0_EL1" },
555  { ArmISA::MISCREG_DBGWVR1_EL1, "DBGWVR1_EL1" },
556  { ArmISA::MISCREG_DBGWVR2_EL1, "DBGWVR2_EL1" },
557  { ArmISA::MISCREG_DBGWVR3_EL1, "DBGWVR3_EL1" },
558  { ArmISA::MISCREG_DBGWCR0_EL1, "DBGWCR0_EL1" },
559  { ArmISA::MISCREG_DBGWCR1_EL1, "DBGWCR1_EL1" },
560  { ArmISA::MISCREG_DBGWCR2_EL1, "DBGWCR2_EL1" },
561  { ArmISA::MISCREG_DBGWCR3_EL1, "DBGWCR3_EL1" },
562  { ArmISA::MISCREG_MDCCSR_EL0, "MDCCSR_EL0" },
563  // ArmISA::MISCREG_MDDTR_EL0?
564  // ArmISA::MISCREG_MDDTRTX_EL0?
565  // ArmISA::MISCREG_MDDTRRX_EL0?
566  // ArmISA::MISCREG_DBGVCR32_EL2?
567  { ArmISA::MISCREG_MDRAR_EL1, "MDRAR_EL1" },
568  { ArmISA::MISCREG_OSLAR_EL1, "OSLAR_EL1" },
569  { ArmISA::MISCREG_OSLSR_EL1, "OSLSR_EL1" },
570  { ArmISA::MISCREG_OSDLR_EL1, "OSDLR_EL1" },
571  { ArmISA::MISCREG_DBGPRCR_EL1, "DBGPRCR_EL1" },
572  { ArmISA::MISCREG_DBGCLAIMSET_EL1, "DBGCLAIMSET_EL1" },
573  { ArmISA::MISCREG_DBGCLAIMCLR_EL1, "DBGCLAIMCLR_EL1" },
574  { ArmISA::MISCREG_DBGAUTHSTATUS_EL1, "DBGAUTHSTATUS_EL1" },
575  // ArmISA::MISCREG_TEECR32_EL1? not in ARM DDI 0487A.b+
576  // ArmISA::MISCREG_TEEHBR32_EL1? not in ARM DDI 0487A.b+
577 
578  // AArch64 registers (Op0=1)
579  { ArmISA::MISCREG_MIDR_EL1, "MIDR_EL1" },
580  { ArmISA::MISCREG_MPIDR_EL1, "MPIDR_EL1" },
581  { ArmISA::MISCREG_REVIDR_EL1, "REVIDR_EL1" },
582  { ArmISA::MISCREG_ID_PFR0_EL1, "ID_PFR0_EL1" },
583  { ArmISA::MISCREG_ID_PFR1_EL1, "ID_PFR1_EL1" },
584  { ArmISA::MISCREG_ID_DFR0_EL1, "ID_DFR0_EL1" },
585  { ArmISA::MISCREG_ID_AFR0_EL1, "ID_AFR0_EL1" },
586  { ArmISA::MISCREG_ID_MMFR0_EL1, "ID_MMFR0_EL1" },
587  { ArmISA::MISCREG_ID_MMFR1_EL1, "ID_MMFR1_EL1" },
588  { ArmISA::MISCREG_ID_MMFR2_EL1, "ID_MMFR2_EL1" },
589  { ArmISA::MISCREG_ID_MMFR3_EL1, "ID_MMFR3_EL1" },
590  { ArmISA::MISCREG_ID_MMFR4_EL1, "ID_MMFR4_EL1" },
591  { ArmISA::MISCREG_ID_ISAR0_EL1, "ID_ISAR0_EL1" },
592  { ArmISA::MISCREG_ID_ISAR1_EL1, "ID_ISAR1_EL1" },
593  { ArmISA::MISCREG_ID_ISAR2_EL1, "ID_ISAR2_EL1" },
594  { ArmISA::MISCREG_ID_ISAR3_EL1, "ID_ISAR3_EL1" },
595  { ArmISA::MISCREG_ID_ISAR4_EL1, "ID_ISAR4_EL1" },
596  { ArmISA::MISCREG_ID_ISAR5_EL1, "ID_ISAR5_EL1" },
597  { ArmISA::MISCREG_ID_ISAR6_EL1, "ID_ISAR6_EL1" },
598  { ArmISA::MISCREG_MVFR0_EL1, "MVFR0_EL1" },
599  { ArmISA::MISCREG_MVFR1_EL1, "MVFR1_EL1" },
600  { ArmISA::MISCREG_MVFR2_EL1, "MVFR2_EL1" },
601  { ArmISA::MISCREG_ID_AA64PFR0_EL1, "ID_AA64PFR0_EL1" },
602  { ArmISA::MISCREG_ID_AA64PFR1_EL1, "ID_AA64PFR1_EL1" },
603  { ArmISA::MISCREG_ID_AA64DFR0_EL1, "ID_AA64DFR0_EL1" },
604  { ArmISA::MISCREG_ID_AA64DFR1_EL1, "ID_AA64DFR1_EL1" },
605  { ArmISA::MISCREG_ID_AA64AFR0_EL1, "ID_AA64AFR0_EL1" },
606  { ArmISA::MISCREG_ID_AA64AFR1_EL1, "ID_AA64AFR1_EL1" },
607  { ArmISA::MISCREG_ID_AA64ISAR0_EL1, "ID_AA64ISAR0_EL1" },
608  { ArmISA::MISCREG_ID_AA64ISAR1_EL1, "ID_AA64ISAR1_EL1" },
609  { ArmISA::MISCREG_ID_AA64MMFR0_EL1, "ID_AA64MMFR0_EL1" },
610  { ArmISA::MISCREG_ID_AA64MMFR1_EL1, "ID_AA64MMFR1_EL1" },
611  { ArmISA::MISCREG_CCSIDR_EL1, "CCSIDR_EL1" },
612  { ArmISA::MISCREG_CLIDR_EL1, "CLIDR_EL1" },
613  { ArmISA::MISCREG_AIDR_EL1, "AIDR_EL1" },
614  { ArmISA::MISCREG_CSSELR_EL1, "CSSELR_EL1" },
615  { ArmISA::MISCREG_CTR_EL0, "CTR_EL0" },
616  { ArmISA::MISCREG_DCZID_EL0, "DCZID_EL0" },
617  { ArmISA::MISCREG_VPIDR_EL2, "VPIDR_EL2" },
618  { ArmISA::MISCREG_VMPIDR_EL2, "VMPIDR_EL2" },
619  { ArmISA::MISCREG_SCTLR_EL1, "SCTLR_EL1" },
620  { ArmISA::MISCREG_ACTLR_EL1, "ACTLR_EL1" },
621  { ArmISA::MISCREG_CPACR_EL1, "CPACR_EL1" },
622  { ArmISA::MISCREG_SCTLR_EL2, "SCTLR_EL2" },
623  { ArmISA::MISCREG_ACTLR_EL2, "ACTLR_EL2" },
624  { ArmISA::MISCREG_HCR_EL2, "HCR_EL2" },
625  { ArmISA::MISCREG_MDCR_EL2, "MDCR_EL2" },
626  { ArmISA::MISCREG_CPTR_EL2, "CPTR_EL2" },
627  { ArmISA::MISCREG_HSTR_EL2, "HSTR_EL2" },
628  { ArmISA::MISCREG_HACR_EL2, "HACR_EL2" },
629  { ArmISA::MISCREG_SCTLR_EL3, "SCTLR_EL3" },
630  { ArmISA::MISCREG_ACTLR_EL3, "ACTLR_EL3" },
631  { ArmISA::MISCREG_SCR_EL3, "SCR_EL3" },
632  // ArmISA::MISCREG_SDER32_EL3?
633  { ArmISA::MISCREG_CPTR_EL3, "CPTR_EL3" },
634  { ArmISA::MISCREG_MDCR_EL3, "MDCR_EL3" },
635  { ArmISA::MISCREG_TTBR0_EL1, "TTBR0_EL1" },
636  { ArmISA::MISCREG_TTBR1_EL1, "TTBR1_EL1" },
637  { ArmISA::MISCREG_TCR_EL1, "TCR_EL1" },
638  { ArmISA::MISCREG_TTBR0_EL2, "TTBR0_EL2" },
639  { ArmISA::MISCREG_TCR_EL2, "TCR_EL2" },
640  { ArmISA::MISCREG_VTTBR_EL2, "VTTBR_EL2" },
641  { ArmISA::MISCREG_VTCR_EL2, "VTCR_EL2" },
642  { ArmISA::MISCREG_TTBR0_EL3, "TTBR0_EL3" },
643  { ArmISA::MISCREG_TCR_EL3, "TCR_EL3" },
644  // ArmISA::MISCREG_DACR32_EL2?
645  { ArmISA::MISCREG_SPSR_EL1, "SPSR_EL1" },
646  { ArmISA::MISCREG_ELR_EL1, "ELR_EL1" },
647  { ArmISA::MISCREG_SP_EL0, "SP_EL0" },
648  // ArmISA::MISCREG_SPSEL?
649  // ArmISA::MISCREG_CURRENTEL?
650  // ArmISA::MISCREG_NZCV?
651  // ArmISA::MISCREG_DAIF?
652  { ArmISA::MISCREG_FPCR, "FPCR" },
653  { ArmISA::MISCREG_FPSR, "FPSR" },
654  { ArmISA::MISCREG_DSPSR_EL0, "DSPSR_EL0" },
655  { ArmISA::MISCREG_DLR_EL0, "DLR_EL0" },
656  { ArmISA::MISCREG_SPSR_EL2, "SPSR_EL2" },
657  { ArmISA::MISCREG_ELR_EL2, "ELR_EL2" },
658  { ArmISA::MISCREG_SP_EL1, "SP_EL1" },
659  // ArmISA::MISCREG_SPSR_IRQ_AA64?
660  // ArmISA::MISCREG_SPSR_ABT_AA64?
661  // ArmISA::MISCREG_SPSR_UND_AA64?
662  // ArmISA::MISCREG_SPSR_FIQ_AA64?
663  { ArmISA::MISCREG_SPSR_EL3, "SPSR_EL3" },
664  { ArmISA::MISCREG_ELR_EL3, "ELR_EL3" },
665  { ArmISA::MISCREG_SP_EL2, "SP_EL2" },
666  { ArmISA::MISCREG_AFSR0_EL1, "AFSR0_EL1" },
667  { ArmISA::MISCREG_AFSR1_EL1, "AFSR1_EL1" },
668  { ArmISA::MISCREG_ESR_EL1, "ESR_EL1" },
669  // ArmISA::MISCREG_IFSR32_EL2?
670  { ArmISA::MISCREG_AFSR0_EL2, "AFSR0_EL2" },
671  { ArmISA::MISCREG_AFSR1_EL2, "AFSR1_EL2" },
672  { ArmISA::MISCREG_ESR_EL2, "ESR_EL2" },
673  // ArmISA::MISCREG_FPEXC32_EL2?
674  { ArmISA::MISCREG_AFSR0_EL3, "AFSR0_EL3" },
675  { ArmISA::MISCREG_AFSR1_EL3, "AFSR1_EL3" },
676  { ArmISA::MISCREG_ESR_EL3, "ESR_EL3" },
677  { ArmISA::MISCREG_FAR_EL1, "FAR_EL1" },
678  { ArmISA::MISCREG_FAR_EL2, "FAR_EL2" },
679  { ArmISA::MISCREG_HPFAR_EL2, "HPFAR_EL2" },
680  { ArmISA::MISCREG_FAR_EL3, "FAR_EL3" },
681  { ArmISA::MISCREG_IC_IALLUIS, "IC IALLUIS" },
682  { ArmISA::MISCREG_PAR_EL1, "PAR_EL1" },
683  { ArmISA::MISCREG_IC_IALLU, "IC IALLU" },
684  { ArmISA::MISCREG_DC_IVAC_Xt, "DC IVAC" }, //XXX verify
685  { ArmISA::MISCREG_DC_ISW_Xt, "DC ISW" }, //XXX verify
686  { ArmISA::MISCREG_AT_S1E1R_Xt, "AT S1E1R" }, //XXX verify
687  { ArmISA::MISCREG_AT_S1E1W_Xt, "AT S1E1W" }, //XXX verify
688  { ArmISA::MISCREG_AT_S1E0R_Xt, "AT S1E0R" }, //XXX verify
689  { ArmISA::MISCREG_AT_S1E0W_Xt, "AT S1E0W" }, //XXX verify
690  { ArmISA::MISCREG_DC_CSW_Xt, "DC CSW" }, //XXX verify
691  { ArmISA::MISCREG_DC_CISW_Xt, "DC CISW" }, //XXX verify
692  { ArmISA::MISCREG_DC_ZVA_Xt, "DC ZVA" }, //XXX verify
693  { ArmISA::MISCREG_IC_IVAU_Xt, "IC IVAU" }, //XXX verify
694  { ArmISA::MISCREG_DC_CVAC_Xt, "DC CVAC" }, //XXX verify
695  { ArmISA::MISCREG_DC_CVAU_Xt, "DC CVAU" }, //XXX verify
696  { ArmISA::MISCREG_DC_CIVAC_Xt, "DC CIVAC" }, //XXX verify
697  { ArmISA::MISCREG_AT_S1E2R_Xt, "AT S1E2R" }, //XXX verify
698  { ArmISA::MISCREG_AT_S1E2W_Xt, "AT S1E2W" }, //XXX verify
699  { ArmISA::MISCREG_AT_S12E1R_Xt, "AT S12E1R" }, //XXX verify
700  { ArmISA::MISCREG_AT_S12E1W_Xt, "AT S12E1W" }, //XXX verify
701  { ArmISA::MISCREG_AT_S12E0R_Xt, "AT S12E0R" }, //XXX verify
702  { ArmISA::MISCREG_AT_S12E0W_Xt, "AT S12E0W" }, //XXX verify
703  { ArmISA::MISCREG_AT_S1E3R_Xt, "AT S1E3R" }, //XXX verify
704  { ArmISA::MISCREG_AT_S1E3W_Xt, "AT S1E3W" }, //XXX verify
705  { ArmISA::MISCREG_TLBI_VMALLE1IS, "TLBI VMALLE1IS" },
706  { ArmISA::MISCREG_TLBI_VAE1IS_Xt, "TLBI VAE1IS" }, //XXX verify
707  { ArmISA::MISCREG_TLBI_ASIDE1IS_Xt, "TLBI ASIDE1IS" }, //XXX verify
708  { ArmISA::MISCREG_TLBI_VAAE1IS_Xt, "TLBI VAAE1IS" }, //XXX verify
709  { ArmISA::MISCREG_TLBI_VALE1IS_Xt, "TLBI VALE1IS" }, //XXX verify
710  { ArmISA::MISCREG_TLBI_VAALE1IS_Xt, "TLBI VAALE1IS" }, //XXX verify
711  { ArmISA::MISCREG_TLBI_VMALLE1, "TLBI VMALLE1" },
712  { ArmISA::MISCREG_TLBI_VAE1_Xt, "TLBI VAE1" }, //XXX verify
713  { ArmISA::MISCREG_TLBI_ASIDE1_Xt, "TLBI ASIDE1" }, //XXX verify
714  { ArmISA::MISCREG_TLBI_VAAE1_Xt, "TLBI VAAE1" }, //XXX verify
715  { ArmISA::MISCREG_TLBI_VALE1_Xt, "TLBI VALE1" }, //XXX verify
716  { ArmISA::MISCREG_TLBI_VAALE1_Xt, "TLBI VAALE1" }, //XXX verify
717  { ArmISA::MISCREG_TLBI_IPAS2E1IS_Xt, "TLBI IPAS2E1IS" }, //XXX verify
718  { ArmISA::MISCREG_TLBI_IPAS2LE1IS_Xt, "TLBI IPAS2LE1IS" }, //XXX verify
719  { ArmISA::MISCREG_TLBI_ALLE2IS, "TLBI ALLE2IS" },
720  { ArmISA::MISCREG_TLBI_VAE2IS_Xt, "TLBI VAE2IS" }, //XXX verify
721  { ArmISA::MISCREG_TLBI_ALLE1IS, "TLBI ALLE1IS" },
722  { ArmISA::MISCREG_TLBI_VALE2IS_Xt, "TLBI VALE2IS" }, //XXX verify
723  { ArmISA::MISCREG_TLBI_VMALLS12E1IS, "TLBI VMALLS12E1IS" },
724  { ArmISA::MISCREG_TLBI_IPAS2E1_Xt, "TLBI IPAS2E1" }, //XXX verify
725  { ArmISA::MISCREG_TLBI_IPAS2LE1_Xt, "TLBI IPAS2LE1" }, //XXX verify
726  { ArmISA::MISCREG_TLBI_ALLE2, "TLBI ALLE2" },
727  { ArmISA::MISCREG_TLBI_VAE2_Xt, "TLBI VAE2" }, //XXX verify
728  { ArmISA::MISCREG_TLBI_ALLE1, "TLBI ALLE1" },
729  { ArmISA::MISCREG_TLBI_VALE2_Xt, "TLBI VALE2" }, //XXX verify
730  { ArmISA::MISCREG_TLBI_VMALLS12E1, "TLBI VMALLS12E1" },
731  { ArmISA::MISCREG_TLBI_ALLE3IS, "TLBI ALLE3IS" },
732  { ArmISA::MISCREG_TLBI_VAE3IS_Xt, "TLBI VAE3IS" }, //XXX verify
733  { ArmISA::MISCREG_TLBI_VALE3IS_Xt, "TLBI VALE3IS" }, //XXX verify
734  { ArmISA::MISCREG_TLBI_ALLE3, "TLBI ALLE3" },
735  { ArmISA::MISCREG_TLBI_VAE3_Xt, "TLBI VAE3" }, //XXX verify
736  { ArmISA::MISCREG_TLBI_VALE3_Xt, "TLBI VALE3" }, //XXX verify
737  { ArmISA::MISCREG_PMINTENSET_EL1, "PMINTENSET_EL1" },
738  { ArmISA::MISCREG_PMINTENCLR_EL1, "PMINTENCLR_EL1" },
739  { ArmISA::MISCREG_PMCR_EL0, "PMCR_EL0" },
740  { ArmISA::MISCREG_PMCNTENSET_EL0, "PMCNTENSET_EL0" },
741  { ArmISA::MISCREG_PMCNTENCLR_EL0, "PMCNTENCLR_EL0" },
742  { ArmISA::MISCREG_PMOVSCLR_EL0, "PMOVSCLR_EL0" },
743  { ArmISA::MISCREG_PMSWINC_EL0, "PMSWINC_EL0" },
744  { ArmISA::MISCREG_PMSELR_EL0, "PMSELR_EL0" },
745  { ArmISA::MISCREG_PMCEID0_EL0, "PMCEID0_EL0" },
746  { ArmISA::MISCREG_PMCEID1_EL0, "PMCEID1_EL0" },
747  { ArmISA::MISCREG_PMCCNTR_EL0, "PMCCNTR_EL0" },
748  { ArmISA::MISCREG_PMXEVTYPER_EL0, "PMXEVTYPER_EL0" },
749  { ArmISA::MISCREG_PMCCFILTR_EL0, "PMCCFILTR_EL0" },
750  { ArmISA::MISCREG_PMXEVCNTR_EL0, "PMXEVCNTR_EL0" },
751  { ArmISA::MISCREG_PMUSERENR_EL0, "PMUSERENR_EL0" },
752  { ArmISA::MISCREG_PMOVSSET_EL0, "PMOVSSET_EL0" },
753  { ArmISA::MISCREG_MAIR_EL1, "MAIR_EL1" },
754  { ArmISA::MISCREG_AMAIR_EL1, "AMAIR_EL1" },
755  { ArmISA::MISCREG_MAIR_EL2, "MAIR_EL2" },
756  { ArmISA::MISCREG_AMAIR_EL2, "AMAIR_EL2" },
757  { ArmISA::MISCREG_MAIR_EL3, "MAIR_EL3" },
758  { ArmISA::MISCREG_AMAIR_EL3, "AMAIR_EL3" },
759  // ArmISA::MISCREG_L2CTLR_EL1?
760  // ArmISA::MISCREG_L2ECTLR_EL1?
761  { ArmISA::MISCREG_VBAR_EL1, "VBAR_EL1" },
762  // ArmISA::MISCREG_RVBAR_EL1?
763  { ArmISA::MISCREG_ISR_EL1, "ISR_EL1" },
764  { ArmISA::MISCREG_VBAR_EL2, "VBAR_EL2" },
765  // ArmISA::MISCREG_RVBAR_EL2?
766  { ArmISA::MISCREG_VBAR_EL3, "VBAR_EL3" },
767  { ArmISA::MISCREG_RVBAR_EL3, "RVBAR_EL3" },
768  { ArmISA::MISCREG_RMR_EL3, "RMR_EL3" },
769  { ArmISA::MISCREG_CONTEXTIDR_EL1, "CONTEXTIDR_EL1" },
770  { ArmISA::MISCREG_TPIDR_EL1, "TPIDR_EL1" },
771  { ArmISA::MISCREG_TPIDR_EL0, "TPIDR_EL0" },
772  { ArmISA::MISCREG_TPIDRRO_EL0, "TPIDRRO_EL0" },
773  { ArmISA::MISCREG_TPIDR_EL2, "TPIDR_EL2" },
774  { ArmISA::MISCREG_TPIDR_EL3, "TPIDR_EL3" },
775  { ArmISA::MISCREG_CNTKCTL_EL1, "CNTKCTL_EL1" },
776  { ArmISA::MISCREG_CNTFRQ_EL0, "CNTFRQ_EL0" },
777  { ArmISA::MISCREG_CNTPCT_EL0, "CNTPCT_EL0" },
778  { ArmISA::MISCREG_CNTVCT_EL0, "CNTVCT_EL0" },
779  { ArmISA::MISCREG_CNTP_TVAL_EL0, "CNTP_TVAL_EL0" },
780  { ArmISA::MISCREG_CNTP_CTL_EL0, "CNTP_CTL_EL0" },
781  { ArmISA::MISCREG_CNTP_CVAL_EL0, "CNTP_CVAL_EL0" },
782  { ArmISA::MISCREG_CNTV_TVAL_EL0, "CNTV_TVAL_EL0" },
783  { ArmISA::MISCREG_CNTV_CTL_EL0, "CNTV_CTL_EL0" },
784  { ArmISA::MISCREG_CNTV_CVAL_EL0, "CNTV_CVAL_EL0" },
785  { ArmISA::MISCREG_PMEVCNTR0_EL0, "PMEVCNTR0_EL0" },
786  { ArmISA::MISCREG_PMEVCNTR1_EL0, "PMEVCNTR1_EL0" },
787  { ArmISA::MISCREG_PMEVCNTR2_EL0, "PMEVCNTR2_EL0" },
788  { ArmISA::MISCREG_PMEVCNTR3_EL0, "PMEVCNTR3_EL0" },
789  { ArmISA::MISCREG_PMEVCNTR4_EL0, "PMEVCNTR4_EL0" },
790  { ArmISA::MISCREG_PMEVCNTR5_EL0, "PMEVCNTR5_EL0" },
791  { ArmISA::MISCREG_PMEVTYPER0_EL0, "PMEVTYPER0_EL0" },
792  { ArmISA::MISCREG_PMEVTYPER1_EL0, "PMEVTYPER1_EL0" },
793  { ArmISA::MISCREG_PMEVTYPER2_EL0, "PMEVTYPER2_EL0" },
794  { ArmISA::MISCREG_PMEVTYPER3_EL0, "PMEVTYPER3_EL0" },
795  { ArmISA::MISCREG_PMEVTYPER4_EL0, "PMEVTYPER4_EL0" },
796  { ArmISA::MISCREG_PMEVTYPER5_EL0, "PMEVTYPER5_EL0" },
797  { ArmISA::MISCREG_CNTVOFF_EL2, "CNTVOFF_EL2" },
798  { ArmISA::MISCREG_CNTHCTL_EL2, "CNTHCTL_EL2" },
799  { ArmISA::MISCREG_CNTHP_TVAL_EL2, "CNTHP_TVAL_EL2" },
800  { ArmISA::MISCREG_CNTHP_CTL_EL2, "CNTHP_CTL_EL2" },
801  { ArmISA::MISCREG_CNTHP_CVAL_EL2, "CNTHP_CVAL_EL2" },
802  { ArmISA::MISCREG_CNTPS_TVAL_EL1, "CNTPS_TVAL_EL1" },
803  { ArmISA::MISCREG_CNTPS_CTL_EL1, "CNTPS_CTL_EL1" },
804  { ArmISA::MISCREG_CNTPS_CVAL_EL1, "CNTPS_CVAL_EL1" },
805  // ArmISA::MISCREG_IL1DATA0_EL1?
806  // ArmISA::MISCREG_IL1DATA1_EL1?
807  // ArmISA::MISCREG_IL1DATA2_EL1?
808  // ArmISA::MISCREG_IL1DATA3_EL1?
809  // ArmISA::MISCREG_DL1DATA0_EL1?
810  // ArmISA::MISCREG_DL1DATA1_EL1?
811  // ArmISA::MISCREG_DL1DATA2_EL1?
812  // ArmISA::MISCREG_DL1DATA3_EL1?
813  // ArmISA::MISCREG_DL1DATA4_EL1?
814  // ArmISA::MISCREG_L2ACTLR_EL1?
815  { ArmISA::MISCREG_CPUACTLR_EL1, "CPUACTLR_EL1" },
816  { ArmISA::MISCREG_CPUECTLR_EL1, "CPUECTLR_EL1" },
817  { ArmISA::MISCREG_CPUMERRSR_EL1, "CPUMERRSR_EL1" },
818  { ArmISA::MISCREG_L2MERRSR_EL1, "L2MERRSR_EL1" },
819  // ArmISA::MISCREG_CBAR_EL1?
820  { ArmISA::MISCREG_CONTEXTIDR_EL2, "CONTEXTIDR_EL2" },
821 
822  // Introduced in ARMv8.1
823  { ArmISA::MISCREG_TTBR1_EL2, "TTBR1_EL2" },
824  { ArmISA::MISCREG_CNTHV_CTL_EL2, "CNTHV_CTL_EL2" },
825  { ArmISA::MISCREG_CNTHV_CVAL_EL2, "CNTHV_CVAL_EL2" },
826  { ArmISA::MISCREG_CNTHV_TVAL_EL2, "CNTHV_TVAL_EL2" },
827 
828  // RAS extension (unimplemented)
829  { ArmISA::MISCREG_ERRIDR_EL1, "ERRIDR_EL1" },
830  { ArmISA::MISCREG_ERRSELR_EL1, "ERRSELR_EL1" },
831  { ArmISA::MISCREG_ERXFR_EL1, "ERXFR_EL1" },
832  { ArmISA::MISCREG_ERXCTLR_EL1, "ERXCTLR_EL1" },
833  { ArmISA::MISCREG_ERXSTATUS_EL1, "ERXSTATUS_EL1" },
834  { ArmISA::MISCREG_ERXADDR_EL1, "ERXADDR_EL1" },
835  { ArmISA::MISCREG_ERXMISC0_EL1, "ERXMISC0_EL1" },
836  { ArmISA::MISCREG_ERXMISC1_EL1, "ERXMISC1_EL1" },
837  { ArmISA::MISCREG_DISR_EL1, "DISR_EL1" },
838  { ArmISA::MISCREG_VSESR_EL2, "VSESR_EL2" },
839  { ArmISA::MISCREG_VDISR_EL2, "VDISR_EL2" }
840 });
841 
843  { ArmISA::INTREG_R0, "R0" },
844  { ArmISA::INTREG_R1, "R1" },
845  { ArmISA::INTREG_R2, "R2" },
846  { ArmISA::INTREG_R3, "R3" },
847  { ArmISA::INTREG_R4, "R4" },
848  { ArmISA::INTREG_R5, "R5" },
849  { ArmISA::INTREG_R6, "R6" },
850  { ArmISA::INTREG_R7, "R7" },
851  { ArmISA::INTREG_R8, "R8" },
852  { ArmISA::INTREG_R9, "R9" },
853  { ArmISA::INTREG_R10, "R10" },
854  { ArmISA::INTREG_R11, "R11" },
855  { ArmISA::INTREG_R12, "R12" },
856  { ArmISA::INTREG_R13, "R13" },
857  { ArmISA::INTREG_R14, "R14" },
858  { ArmISA::INTREG_R15, "R15" }
859 });
860 
862  { ArmISA::INTREG_X0, "X0" },
863  { ArmISA::INTREG_X1, "X1" },
864  { ArmISA::INTREG_X2, "X2" },
865  { ArmISA::INTREG_X3, "X3" },
866  { ArmISA::INTREG_X4, "X4" },
867  { ArmISA::INTREG_X5, "X5" },
868  { ArmISA::INTREG_X6, "X6" },
869  { ArmISA::INTREG_X7, "X7" },
870  { ArmISA::INTREG_X8, "X8" },
871  { ArmISA::INTREG_X9, "X9" },
872  { ArmISA::INTREG_X10, "X10" },
873  { ArmISA::INTREG_X11, "X11" },
874  { ArmISA::INTREG_X12, "X12" },
875  { ArmISA::INTREG_X13, "X13" },
876  { ArmISA::INTREG_X14, "X14" },
877  { ArmISA::INTREG_X15, "X15" },
878  { ArmISA::INTREG_X16, "X16" },
879  { ArmISA::INTREG_X17, "X17" },
880  { ArmISA::INTREG_X18, "X18" },
881  { ArmISA::INTREG_X19, "X19" },
882  { ArmISA::INTREG_X20, "X20" },
883  { ArmISA::INTREG_X21, "X21" },
884  { ArmISA::INTREG_X22, "X22" },
885  { ArmISA::INTREG_X23, "X23" },
886  { ArmISA::INTREG_X24, "X24" },
887  { ArmISA::INTREG_X25, "X25" },
888  { ArmISA::INTREG_X26, "X26" },
889  { ArmISA::INTREG_X27, "X27" },
890  { ArmISA::INTREG_X28, "X28" },
891  { ArmISA::INTREG_X29, "X29" },
892  { ArmISA::INTREG_X30, "X30" },
893  { ArmISA::INTREG_SPX, "SP" },
894 });
895 
897  { ArmISA::INTREG_R0, "X0" },
898  { ArmISA::INTREG_R1, "X1" },
899  { ArmISA::INTREG_R2, "X2" },
900  { ArmISA::INTREG_R3, "X3" },
901  { ArmISA::INTREG_R4, "X4" },
902  { ArmISA::INTREG_R5, "X5" },
903  { ArmISA::INTREG_R6, "X6" },
904  { ArmISA::INTREG_R7, "X7" },
905  { ArmISA::INTREG_R8, "X8" },
906  { ArmISA::INTREG_R9, "X9" },
907  { ArmISA::INTREG_R10, "X10" },
908  { ArmISA::INTREG_R11, "X11" },
909  { ArmISA::INTREG_R12, "X12" },
910  { ArmISA::INTREG_R13, "X13" },
911  { ArmISA::INTREG_R14, "X14" },
912  // Skip PC.
913  { ArmISA::INTREG_R13_SVC, "X19" },
914  { ArmISA::INTREG_R14_SVC, "X18" },
915  { ArmISA::INTREG_R13_MON, "R13" }, // Need to be in monitor mode?
916  { ArmISA::INTREG_R14_MON, "R14" }, // Need to be in monitor mode?
917  { ArmISA::INTREG_R13_HYP, "X15" },
918  { ArmISA::INTREG_R13_ABT, "X21" },
919  { ArmISA::INTREG_R14_ABT, "X20" },
920  { ArmISA::INTREG_R13_UND, "X23" },
921  { ArmISA::INTREG_R14_UND, "X22" },
922  { ArmISA::INTREG_R13_IRQ, "X17" },
923  { ArmISA::INTREG_R14_IRQ, "X16" },
924  { ArmISA::INTREG_R8_FIQ, "X24" },
925  { ArmISA::INTREG_R9_FIQ, "X25" },
926  { ArmISA::INTREG_R10_FIQ, "X26" },
927  { ArmISA::INTREG_R11_FIQ, "X27" },
928  { ArmISA::INTREG_R12_FIQ, "X28" },
929  { ArmISA::INTREG_R13_FIQ, "X29" },
930  { ArmISA::INTREG_R14_FIQ, "X30" },
931  // Skip zero, ureg0-2, and dummy regs.
932  { ArmISA::INTREG_SP0, "SP_EL0" },
933  { ArmISA::INTREG_SP1, "SP_EL1" },
934  { ArmISA::INTREG_SP2, "SP_EL2" },
935  { ArmISA::INTREG_SP3, "SP_EL3" },
936 });
937 
939  { ArmISA::CCREG_NZ, "CPSR" },
940  { ArmISA::CCREG_C, "CPSR.C" },
941  { ArmISA::CCREG_V, "CPSR.V" },
942  { ArmISA::CCREG_GE, "CPSR.GE" },
943  { ArmISA::CCREG_FP, "FPSCR" },
944 });
945 
947  { 0, "V0" }, { 1, "V1" }, { 2, "V2" }, { 3, "V3" },
948  { 4, "V4" }, { 5, "V5" }, { 6, "V6" }, { 7, "V7" },
949  { 8, "V8" }, { 9, "V9" }, { 10, "V10" }, { 11, "V11" },
950  { 12, "V12" }, { 13, "V13" }, { 14, "V14" }, { 15, "V15" },
951  { 16, "V16" }, { 17, "V17" }, { 18, "V18" }, { 19, "V19" },
952  { 20, "V20" }, { 21, "V21" }, { 22, "V22" }, { 23, "V23" },
953  { 24, "V24" }, { 25, "V25" }, { 26, "V26" }, { 27, "V27" },
954  { 28, "V28" }, { 29, "V29" }, { 30, "V30" }, { 31, "V31" }
955 });
956 
958 
959 } // namespace fastmodel
960 } // namespace gem5
gem5::fastmodel::CortexA76TC::ccRegIdxNameMap
static IdxNameMap ccRegIdxNameMap
Definition: thread_context.hh:49
gem5::ArmISA::MISCREG_CTR_EL0
@ MISCREG_CTR_EL0
Definition: misc.hh:575
gem5::ArmISA::MISCREG_SP_EL0
@ MISCREG_SP_EL0
Definition: misc.hh:616
gem5::ArmISA::MISCREG_DCCMVAU
@ MISCREG_DCCMVAU
Definition: misc.hh:316
gem5::ArmISA::MISCREG_PMSWINC
@ MISCREG_PMSWINC
Definition: misc.hh:355
gem5::ArmISA::MISCREG_FAR_EL1
@ MISCREG_FAR_EL1
Definition: misc.hh:649
gem5::ArmISA::MISCREG_HAMAIR0
@ MISCREG_HAMAIR0
Definition: misc.hh:389
gem5::ArmISA::MISCREG_NSACR
@ MISCREG_NSACR
Definition: misc.hh:245
gem5::ArmISA::MISCREG_IC_IALLUIS
@ MISCREG_IC_IALLUIS
Definition: misc.hh:654
gem5::ArmISA::MISCREG_CPSR
@ MISCREG_CPSR
Definition: misc.hh:61
gem5::ArmISA::MISCREG_ID_MMFR4
@ MISCREG_ID_MMFR4
Definition: misc.hh:219
gem5::ArmISA::MISCREG_CPTR_EL2
@ MISCREG_CPTR_EL2
Definition: misc.hh:588
gem5::ArmISA::MISCREG_PMCCFILTR
@ MISCREG_PMCCFILTR
Definition: misc.hh:361
gem5::ArmISA::MISCREG_PMCEID1
@ MISCREG_PMCEID1
Definition: misc.hh:358
gem5::ArmISA::CCREG_C
@ CCREG_C
Definition: cc.hh:50
gem5::ArmISA::MISCREG_VTTBR
@ MISCREG_VTTBR
Definition: misc.hh:448
gem5::ArmISA::MISCREG_PMCR
@ MISCREG_PMCR
Definition: misc.hh:351
gem5::ArmISA::MISCREG_CNTV_TVAL
@ MISCREG_CNTV_TVAL
Definition: misc.hh:427
gem5::fastmodel::CortexA76TC::bpSpaceIds
static std::vector< iris::MemorySpaceId > bpSpaceIds
Definition: thread_context.hh:51
gem5::ArmISA::MISCREG_CSSELR
@ MISCREG_CSSELR
Definition: misc.hh:230
gem5::Iris::ThreadContext::IdxNameMap
std::map< int, std::string > IdxNameMap
Definition: thread_context.hh:57
gem5::Iris::PhysicalMemoryNonSecureMsn
@ PhysicalMemoryNonSecureMsn
Definition: memory_spaces.hh:48
gem5::ArmISA::MISCREG_DCCMVAC
@ MISCREG_DCCMVAC
Definition: misc.hh:312
gem5::ArmISA::MISCREG_TTBR0_EL2
@ MISCREG_TTBR0_EL2
Definition: misc.hh:603
gem5::ArmISA::MISCREG_DBGPRCR_EL1
@ MISCREG_DBGPRCR_EL1
Definition: misc.hh:531
gem5::ArmISA::MISCREG_AMAIR_EL1
@ MISCREG_AMAIR_EL1
Definition: misc.hh:728
gem5::ArmISA::MISCREG_AMAIR0_NS
@ MISCREG_AMAIR0_NS
Definition: misc.hh:382
gem5::ArmISA::MISCREG_VBAR_EL3
@ MISCREG_VBAR_EL3
Definition: misc.hh:742
gem5::ArmISA::MISCREG_AT_S12E0R_Xt
@ MISCREG_AT_S12E0R_Xt
Definition: misc.hh:674
gem5::ArmISA::MISCREG_PMCCFILTR_EL0
@ MISCREG_PMCCFILTR_EL0
Definition: misc.hh:722
gem5::ArmISA::MISCREG_PMXEVTYPER_EL0
@ MISCREG_PMXEVTYPER_EL0
Definition: misc.hh:721
gem5::ArmISA::MODE_MON
@ MODE_MON
Definition: types.hh:285
gem5::ArmISA::MISCREG_PMOVSCLR_EL0
@ MISCREG_PMOVSCLR_EL0
Definition: misc.hh:715
gem5::ArmISA::MISCREG_HSTR
@ MISCREG_HSTR
Definition: misc.hh:252
gem5::Iris::PhysicalMemorySecureMsn
@ PhysicalMemorySecureMsn
Definition: memory_spaces.hh:47
gem5::ArmISA::MISCREG_PMOVSR
@ MISCREG_PMOVSR
Definition: misc.hh:354
gem5::ArmISA::MISCREG_MDCR_EL3
@ MISCREG_MDCR_EL3
Definition: misc.hh:596
gem5::ArmISA::MISCREG_TLBI_ALLE3IS
@ MISCREG_TLBI_ALLE3IS
Definition: misc.hh:704
gem5::ArmISA::MISCREG_TTBR0_EL3
@ MISCREG_TTBR0_EL3
Definition: misc.hh:609
gem5::ArmISA::MISCREG_DBGWVR1_EL1
@ MISCREG_DBGWVR1_EL1
Definition: misc.hh:491
gem5::ArmISA::MISCREG_DC_CISW_Xt
@ MISCREG_DC_CISW_Xt
Definition: misc.hh:664
gem5::ArmISA::MISCREG_ID_ISAR5
@ MISCREG_ID_ISAR5
Definition: misc.hh:225
gem5::ArmISA::MISCREG_DBGDTRRXext
@ MISCREG_DBGDTRRXext
Definition: misc.hh:102
gem5::ArmISA::MISCREG_DC_CIVAC_Xt
@ MISCREG_DC_CIVAC_Xt
Definition: misc.hh:669
gem5::RegVal
uint64_t RegVal
Definition: types.hh:173
gem5::ArmISA::MISCREG_DBGWVR1
@ MISCREG_DBGWVR1
Definition: misc.hh:139
gem5::ArmISA::MISCREG_TPIDRURO_NS
@ MISCREG_TPIDRURO_NS
Definition: misc.hh:406
gem5::ArmISA::MISCREG_PMCNTENCLR
@ MISCREG_PMCNTENCLR
Definition: misc.hh:353
gem5::ArmISA::MISCREG_TLBI_VAAE1IS_Xt
@ MISCREG_TLBI_VAAE1IS_Xt
Definition: misc.hh:681
gem5::ArmISA::MISCREG_SCTLR_EL3
@ MISCREG_SCTLR_EL3
Definition: misc.hh:591
gem5::ArmISA::MISCREG_AT_S1E3W_Xt
@ MISCREG_AT_S1E3W_Xt
Definition: misc.hh:677
gem5::ArmISA::MISCREG_ICIALLU
@ MISCREG_ICIALLU
Definition: misc.hh:297
gem5::ArmISA::MISCREG_PMEVTYPER5_EL0
@ MISCREG_PMEVTYPER5_EL0
Definition: misc.hh:801
gem5::ArmISA::MISCREG_CONTEXTIDR_NS
@ MISCREG_CONTEXTIDR_NS
Definition: misc.hh:400
gem5::ArmISA::MISCREG_HACR_EL2
@ MISCREG_HACR_EL2
Definition: misc.hh:590
gem5::ArmISA::MISCREG_CNTPS_CTL_EL1
@ MISCREG_CNTPS_CTL_EL1
Definition: misc.hh:770
gem5::ArmISA::MISCREG_DBGWCR3_EL1
@ MISCREG_DBGWCR3_EL1
Definition: misc.hh:509
memory_spaces.hh
gem5::ArmISA::MISCREG_ID_MMFR3_EL1
@ MISCREG_ID_MMFR3_EL1
Definition: misc.hh:549
gem5::Iris::ThreadContext::vecRegIds
ResourceIds vecRegIds
Definition: thread_context.hh:95
gem5::ArmISA::MISCREG_TLBI_ALLE1
@ MISCREG_TLBI_ALLE1
Definition: misc.hh:701
gem5::ArmISA::MISCREG_CNTVCT
@ MISCREG_CNTVCT
Definition: misc.hh:415
gem5::ArmISA::MISCREG_AT_S12E0W_Xt
@ MISCREG_AT_S12E0W_Xt
Definition: misc.hh:675
gem5::ArmISA::MISCREG_CPUACTLR_EL1
@ MISCREG_CPUACTLR_EL1
Definition: misc.hh:812
gem5::ArmISA::MISCREG_VPIDR_EL2
@ MISCREG_VPIDR_EL2
Definition: misc.hh:577
gem5::ArmISA::MISCREG_AIDR_EL1
@ MISCREG_AIDR_EL1
Definition: misc.hh:573
gem5::ArmISA::MISCREG_MPIDR
@ MISCREG_MPIDR
Definition: misc.hh:209
gem5::ArmISA::MISCREG_CNTFRQ
@ MISCREG_CNTFRQ
Definition: misc.hh:413
gem5::ArmISA::MISCREG_DBGBCR3_EL1
@ MISCREG_DBGBCR3_EL1
Definition: misc.hh:477
gem5::ArmISA::MISCREG_PMINTENCLR_EL1
@ MISCREG_PMINTENCLR_EL1
Definition: misc.hh:711
gem5::ArmISA::MISCREG_CNTV_CTL_EL0
@ MISCREG_CNTV_CTL_EL0
Definition: misc.hh:759
gem5::ArmISA::MISCREG_ID_ISAR1_EL1
@ MISCREG_ID_ISAR1_EL1
Definition: misc.hh:552
gem5::ArmISA::MISCREG_ATS1CUW
@ MISCREG_ATS1CUW
Definition: misc.hh:307
gem5::fastmodel::CortexA76TC::getBpSpaceIds
const std::vector< iris::MemorySpaceId > & getBpSpaceIds() const override
Definition: thread_context.cc:188
gem5::ArmISA::MISCREG_DC_CVAC_Xt
@ MISCREG_DC_CVAC_Xt
Definition: misc.hh:667
gem5::ArmISA::MISCREG_TCR_EL2
@ MISCREG_TCR_EL2
Definition: misc.hh:604
gem5::ArmISA::MISCREG_CNTPS_TVAL_EL1
@ MISCREG_CNTPS_TVAL_EL1
Definition: misc.hh:772
gem5::ArmISA::MISCREG_SPSR_FIQ
@ MISCREG_SPSR_FIQ
Definition: misc.hh:63
gem5::ArmISA::MISCREG_CNTP_CTL_EL0
@ MISCREG_CNTP_CTL_EL0
Definition: misc.hh:756
gem5::ArmISA::MISCREG_TLBI_IPAS2E1IS_Xt
@ MISCREG_TLBI_IPAS2E1IS_Xt
Definition: misc.hh:690
gem5::ArmISA::MISCREG_VPIDR
@ MISCREG_VPIDR
Definition: misc.hh:233
gem5::ArmISA::MISCREG_HSTR_EL2
@ MISCREG_HSTR_EL2
Definition: misc.hh:589
gem5::ArmISA::MISCREG_PMEVCNTR5_EL0
@ MISCREG_PMEVCNTR5_EL0
Definition: misc.hh:795
gem5::ArmISA::MISCREG_DBGBCR5
@ MISCREG_DBGBCR5
Definition: misc.hh:127
gem5::ArmISA::MISCREG_MDCR_EL2
@ MISCREG_MDCR_EL2
Definition: misc.hh:587
gem5::ArmISA::MISCREG_DBGBCR1_EL1
@ MISCREG_DBGBCR1_EL1
Definition: misc.hh:475
gem5::ArmISA::MISCREG_TLBI_VAAE1_Xt
@ MISCREG_TLBI_VAAE1_Xt
Definition: misc.hh:687
gem5::ArmISA::MISCREG_MVFR1
@ MISCREG_MVFR1
Definition: misc.hh:73
gem5::ArmISA::MISCREG_CNTHCTL
@ MISCREG_CNTHCTL
Definition: misc.hh:429
gem5::ArmISA::MISCREG_ATS12NSOUR
@ MISCREG_ATS12NSOUR
Definition: misc.hh:310
gem5::ArmISA::MISCREG_DCCSW
@ MISCREG_DCCSW
Definition: misc.hh:313
gem5::ArmISA::MISCREG_PMSELR_EL0
@ MISCREG_PMSELR_EL0
Definition: misc.hh:717
gem5::ArmISA::MISCREG_IC_IVAU_Xt
@ MISCREG_IC_IVAU_Xt
Definition: misc.hh:666
gem5::ArmISA::MISCREG_CNTKCTL
@ MISCREG_CNTKCTL
Definition: misc.hh:428
gem5::ArmISA::MISCREG_ACTLR_EL3
@ MISCREG_ACTLR_EL3
Definition: misc.hh:592
gem5::fastmodel::CortexA76TC::CortexA76TC
CortexA76TC(gem5::BaseCPU *cpu, int id, System *system, gem5::BaseMMU *mmu, gem5::BaseISA *isa, iris::IrisConnectionInterface *iris_if, const std::string &iris_path)
Definition: thread_context.cc:42
gem5::ArmISA::MISCREG_SCR_EL3
@ MISCREG_SCR_EL3
Definition: misc.hh:593
gem5::ArmISA::MISCREG_AMAIR1_NS
@ MISCREG_AMAIR1_NS
Definition: misc.hh:385
gem5::ArmISA::MISCREG_DISR_EL1
@ MISCREG_DISR_EL1
Definition: misc.hh:1088
gem5::ArmISA::CCREG_NZ
@ CCREG_NZ
Definition: cc.hh:49
gem5::ArmISA::MISCREG_DC_CSW_Xt
@ MISCREG_DC_CSW_Xt
Definition: misc.hh:663
gem5::ArmISA::MISCREG_DBGBCR0
@ MISCREG_DBGBCR0
Definition: misc.hh:122
gem5::ArmISA::MISCREG_HAMAIR1
@ MISCREG_HAMAIR1
Definition: misc.hh:390
gem5::ArmISA::MISCREG_ID_ISAR5_EL1
@ MISCREG_ID_ISAR5_EL1
Definition: misc.hh:556
gem5::ArmISA::MISCREG_ICIMVAU
@ MISCREG_ICIMVAU
Definition: misc.hh:298
gem5::ArmISA::MISCREG_DBGWVR3_EL1
@ MISCREG_DBGWVR3_EL1
Definition: misc.hh:493
gem5::ArmISA::MISCREG_TLBI_IPAS2LE1IS_Xt
@ MISCREG_TLBI_IPAS2LE1IS_Xt
Definition: misc.hh:691
gem5::ArmISA::MISCREG_CNTP_TVAL
@ MISCREG_CNTP_TVAL
Definition: misc.hh:422
gem5::ArmISA::MISCREG_TTBR1_EL1
@ MISCREG_TTBR1_EL1
Definition: misc.hh:599
gem5::ArmISA::MISCREG_VBAR_EL2
@ MISCREG_VBAR_EL2
Definition: misc.hh:740
gem5::fastmodel::CortexA76TC::initFromIrisInstance
void initFromIrisInstance(const ResourceMap &resources) override
Definition: thread_context.cc:87
gem5::ArmISA::MISCREG_TLBI_VMALLS12E1IS
@ MISCREG_TLBI_VMALLS12E1IS
Definition: misc.hh:696
gem5::ArmISA::MISCREG_TLBI_VALE2_Xt
@ MISCREG_TLBI_VALE2_Xt
Definition: misc.hh:702
gem5::ArmISA::MISCREG_AFSR1_EL2
@ MISCREG_AFSR1_EL2
Definition: misc.hh:643
gem5::ArmISA::MISCREG_TPIDRPRW_NS
@ MISCREG_TPIDRPRW_NS
Definition: misc.hh:409
gem5::ArmISA::MISCREG_ID_MMFR0_EL1
@ MISCREG_ID_MMFR0_EL1
Definition: misc.hh:546
gem5::ArmISA::MISCREG_MDRAR_EL1
@ MISCREG_MDRAR_EL1
Definition: misc.hh:527
gem5::fastmodel::CortexA76TC::vecRegIdxNameMap
static IdxNameMap vecRegIdxNameMap
Definition: thread_context.hh:50
gem5::ArmISA::MISCREG_DCISW
@ MISCREG_DCISW
Definition: misc.hh:303
gem5::ArmISA::MISCREG_HSCTLR
@ MISCREG_HSCTLR
Definition: misc.hh:246
gem5::ArmISA::currEL
static ExceptionLevel currEL(const ThreadContext *tc)
Definition: utility.hh:119
gem5::ArmISA::MISCREG_ESR_EL2
@ MISCREG_ESR_EL2
Definition: misc.hh:644
gem5::ArmISA::MISCREG_AT_S1E0W_Xt
@ MISCREG_AT_S1E0W_Xt
Definition: misc.hh:662
gem5::ArmISA::MISCREG_TLBI_VALE2IS_Xt
@ MISCREG_TLBI_VALE2IS_Xt
Definition: misc.hh:695
gem5::ArmISA::MISCREG_HACTLR
@ MISCREG_HACTLR
Definition: misc.hh:247
gem5::X86ISA::val
Bitfield< 63 > val
Definition: misc.hh:775
gem5::ArmISA::MISCREG_OSLSR_EL1
@ MISCREG_OSLSR_EL1
Definition: misc.hh:529
gem5::ArmISA::MISCREG_L2MERRSR
@ MISCREG_L2MERRSR
Definition: misc.hh:450
gem5::ArmISA::MISCREG_PMINTENSET_EL1
@ MISCREG_PMINTENSET_EL1
Definition: misc.hh:710
thread_context.hh
gem5::ArmISA::MISCREG_TLBI_VALE1IS_Xt
@ MISCREG_TLBI_VALE1IS_Xt
Definition: misc.hh:682
gem5::ArmISA::MISCREG_TLBTR
@ MISCREG_TLBTR
Definition: misc.hh:208
gem5::ArmISA::MISCREG_TPIDR_EL3
@ MISCREG_TPIDR_EL3
Definition: misc.hh:751
gem5::ArmISA::MISCREG_CONTEXTIDR_EL1
@ MISCREG_CONTEXTIDR_EL1
Definition: misc.hh:745
gem5::ArmISA::MISCREG_ID_AA64AFR1_EL1
@ MISCREG_ID_AA64AFR1_EL1
Definition: misc.hh:566
gem5::ArmISA::MISCREG_DBGBVR1_EL1
@ MISCREG_DBGBVR1_EL1
Definition: misc.hh:459
gem5::ArmISA::MISCREG_TCR_EL3
@ MISCREG_TCR_EL3
Definition: misc.hh:610
gem5::ArmISA::MISCREG_ID_ISAR2_EL1
@ MISCREG_ID_ISAR2_EL1
Definition: misc.hh:553
gem5::ArmISA::MISCREG_HIFAR
@ MISCREG_HIFAR
Definition: misc.hh:290
gem5::ArmISA::MISCREG_DBGBVR2
@ MISCREG_DBGBVR2
Definition: misc.hh:108
gem5::ArmISA::MISCREG_ID_ISAR3_EL1
@ MISCREG_ID_ISAR3_EL1
Definition: misc.hh:554
gem5::Iris::SecureMonitorMsn
@ SecureMonitorMsn
Definition: memory_spaces.hh:39
gem5::ArmISA::MISCREG_AMAIR_EL3
@ MISCREG_AMAIR_EL3
Definition: misc.hh:733
gem5::ArmISA::MISCREG_TTBR0_NS
@ MISCREG_TTBR0_NS
Definition: misc.hh:255
gem5::ArmISA::MISCREG_ID_ISAR3
@ MISCREG_ID_ISAR3
Definition: misc.hh:223
gem5::ArmISA::MISCREG_ID_AA64MMFR0_EL1
@ MISCREG_ID_AA64MMFR0_EL1
Definition: misc.hh:569
gem5::X86ISA::system
Bitfield< 15 > system
Definition: misc.hh:1003
gem5::ArmISA::MISCREG_ID_ISAR4_EL1
@ MISCREG_ID_ISAR4_EL1
Definition: misc.hh:555
gem5::ArmISA::MISCREG_ID_MMFR3
@ MISCREG_ID_MMFR3
Definition: misc.hh:218
gem5::ArmISA::MISCREG_MAIR_EL3
@ MISCREG_MAIR_EL3
Definition: misc.hh:732
std::vector< iris::MemorySpaceId >
gem5::ArmISA::MISCREG_DBGOSLAR
@ MISCREG_DBGOSLAR
Definition: misc.hh:187
gem5::ArmISA::MISCREG_PMOVSSET
@ MISCREG_PMOVSSET
Definition: misc.hh:366
gem5::ArmISA::MISCREG_MAIR_EL1
@ MISCREG_MAIR_EL1
Definition: misc.hh:726
gem5::ArmISA::MISCREG_PMUSERENR
@ MISCREG_PMUSERENR
Definition: misc.hh:363
gem5::ThreadContext::readIntRegFlat
virtual RegVal readIntRegFlat(RegIndex idx) const =0
Flat register interfaces.
gem5::ArmISA::MISCREG_DCCISW
@ MISCREG_DCCISW
Definition: misc.hh:318
gem5::ArmISA::MISCREG_PRRR_NS
@ MISCREG_PRRR_NS
Definition: misc.hh:370
gem5::ArmISA::MISCREG_TLBI_VALE1_Xt
@ MISCREG_TLBI_VALE1_Xt
Definition: misc.hh:688
gem5::ArmISA::MISCREG_ID_ISAR1
@ MISCREG_ID_ISAR1
Definition: misc.hh:221
gem5::ArmISA::MISCREG_ATS12NSOPW
@ MISCREG_ATS12NSOPW
Definition: misc.hh:309
gem5::ArmISA::MISCREG_PMSWINC_EL0
@ MISCREG_PMSWINC_EL0
Definition: misc.hh:716
gem5::ArmISA::MISCREG_DFSR_NS
@ MISCREG_DFSR_NS
Definition: misc.hh:269
gem5::ArmISA::MISCREG_TLBI_VAE1IS_Xt
@ MISCREG_TLBI_VAE1IS_Xt
Definition: misc.hh:679
gem5::ArmISA::MISCREG_PMCCNTR_EL0
@ MISCREG_PMCCNTR_EL0
Definition: misc.hh:720
gem5::ArmISA::MISCREG_ID_AA64DFR1_EL1
@ MISCREG_ID_AA64DFR1_EL1
Definition: misc.hh:564
gem5::ArmISA::MISCREG_PAR_EL1
@ MISCREG_PAR_EL1
Definition: misc.hh:655
gem5::ArmISA::MISCREG_TLBI_VALE3IS_Xt
@ MISCREG_TLBI_VALE3IS_Xt
Definition: misc.hh:706
gem5::ArmISA::MISCREG_CNTVCT_EL0
@ MISCREG_CNTVCT_EL0
Definition: misc.hh:755
gem5::ArmISA::MISCREG_CNTPCT_EL0
@ MISCREG_CNTPCT_EL0
Definition: misc.hh:754
gem5::ArmISA::MISCREG_TPIDRRO_EL0
@ MISCREG_TPIDRRO_EL0
Definition: misc.hh:749
gem5::ArmISA::MISCREG_CNTP_CTL
@ MISCREG_CNTP_CTL
Definition: misc.hh:416
gem5::ArmISA::MISCREG_TLBI_VMALLS12E1
@ MISCREG_TLBI_VMALLS12E1
Definition: misc.hh:703
gem5::ArmISA::MISCREG_DBGBVR3
@ MISCREG_DBGBVR3
Definition: misc.hh:109
gem5::fastmodel::CortexA76TC::miscRegIdxNameMap
static IdxNameMap miscRegIdxNameMap
Definition: thread_context.hh:45
gem5::ArmISA::MISCREG_ID_MMFR1
@ MISCREG_ID_MMFR1
Definition: misc.hh:216
gem5::ArmISA::MISCREG_OSDLR_EL1
@ MISCREG_OSDLR_EL1
Definition: misc.hh:530
gem5::ArmISA::MISCREG_CPSR_MODE
@ MISCREG_CPSR_MODE
Definition: misc.hh:78
gem5::ArmISA::MISCREG_ID_DFR0_EL1
@ MISCREG_ID_DFR0_EL1
Definition: misc.hh:544
gem5::ArmISA::MISCREG_VTCR_EL2
@ MISCREG_VTCR_EL2
Definition: misc.hh:606
gem5::ArmISA::MISCREG_DBGBXVR4
@ MISCREG_DBGBXVR4
Definition: misc.hh:175
gem5::Iris::HypAppMsn
@ HypAppMsn
Definition: memory_spaces.hh:43
gem5::ArmISA::MISCREG_TLBI_VAE2_Xt
@ MISCREG_TLBI_VAE2_Xt
Definition: misc.hh:700
gem5::Iris::ThreadContext::memorySpaces
std::vector< iris::MemorySpaceInfo > memorySpaces
Definition: thread_context.hh:98
gem5::BaseMMU
Definition: mmu.hh:50
gem5::ArmISA::MISCREG_DBGCLAIMCLR_EL1
@ MISCREG_DBGCLAIMCLR_EL1
Definition: misc.hh:533
gem5::ArmISA::MISCREG_ID_PFR1_EL1
@ MISCREG_ID_PFR1_EL1
Definition: misc.hh:543
gem5::ArmISA::MISCREG_HCPTR
@ MISCREG_HCPTR
Definition: misc.hh:251
gem5::ArmISA::MISCREG_DBGWCR3
@ MISCREG_DBGWCR3
Definition: misc.hh:157
gem5::ArmISA::MISCREG_ID_ISAR0
@ MISCREG_ID_ISAR0
Definition: misc.hh:220
gem5::ArmISA::MISCREG_CNTKCTL_EL1
@ MISCREG_CNTKCTL_EL1
Definition: misc.hh:768
gem5::ArmISA::MISCREG_CPUMERRSR_EL1
@ MISCREG_CPUMERRSR_EL1
Definition: misc.hh:814
gem5::ArmISA::MISCREG_OSECCR_EL1
@ MISCREG_OSECCR_EL1
Definition: misc.hh:457
gem5::ArmISA::MISCREG_MAIR_EL2
@ MISCREG_MAIR_EL2
Definition: misc.hh:730
gem5::ArmISA::MISCREG_ID_MMFR2
@ MISCREG_ID_MMFR2
Definition: misc.hh:217
gem5::ArmISA::MISCREG_DBGBVR0_EL1
@ MISCREG_DBGBVR0_EL1
Definition: misc.hh:458
gem5::Iris::GuestMsn
@ GuestMsn
Definition: memory_spaces.hh:40
gem5::ArmISA::MISCREG_DBGAUTHSTATUS_EL1
@ MISCREG_DBGAUTHSTATUS_EL1
Definition: misc.hh:534
gem5::ArmISA::MISCREG_CNTHP_TVAL_EL2
@ MISCREG_CNTHP_TVAL_EL2
Definition: misc.hh:776
gem5::ArmISA::MISCREG_CNTHCTL_EL2
@ MISCREG_CNTHCTL_EL2
Definition: misc.hh:773
gem5::ArmISA::MISCREG_ID_PFR0_EL1
@ MISCREG_ID_PFR0_EL1
Definition: misc.hh:542
gem5::ArmISA::MISCREG_CPUMERRSR
@ MISCREG_CPUMERRSR
Definition: misc.hh:449
gem5::ArmISA::MISCREG_ERRSELR_EL1
@ MISCREG_ERRSELR_EL1
Definition: misc.hh:1081
gem5::ArmISA::MISCREG_CNTVOFF
@ MISCREG_CNTVOFF
Definition: misc.hh:433
gem5::ArmISA::MISCREG_ELR_EL1
@ MISCREG_ELR_EL1
Definition: misc.hh:614
gem5::ArmISA::MISCREG_DBGCLAIMSET_EL1
@ MISCREG_DBGCLAIMSET_EL1
Definition: misc.hh:532
gem5::ArmISA::MISCREG_DBGBCR1
@ MISCREG_DBGBCR1
Definition: misc.hh:123
gem5::ArmISA::MISCREG_FCSEIDR
@ MISCREG_FCSEIDR
Definition: misc.hh:398
gem5::System
Definition: system.hh:77
gem5::ArmISA::MISCREG_PMEVCNTR1_EL0
@ MISCREG_PMEVCNTR1_EL0
Definition: misc.hh:791
gem5::ArmISA::MISCREG_DBGWCR0
@ MISCREG_DBGWCR0
Definition: misc.hh:154
gem5::ArmISA::MISCREG_DBGBVR5_EL1
@ MISCREG_DBGBVR5_EL1
Definition: misc.hh:463
gem5::ArmISA::MISCREG_HMAIR1
@ MISCREG_HMAIR1
Definition: misc.hh:388
gem5::ArmISA::MISCREG_ATS1CUR
@ MISCREG_ATS1CUR
Definition: misc.hh:306
gem5::ArmISA::MISCREG_ID_AA64PFR1_EL1
@ MISCREG_ID_AA64PFR1_EL1
Definition: misc.hh:562
gem5::ArmISA::MISCREG_ERRIDR_EL1
@ MISCREG_ERRIDR_EL1
Definition: misc.hh:1080
gem5::ThreadContext
ThreadContext is the external interface to all thread state for anything outside of the CPU.
Definition: thread_context.hh:93
gem5::ArmISA::MISCREG_DBGWCR2_EL1
@ MISCREG_DBGWCR2_EL1
Definition: misc.hh:508
gem5::ArmISA::MISCREG_TPIDRURW_NS
@ MISCREG_TPIDRURW_NS
Definition: misc.hh:403
gem5::ArmISA::MISCREG_DBGBCR3
@ MISCREG_DBGBCR3
Definition: misc.hh:125
gem5::ArmISA::MISCREG_SCTLR_EL1
@ MISCREG_SCTLR_EL1
Definition: misc.hh:579
gem5::ArmISA::MISCREG_ID_ISAR2
@ MISCREG_ID_ISAR2
Definition: misc.hh:222
gem5::ArmISA::MISCREG_ID_MMFR2_EL1
@ MISCREG_ID_MMFR2_EL1
Definition: misc.hh:548
gem5::ArmISA::MISCREG_PMCNTENSET
@ MISCREG_PMCNTENSET
Definition: misc.hh:352
gem5::ArmISA::MISCREG_HDCR
@ MISCREG_HDCR
Definition: misc.hh:250
gem5::ArmISA::MISCREG_CPTR_EL3
@ MISCREG_CPTR_EL3
Definition: misc.hh:595
gem5::ArmISA::MISCREG_ID_ISAR4
@ MISCREG_ID_ISAR4
Definition: misc.hh:224
gem5::ArmISA::MISCREG_MDCCINT_EL1
@ MISCREG_MDCCINT_EL1
Definition: misc.hh:453
gem5::ArmISA::MISCREG_DBGAUTHSTATUS
@ MISCREG_DBGAUTHSTATUS
Definition: misc.hh:194
gem5::ArmISA::MISCREG_MVBAR
@ MISCREG_MVBAR
Definition: misc.hh:394
gem5::ArmISA::MISCREG_DBGBVR4_EL1
@ MISCREG_DBGBVR4_EL1
Definition: misc.hh:462
gem5::ArmISA::MISCREG_HACR
@ MISCREG_HACR
Definition: misc.hh:253
gem5::ArmISA::MISCREG_PMOVSSET_EL0
@ MISCREG_PMOVSSET_EL0
Definition: misc.hh:725
gem5::ArmISA::MISCREG_ERXMISC1_EL1
@ MISCREG_ERXMISC1_EL1
Definition: misc.hh:1087
gem5::ArmISA::MISCREG_DBGWVR2_EL1
@ MISCREG_DBGWVR2_EL1
Definition: misc.hh:492
gem5::ArmISA::MISCREG_OSDTRRX_EL1
@ MISCREG_OSDTRRX_EL1
Definition: misc.hh:454
gem5::ArmISA::MISCREG_CPUECTLR_EL1
@ MISCREG_CPUECTLR_EL1
Definition: misc.hh:813
gem5::ArmISA::MISCREG_PMSELR
@ MISCREG_PMSELR
Definition: misc.hh:356
gem5::ArmISA::EL2
@ EL2
Definition: types.hh:268
gem5::ArmISA::MISCREG_REVIDR_EL1
@ MISCREG_REVIDR_EL1
Definition: misc.hh:541
gem5::ArmISA::MISCREG_CNTPCT
@ MISCREG_CNTPCT
Definition: misc.hh:414
gem5::ArmISA::MISCREG_AMAIR_EL2
@ MISCREG_AMAIR_EL2
Definition: misc.hh:731
gem5::ArmISA::MISCREG_SPSR_IRQ
@ MISCREG_SPSR_IRQ
Definition: misc.hh:64
gem5::ArmISA::MISCREG_MIDR_EL1
@ MISCREG_MIDR_EL1
Definition: misc.hh:539
gem5::ArmISA::MISCREG_AT_S1E1W_Xt
@ MISCREG_AT_S1E1W_Xt
Definition: misc.hh:660
gem5::Iris::ThreadContext::miscRegIds
ResourceIds miscRegIds
Definition: thread_context.hh:86
gem5::ArmISA::MISCREG_CNTHP_CVAL_EL2
@ MISCREG_CNTHP_CVAL_EL2
Definition: misc.hh:775
gem5::ArmISA::MISCREG_SCTLR_EL2
@ MISCREG_SCTLR_EL2
Definition: misc.hh:584
gem5::ArmISA::MISCREG_ID_AA64AFR0_EL1
@ MISCREG_ID_AA64AFR0_EL1
Definition: misc.hh:565
gem5::ArmISA::MISCREG_PMEVTYPER2_EL0
@ MISCREG_PMEVTYPER2_EL0
Definition: misc.hh:798
gem5::ArmISA::MISCREG_CCSIDR
@ MISCREG_CCSIDR
Definition: misc.hh:227
gem5::ThreadContext::setIntRegFlat
virtual void setIntRegFlat(RegIndex idx, RegVal val)=0
gem5::ArmISA::MISCREG_MVFR0
@ MISCREG_MVFR0
Definition: misc.hh:74
gem5::ArmISA::MISCREG_HTTBR
@ MISCREG_HTTBR
Definition: misc.hh:447
gem5::ArmISA::MISCREG_SPSR
@ MISCREG_SPSR
Definition: misc.hh:62
gem5::ArmISA::MISCREG_CNTHP_TVAL
@ MISCREG_CNTHP_TVAL
Definition: misc.hh:432
gem5::ArmISA::MISCREG_DBGWVR0_EL1
@ MISCREG_DBGWVR0_EL1
Definition: misc.hh:490
gem5::ArmISA::MISCREG_ICIALLUIS
@ MISCREG_ICIALLUIS
Definition: misc.hh:292
gem5::ArmISA::MISCREG_CNTPS_CVAL_EL1
@ MISCREG_CNTPS_CVAL_EL1
Definition: misc.hh:771
gem5::ArmISA::MISCREG_PMXEVCNTR_EL0
@ MISCREG_PMXEVCNTR_EL0
Definition: misc.hh:723
gem5::ArmISA::MISCREG_VMPIDR
@ MISCREG_VMPIDR
Definition: misc.hh:234
gem5::ArmISA::MISCREG_VSESR_EL2
@ MISCREG_VSESR_EL2
Definition: misc.hh:1089
gem5::Iris::ThreadContext::readCCRegFlat
RegVal readCCRegFlat(RegIndex idx) const override
Definition: thread_context.cc:641
gem5::ArmISA::MISCREG_DBGCLAIMSET
@ MISCREG_DBGCLAIMSET
Definition: misc.hh:192
gem5::ArmISA::MISCREG_HMAIR0
@ MISCREG_HMAIR0
Definition: misc.hh:387
gem5::ArmISA::MISCREG_DBGWCR1_EL1
@ MISCREG_DBGWCR1_EL1
Definition: misc.hh:507
gem5::ArmISA::MISCREG_CPACR_EL1
@ MISCREG_CPACR_EL1
Definition: misc.hh:582
gem5::fastmodel::CortexA76TC::intReg32IdxNameMap
static IdxNameMap intReg32IdxNameMap
Definition: thread_context.hh:46
gem5::ArmISA::MISCREG_ATS1HR
@ MISCREG_ATS1HR
Definition: misc.hh:319
gem5::ArmISA::MISCREG_MVFR1_EL1
@ MISCREG_MVFR1_EL1
Definition: misc.hh:559
gem5::ArmISA::MISCREG_ID_ISAR0_EL1
@ MISCREG_ID_ISAR0_EL1
Definition: misc.hh:551
gem5::ArmISA::MISCREG_PMINTENSET
@ MISCREG_PMINTENSET
Definition: misc.hh:364
gem5::ArmISA::MISCREG_ACTLR_EL2
@ MISCREG_ACTLR_EL2
Definition: misc.hh:585
gem5::ArmISA::MISCREG_DFAR_NS
@ MISCREG_DFAR_NS
Definition: misc.hh:284
gem5::ArmISA::MISCREG_MPIDR_EL1
@ MISCREG_MPIDR_EL1
Definition: misc.hh:540
gem5::ArmISA::MISCREG_TLBI_ASIDE1IS_Xt
@ MISCREG_TLBI_ASIDE1IS_Xt
Definition: misc.hh:680
gem5::ArmISA::MISCREG_SPSR_EL2
@ MISCREG_SPSR_EL2
Definition: misc.hh:625
gem5::ArmISA::MISCREG_ERXCTLR_EL1
@ MISCREG_ERXCTLR_EL1
Definition: misc.hh:1083
gem5::ArmISA::MISCREG_DC_ZVA_Xt
@ MISCREG_DC_ZVA_Xt
Definition: misc.hh:665
gem5::ArmISA::MISCREG_SP_EL1
@ MISCREG_SP_EL1
Definition: misc.hh:627
gem5::ArmISA::MISCREG_AT_S1E0R_Xt
@ MISCREG_AT_S1E0R_Xt
Definition: misc.hh:661
gem5::BaseCPU
Definition: base.hh:107
gem5::ArmISA::MISCREG_DACR_NS
@ MISCREG_DACR_NS
Definition: misc.hh:266
gem5::Iris::ThreadContext::extractResourceMap
void extractResourceMap(ResourceIds &ids, const ResourceMap &resources, const IdxNameMap &idx_names)
Definition: thread_context.cc:104
gem5::Iris::ThreadContext::ccRegIds
ResourceIds ccRegIds
Definition: thread_context.hh:90
gem5::ArmISA::MISCREG_ISR
@ MISCREG_ISR
Definition: misc.hh:396
gem5::ArmISA::MISCREG_ID_ISAR6_EL1
@ MISCREG_ID_ISAR6_EL1
Definition: misc.hh:557
gem5::ArmISA::MISCREG_ID_AFR0
@ MISCREG_ID_AFR0
Definition: misc.hh:214
gem5::ArmISA::MISCREG_MIDR
@ MISCREG_MIDR
Definition: misc.hh:205
gem5::insertBits
constexpr T insertBits(T val, unsigned first, unsigned last, B bit_val)
Returns val with bits first to last set to the LSBs of bit_val.
Definition: bitfield.hh:166
gem5::bits
constexpr T bits(T val, unsigned first, unsigned last)
Extract the bitfield from position 'first' to 'last' (inclusive) from 'val' and right justify it.
Definition: bitfield.hh:76
gem5::ArmISA::MISCREG_DBGBCR4_EL1
@ MISCREG_DBGBCR4_EL1
Definition: misc.hh:478
gem5::ArmISA::MISCREG_IFSR_NS
@ MISCREG_IFSR_NS
Definition: misc.hh:272
gem5::ArmISA::EL3
@ EL3
Definition: types.hh:269
gem5::ArmISA::MISCREG_PMCNTENSET_EL0
@ MISCREG_PMCNTENSET_EL0
Definition: misc.hh:713
gem5::ArmISA::MISCREG_DBGBVR2_EL1
@ MISCREG_DBGBVR2_EL1
Definition: misc.hh:460
gem5::ArmISA::MISCREG_CNTP_CVAL
@ MISCREG_CNTP_CVAL
Definition: misc.hh:419
gem5::ArmISA::MISCREG_CNTHP_CTL_EL2
@ MISCREG_CNTHP_CTL_EL2
Definition: misc.hh:774
gem5::ArmISA::MISCREG_DBGPRCR
@ MISCREG_DBGPRCR
Definition: misc.hh:190
gem5::fastmodel::CortexA76TC::intReg64IdxNameMap
static IdxNameMap intReg64IdxNameMap
Definition: thread_context.hh:47
gem5::ArmISA::MISCREG_ID_PFR1
@ MISCREG_ID_PFR1
Definition: misc.hh:212
gem5::ArmISA::MISCREG_ID_AA64DFR0_EL1
@ MISCREG_ID_AA64DFR0_EL1
Definition: misc.hh:563
gem5::ArmISA::MISCREG_CNTV_CVAL
@ MISCREG_CNTV_CVAL
Definition: misc.hh:426
gem5::Iris::ThreadContext::flattenedIntIds
ResourceIds flattenedIntIds
Definition: thread_context.hh:89
gem5::ArmISA::MISCREG_CNTV_CVAL_EL0
@ MISCREG_CNTV_CVAL_EL0
Definition: misc.hh:760
gem5::ArmISA::MISCREG_HDFAR
@ MISCREG_HDFAR
Definition: misc.hh:289
gem5::ArmISA::MISCREG_ID_AA64MMFR1_EL1
@ MISCREG_ID_AA64MMFR1_EL1
Definition: misc.hh:570
gem5::ArmISA::MISCREG_SPSR_EL1
@ MISCREG_SPSR_EL1
Definition: misc.hh:612
gem5::ArmISA::MISCREG_RVBAR_EL3
@ MISCREG_RVBAR_EL3
Definition: misc.hh:743
gem5::ArmISA::MISCREG_CSSELR_EL1
@ MISCREG_CSSELR_EL1
Definition: misc.hh:574
gem5::ArmISA::MISCREG_TCMTR
@ MISCREG_TCMTR
Definition: misc.hh:207
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::fastmodel::CortexA76TC::readCCRegFlat
RegVal readCCRegFlat(RegIndex idx) const override
Definition: thread_context.cc:148
gem5::ArmISA::MISCREG_PAR_NS
@ MISCREG_PAR_NS
Definition: misc.hh:295
gem5::ArmISA::MISCREG_NMRR_NS
@ MISCREG_NMRR_NS
Definition: misc.hh:376
gem5::GEM5_DEPRECATED_NAMESPACE
GEM5_DEPRECATED_NAMESPACE(GuestABI, guest_abi)
gem5::ArmISA::MISCREG_PMEVCNTR4_EL0
@ MISCREG_PMEVCNTR4_EL0
Definition: misc.hh:794
gem5::ArmISA::MISCREG_CNTHP_CVAL
@ MISCREG_CNTHP_CVAL
Definition: misc.hh:431
gem5::ArmISA::MISCREG_DBGBXVR5
@ MISCREG_DBGBXVR5
Definition: misc.hh:176
gem5::ArmISA::MISCREG_DBGBCR0_EL1
@ MISCREG_DBGBCR0_EL1
Definition: misc.hh:474
gem5::ArmISA::MISCREG_PMCEID1_EL0
@ MISCREG_PMCEID1_EL0
Definition: misc.hh:719
gem5::Iris::ThreadContext::extractResourceId
iris::ResourceId extractResourceId(const ResourceMap &resources, const std::string &name)
Definition: thread_context.cc:97
gem5::ArmISA::MISCREG_CNTP_TVAL_EL0
@ MISCREG_CNTP_TVAL_EL0
Definition: misc.hh:758
gem5::ArmISA::MISCREG_MVFR2_EL1
@ MISCREG_MVFR2_EL1
Definition: misc.hh:560
gem5::ArmISA::MISCREG_AFSR0_EL2
@ MISCREG_AFSR0_EL2
Definition: misc.hh:642
gem5::ArmISA::MISCREG_AT_S12E1R_Xt
@ MISCREG_AT_S12E1R_Xt
Definition: misc.hh:672
gem5::ArmISA::MISCREG_RMR_EL3
@ MISCREG_RMR_EL3
Definition: misc.hh:744
gem5::ArmISA::isSecure
bool isSecure(ThreadContext *tc)
Definition: utility.cc:72
gem5::ArmISA::CCREG_GE
@ CCREG_GE
Definition: cc.hh:52
gem5::ArmISA::MISCREG_HTPIDR
@ MISCREG_HTPIDR
Definition: misc.hh:411
gem5::ArmISA::MISCREG_SP_EL2
@ MISCREG_SP_EL2
Definition: misc.hh:634
gem5::ArmISA::MISCREG_ID_AA64ISAR1_EL1
@ MISCREG_ID_AA64ISAR1_EL1
Definition: misc.hh:568
gem5::ArmISA::MISCREG_AT_S1E2W_Xt
@ MISCREG_AT_S1E2W_Xt
Definition: misc.hh:671
gem5::ArmISA::MISCREG_DBGWCR1
@ MISCREG_DBGWCR1
Definition: misc.hh:155
utility.hh
gem5::ArmISA::MISCREG_TPIDR_EL2
@ MISCREG_TPIDR_EL2
Definition: misc.hh:750
gem5::ArmISA::MISCREG_TLBI_IPAS2LE1_Xt
@ MISCREG_TLBI_IPAS2LE1_Xt
Definition: misc.hh:698
gem5::ArmISA::MISCREG_IC_IALLU
@ MISCREG_IC_IALLU
Definition: misc.hh:656
gem5::ArmISA::MISCREG_DBGBCR5_EL1
@ MISCREG_DBGBCR5_EL1
Definition: misc.hh:479
gem5::Iris::ThreadContext::readMiscRegNoEffect
RegVal readMiscRegNoEffect(RegIndex misc_reg) const override
Definition: thread_context.cc:572
gem5::ArmISA::MISCREG_TLBI_VAALE1IS_Xt
@ MISCREG_TLBI_VAALE1IS_Xt
Definition: misc.hh:683
gem5::ArmISA::MISCREG_ID_AFR0_EL1
@ MISCREG_ID_AFR0_EL1
Definition: misc.hh:545
gem5::ArmISA::MISCREG_SDER
@ MISCREG_SDER
Definition: misc.hh:244
gem5::ArmISA::MISCREG_AFSR0_EL3
@ MISCREG_AFSR0_EL3
Definition: misc.hh:646
gem5::ArmISA::MISCREG_DLR_EL0
@ MISCREG_DLR_EL0
Definition: misc.hh:624
gem5::ArmISA::MISCREG_DBGBCR4
@ MISCREG_DBGBCR4
Definition: misc.hh:126
gem5::ArmISA::MISCREG_DBGWVR3
@ MISCREG_DBGWVR3
Definition: misc.hh:141
gem5::ArmISA::MISCREG_PMINTENCLR
@ MISCREG_PMINTENCLR
Definition: misc.hh:365
gem5::Iris::ThreadContext::setCCRegFlat
void setCCRegFlat(RegIndex idx, RegVal val) override
Definition: thread_context.cc:651
gem5::ArmISA::MISCREG_CNTVOFF_EL2
@ MISCREG_CNTVOFF_EL2
Definition: misc.hh:788
gem5::ArmISA::MISCREG_DBGWCR0_EL1
@ MISCREG_DBGWCR0_EL1
Definition: misc.hh:506
gem5::ArmISA::MISCREG_ATS12NSOPR
@ MISCREG_ATS12NSOPR
Definition: misc.hh:308
gem5::ArmISA::MISCREG_AIDR
@ MISCREG_AIDR
Definition: misc.hh:229
gem5::ArmISA::MISCREG_SPSR_EL3
@ MISCREG_SPSR_EL3
Definition: misc.hh:632
gem5::ArmISA::MISCREG_RMR
@ MISCREG_RMR
Definition: misc.hh:395
gem5::ArmISA::MISCREG_VBAR_NS
@ MISCREG_VBAR_NS
Definition: misc.hh:392
gem5::ArmISA::CCREG_FP
@ CCREG_FP
Definition: cc.hh:53
gem5::ArmISA::MISCREG_AIFSR
@ MISCREG_AIFSR
Definition: misc.hh:277
gem5::ArmISA::MISCREG_FPSCR_QC
@ MISCREG_FPSCR_QC
Definition: misc.hh:81
gem5::ArmISA::MISCREG_DCIMVAC
@ MISCREG_DCIMVAC
Definition: misc.hh:302
gem5::ArmISA::MISCREG_ATS1CPW
@ MISCREG_ATS1CPW
Definition: misc.hh:305
panic_if
#define panic_if(cond,...)
Conditional panic macro that checks the supplied condition and only panics if the condition is true a...
Definition: logging.hh:203
gem5::fastmodel::CortexA76TC::flattenedIntIdxNameMap
static IdxNameMap flattenedIntIdxNameMap
Definition: thread_context.hh:48
gem5::ArmISA::MISCREG_CTR
@ MISCREG_CTR
Definition: misc.hh:206
gem5::fastmodel::CortexA76TC
Definition: thread_context.hh:42
gem5::Iris::ThreadContext::intReg32Ids
ResourceIds intReg32Ids
Definition: thread_context.hh:87
gem5::ArmISA::MISCREG_HCR
@ MISCREG_HCR
Definition: misc.hh:248
gem5::ArmISA::MISCREG_ATS1HW
@ MISCREG_ATS1HW
Definition: misc.hh:320
gem5::ArmISA::MISCREG_ADFSR
@ MISCREG_ADFSR
Definition: misc.hh:274
gem5::ArmISA::MISCREG_PMXEVCNTR
@ MISCREG_PMXEVCNTR
Definition: misc.hh:362
gem5::ArmISA::MISCREG_TTBCR_NS
@ MISCREG_TTBCR_NS
Definition: misc.hh:261
gem5::Iris::ThreadContext::intReg64Ids
ResourceIds intReg64Ids
Definition: thread_context.hh:88
gem5::ArmISA::MISCREG_AFSR1_EL3
@ MISCREG_AFSR1_EL3
Definition: misc.hh:647
gem5::ArmISA::MISCREG_ATS12NSOUW
@ MISCREG_ATS12NSOUW
Definition: misc.hh:311
gem5::ArmISA::MISCREG_CNTHP_CTL
@ MISCREG_CNTHP_CTL
Definition: misc.hh:430
gem5::Iris::ThreadContext::ResourceMap
std::map< std::string, iris::ResourceInfo > ResourceMap
Definition: thread_context.hh:54
gem5::ArmISA::MISCREG_L2MERRSR_EL1
@ MISCREG_L2MERRSR_EL1
Definition: misc.hh:815
gem5::ArmISA::MISCREG_AT_S1E3R_Xt
@ MISCREG_AT_S1E3R_Xt
Definition: misc.hh:676
gem5::ArmISA::MISCREG_CNTP_CVAL_EL0
@ MISCREG_CNTP_CVAL_EL0
Definition: misc.hh:757
gem5::ArmISA::MISCREG_FPSCR
@ MISCREG_FPSCR
Definition: misc.hh:72
gem5::ArmISA::MISCREG_VDISR_EL2
@ MISCREG_VDISR_EL2
Definition: misc.hh:1090
gem5::ArmISA::MISCREG_TLBI_ASIDE1_Xt
@ MISCREG_TLBI_ASIDE1_Xt
Definition: misc.hh:686
gem5::ArmISA::MISCREG_CLIDR
@ MISCREG_CLIDR
Definition: misc.hh:228
gem5::ArmISA::MISCREG_VTTBR_EL2
@ MISCREG_VTTBR_EL2
Definition: misc.hh:605
gem5::ArmISA::MISCREG_DSPSR_EL0
@ MISCREG_DSPSR_EL0
Definition: misc.hh:623
gem5::ArmISA::MISCREG_CNTHV_TVAL_EL2
@ MISCREG_CNTHV_TVAL_EL2
Definition: misc.hh:783
gem5::ArmISA::MISCREG_TLBI_VAALE1_Xt
@ MISCREG_TLBI_VAALE1_Xt
Definition: misc.hh:689
gem5::ArmISA::MISCREG_DBGBCR2
@ MISCREG_DBGBCR2
Definition: misc.hh:124
gem5::fastmodel::CortexA76TC::translateAddress
bool translateAddress(Addr &paddr, Addr vaddr) override
Definition: thread_context.cc:50
gem5::ArmISA::MISCREG_DBGBCR2_EL1
@ MISCREG_DBGBCR2_EL1
Definition: misc.hh:476
gem5::ArmISA::MISCREG_PMEVCNTR3_EL0
@ MISCREG_PMEVCNTR3_EL0
Definition: misc.hh:793
gem5::ArmISA::MISCREG_DBGWVR2
@ MISCREG_DBGWVR2
Definition: misc.hh:140
gem5::Iris::NsHypMsn
@ NsHypMsn
Definition: memory_spaces.hh:41
gem5::ArmISA::MISCREG_SCR
@ MISCREG_SCR
Definition: misc.hh:243
gem5::fastmodel::CortexA76TC::readIntRegFlat
RegVal readIntRegFlat(RegIndex idx) const override
Flat register interfaces.
Definition: thread_context.cc:106
gem5::ArmISA::MISCREG_ID_MMFR1_EL1
@ MISCREG_ID_MMFR1_EL1
Definition: misc.hh:547
gem5::ArmISA::MISCREG_ESR_EL3
@ MISCREG_ESR_EL3
Definition: misc.hh:648
gem5::Iris::ThreadContext::setMiscReg
void setMiscReg(RegIndex misc_reg, const RegVal val) override
Definition: thread_context.hh:360
gem5::ArmISA::MISCREG_ELR_EL2
@ MISCREG_ELR_EL2
Definition: misc.hh:626
gem5::ArmISA::MISCREG_ID_PFR0
@ MISCREG_ID_PFR0
Definition: misc.hh:211
gem5::ArmISA::MISCREG_PMEVTYPER1_EL0
@ MISCREG_PMEVTYPER1_EL0
Definition: misc.hh:797
gem5::ArmISA::MISCREG_DBGDTRTXext
@ MISCREG_DBGDTRTXext
Definition: misc.hh:104
gem5::ArmISA::MISCREG_VMPIDR_EL2
@ MISCREG_VMPIDR_EL2
Definition: misc.hh:578
gem5::ArmISA::MISCREG_PMEVTYPER3_EL0
@ MISCREG_PMEVTYPER3_EL0
Definition: misc.hh:799
gem5::ArmISA::MISCREG_DBGWFAR
@ MISCREG_DBGWFAR
Definition: misc.hh:100
gem5::ArmISA::id
Bitfield< 33 > id
Definition: misc_types.hh:250
gem5::ArmISA::MISCREG_PMEVCNTR0_EL0
@ MISCREG_PMEVCNTR0_EL0
Definition: misc.hh:790
gem5::ArmISA::MISCREG_TLBI_ALLE3
@ MISCREG_TLBI_ALLE3
Definition: misc.hh:707
gem5::ArmISA::MISCREG_REVIDR
@ MISCREG_REVIDR
Definition: misc.hh:210
gem5::ArmISA::MISCREG_SPSR_ABT
@ MISCREG_SPSR_ABT
Definition: misc.hh:67
gem5::ArmISA::MISCREG_OSDTRTX_EL1
@ MISCREG_OSDTRTX_EL1
Definition: misc.hh:456
gem5::ArmISA::MISCREG_ERXMISC0_EL1
@ MISCREG_ERXMISC0_EL1
Definition: misc.hh:1086
gem5::ArmISA::MISCREG_FPSR
@ MISCREG_FPSR
Definition: misc.hh:622
gem5::ArmISA::MISCREG_HVBAR
@ MISCREG_HVBAR
Definition: misc.hh:397
gem5::ArmISA::MISCREG_AFSR0_EL1
@ MISCREG_AFSR0_EL1
Definition: misc.hh:635
gem5::ArmISA::MISCREG_PMXEVTYPER
@ MISCREG_PMXEVTYPER
Definition: misc.hh:360
gem5::ArmISA::MISCREG_HSR
@ MISCREG_HSR
Definition: misc.hh:282
gem5::ArmISA::MISCREG_SEV_MAILBOX
@ MISCREG_SEV_MAILBOX
Definition: misc.hh:92
gem5::Iris::ThreadContext::pcRscId
iris::ResourceId pcRscId
Definition: thread_context.hh:92
gem5::ArmISA::MISCREG_ID_ISAR6
@ MISCREG_ID_ISAR6
Definition: misc.hh:226
gem5::ArmISA::MISCREG_CONTEXTIDR_EL2
@ MISCREG_CONTEXTIDR_EL2
Definition: misc.hh:817
gem5::ArmISA::MISCREG_ELR_EL3
@ MISCREG_ELR_EL3
Definition: misc.hh:633
gem5::ArmISA::MISCREG_CNTHV_CVAL_EL2
@ MISCREG_CNTHV_CVAL_EL2
Definition: misc.hh:782
gem5::ArmISA::MISCREG_IFAR_NS
@ MISCREG_IFAR_NS
Definition: misc.hh:287
gem5::ArmISA::MISCREG_DCZID_EL0
@ MISCREG_DCZID_EL0
Definition: misc.hh:576
gem5::ArmISA::MISCREG_TTBR1_NS
@ MISCREG_TTBR1_NS
Definition: misc.hh:258
gem5::ArmISA::MISCREG_FPCR
@ MISCREG_FPCR
Definition: misc.hh:621
gem5::MipsISA::vaddr
vaddr
Definition: pra_constants.hh:278
gem5::ArmISA::MISCREG_DC_IVAC_Xt
@ MISCREG_DC_IVAC_Xt
Definition: misc.hh:657
gem5::ArmISA::MISCREG_CNTFRQ_EL0
@ MISCREG_CNTFRQ_EL0
Definition: misc.hh:753
gem5::ArmISA::MISCREG_DBGBVR0
@ MISCREG_DBGBVR0
Definition: misc.hh:106
gem5::ArmISA::MISCREG_TPIDR_EL0
@ MISCREG_TPIDR_EL0
Definition: misc.hh:748
gem5::ArmISA::MISCREG_PMCEID0_EL0
@ MISCREG_PMCEID0_EL0
Definition: misc.hh:718
gem5::ArmISA::MISCREG_PMCEID0
@ MISCREG_PMCEID0
Definition: misc.hh:357
gem5::BaseISA
Definition: isa.hh:54
gem5::ArmISA::MISCREG_DC_CVAU_Xt
@ MISCREG_DC_CVAU_Xt
Definition: misc.hh:668
gem5::RegIndex
uint16_t RegIndex
Definition: types.hh:176
gem5::ArmISA::MISCREG_DBGWCR2
@ MISCREG_DBGWCR2
Definition: misc.hh:156
gem5::ArmISA::MISCREG_AT_S12E1W_Xt
@ MISCREG_AT_S12E1W_Xt
Definition: misc.hh:673
gem5::ArmISA::MISCREG_HCR_EL2
@ MISCREG_HCR_EL2
Definition: misc.hh:586
gem5::ArmISA::MISCREG_RAMINDEX
@ MISCREG_RAMINDEX
Definition: misc.hh:444
gem5::ArmISA::MISCREG_AFSR1_EL1
@ MISCREG_AFSR1_EL1
Definition: misc.hh:637
gem5::ArmISA::MISCREG_TLBI_ALLE1IS
@ MISCREG_TLBI_ALLE1IS
Definition: misc.hh:694
gem5::ArmISA::MISCREG_ATS1CPR
@ MISCREG_ATS1CPR
Definition: misc.hh:304
gem5::ArmISA::MISCREG_TTBR0_EL1
@ MISCREG_TTBR0_EL1
Definition: misc.hh:597
gem5::ArmISA::MISCREG_TLBI_VALE3_Xt
@ MISCREG_TLBI_VALE3_Xt
Definition: misc.hh:709
gem5::fastmodel::CortexA76TC::setCCRegFlat
void setCCRegFlat(RegIndex idx, RegVal val) override
Definition: thread_context.cc:165
gem5::ArmISA::MISCREG_TLBI_ALLE2
@ MISCREG_TLBI_ALLE2
Definition: misc.hh:699
gem5::ArmISA::MISCREG_PMEVTYPER4_EL0
@ MISCREG_PMEVTYPER4_EL0
Definition: misc.hh:800
gem5::ArmISA::MISCREG_FAR_EL2
@ MISCREG_FAR_EL2
Definition: misc.hh:651
gem5::ArmISA::MISCREG_DBGBVR4
@ MISCREG_DBGBVR4
Definition: misc.hh:110
gem5::ArmISA::MISCREG_FAR_EL3
@ MISCREG_FAR_EL3
Definition: misc.hh:653
gem5::ArmISA::MISCREG_TLBI_VMALLE1
@ MISCREG_TLBI_VMALLE1
Definition: misc.hh:684
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40
gem5::ArmISA::MISCREG_ID_AA64PFR0_EL1
@ MISCREG_ID_AA64PFR0_EL1
Definition: misc.hh:561
gem5::ArmISA::MISCREG_DBGCLAIMCLR
@ MISCREG_DBGCLAIMCLR
Definition: misc.hh:193
gem5::ArmISA::MISCREG_HPFAR_EL2
@ MISCREG_HPFAR_EL2
Definition: misc.hh:652
gem5::ArmISA::MISCREG_TLBI_VAE1_Xt
@ MISCREG_TLBI_VAE1_Xt
Definition: misc.hh:685
gem5::ArmISA::MISCREG_PMCCNTR
@ MISCREG_PMCCNTR
Definition: misc.hh:359
gem5::ArmISA::MISCREG_CNTV_CTL
@ MISCREG_CNTV_CTL
Definition: misc.hh:425
gem5::ArmISA::MISCREG_ERXFR_EL1
@ MISCREG_ERXFR_EL1
Definition: misc.hh:1082
gem5::ArmISA::MISCREG_PMUSERENR_EL0
@ MISCREG_PMUSERENR_EL0
Definition: misc.hh:724
gem5::ArmISA::MISCREG_ACTLR_EL1
@ MISCREG_ACTLR_EL1
Definition: misc.hh:581
gem5::ArmISA::MISCREG_CCSIDR_EL1
@ MISCREG_CCSIDR_EL1
Definition: misc.hh:571
gem5::ArmISA::MISCREG_CNTHV_CTL_EL2
@ MISCREG_CNTHV_CTL_EL2
Definition: misc.hh:781
gem5::ArmISA::MISCREG_HPFAR
@ MISCREG_HPFAR
Definition: misc.hh:291
gem5::ArmISA::MISCREG_ERXADDR_EL1
@ MISCREG_ERXADDR_EL1
Definition: misc.hh:1085
gem5::ArmISA::MISCREG_ESR_EL1
@ MISCREG_ESR_EL1
Definition: misc.hh:639
gem5::ArmISA::CCREG_V
@ CCREG_V
Definition: cc.hh:51
gem5::ArmISA::MISCREG_TPIDR_EL1
@ MISCREG_TPIDR_EL1
Definition: misc.hh:747
gem5::ArmISA::MISCREG_ID_MMFR0
@ MISCREG_ID_MMFR0
Definition: misc.hh:215
gem5::ArmISA::MISCREG_TLBI_VMALLE1IS
@ MISCREG_TLBI_VMALLE1IS
Definition: misc.hh:678
gem5::ArmISA::MISCREG_VBAR_EL1
@ MISCREG_VBAR_EL1
Definition: misc.hh:736
gem5::ArmISA::MISCREG_TLBI_VAE3IS_Xt
@ MISCREG_TLBI_VAE3IS_Xt
Definition: misc.hh:705
gem5::ArmISA::MISCREG_TLBI_IPAS2E1_Xt
@ MISCREG_TLBI_IPAS2E1_Xt
Definition: misc.hh:697
gem5::ArmISA::MISCREG_PMCNTENCLR_EL0
@ MISCREG_PMCNTENCLR_EL0
Definition: misc.hh:714
gem5::ArmISA::MISCREG_CPACR
@ MISCREG_CPACR
Definition: misc.hh:241
gem5::ArmISA::MISCREG_ID_MMFR4_EL1
@ MISCREG_ID_MMFR4_EL1
Definition: misc.hh:550
gem5::ArmISA::MISCREG_MDSCR_EL1
@ MISCREG_MDSCR_EL1
Definition: misc.hh:455
gem5::ArmISA::MISCREG_PMEVCNTR2_EL0
@ MISCREG_PMEVCNTR2_EL0
Definition: misc.hh:792
gem5::Iris::CanonicalMsn
CanonicalMsn
Definition: memory_spaces.hh:37
gem5::ArmISA::MISCREG_ISR_EL1
@ MISCREG_ISR_EL1
Definition: misc.hh:739
gem5::ArmISA::MISCREG_DC_ISW_Xt
@ MISCREG_DC_ISW_Xt
Definition: misc.hh:658
gem5::ArmISA::MISCREG_ID_AA64ISAR0_EL1
@ MISCREG_ID_AA64ISAR0_EL1
Definition: misc.hh:567
gem5::ArmISA::MISCREG_CLIDR_EL1
@ MISCREG_CLIDR_EL1
Definition: misc.hh:572
gem5::ArmISA::MISCREG_OSLAR_EL1
@ MISCREG_OSLAR_EL1
Definition: misc.hh:528
gem5::ArmISA::MISCREG_AT_S1E1R_Xt
@ MISCREG_AT_S1E1R_Xt
Definition: misc.hh:659
gem5::ArmISA::MISCREG_TTBR1_EL2
@ MISCREG_TTBR1_EL2
Definition: misc.hh:820
gem5::ArmISA::MISCREG_ID_DFR0
@ MISCREG_ID_DFR0
Definition: misc.hh:213
gem5::ArmISA::MISCREG_PMCR_EL0
@ MISCREG_PMCR_EL0
Definition: misc.hh:712
gem5::ArmISA::MISCREG_MVFR0_EL1
@ MISCREG_MVFR0_EL1
Definition: misc.hh:558
gem5::ArmISA::MISCREG_PMEVTYPER0_EL0
@ MISCREG_PMEVTYPER0_EL0
Definition: misc.hh:796
gem5::ArmISA::MISCREG_DBGBVR5
@ MISCREG_DBGBVR5
Definition: misc.hh:111
gem5::ArmISA::MISCREG_DBGBVR1
@ MISCREG_DBGBVR1
Definition: misc.hh:107
gem5::fastmodel::CortexA76TC::setIntRegFlat
void setIntRegFlat(RegIndex idx, RegVal val) override
Definition: thread_context.cc:129
gem5::ArmISA::MISCREG_TLBI_VAE2IS_Xt
@ MISCREG_TLBI_VAE2IS_Xt
Definition: misc.hh:693
gem5::ArmISA::MISCREG_DBGWVR0
@ MISCREG_DBGWVR0
Definition: misc.hh:138
gem5::ArmISA::MISCREG_TCR_EL1
@ MISCREG_TCR_EL1
Definition: misc.hh:601
gem5::ArmISA::MISCREG_DBGBVR3_EL1
@ MISCREG_DBGBVR3_EL1
Definition: misc.hh:461
gem5::ArmISA::MISCREG_TLBI_ALLE2IS
@ MISCREG_TLBI_ALLE2IS
Definition: misc.hh:692
gem5::ArmISA::MISCREG_MDCCSR_EL0
@ MISCREG_MDCCSR_EL0
Definition: misc.hh:522
gem5::ArmISA::MISCREG_TLBI_VAE3_Xt
@ MISCREG_TLBI_VAE3_Xt
Definition: misc.hh:708
gem5::ArmISA::MISCREG_CNTV_TVAL_EL0
@ MISCREG_CNTV_TVAL_EL0
Definition: misc.hh:761
gem5::ArmISA::MISCREG_AT_S1E2R_Xt
@ MISCREG_AT_S1E2R_Xt
Definition: misc.hh:670
gem5::ArmISA::MISCREG_CPSR_Q
@ MISCREG_CPSR_Q
Definition: misc.hh:79
gem5::ArmISA::MISCREG_SPSR_UND
@ MISCREG_SPSR_UND
Definition: misc.hh:69
gem5::ArmISA::MISCREG_ERXSTATUS_EL1
@ MISCREG_ERXSTATUS_EL1
Definition: misc.hh:1084

Generated on Tue Sep 21 2021 12:24:23 for gem5 by doxygen 1.8.17