gem5  v21.2.1.1
faults.cc
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41 
42 #include "arch/arm/faults.hh"
43 
45 #include "arch/arm/interrupts.hh"
46 #include "arch/arm/isa.hh"
47 #include "arch/arm/self_debug.hh"
48 #include "arch/arm/system.hh"
49 #include "arch/arm/utility.hh"
50 #include "base/compiler.hh"
51 #include "base/trace.hh"
52 #include "cpu/base.hh"
53 #include "cpu/thread_context.hh"
54 #include "debug/Faults.hh"
55 #include "sim/full_system.hh"
56 
57 namespace gem5
58 {
59 
60 namespace ArmISA
61 {
62 
63 const uint32_t HighVecs = 0xFFFF0000;
64 
66  0x01, // AlignmentFault
67  0x04, // InstructionCacheMaintenance
68  0xff, // SynchExtAbtOnTranslTableWalkL0 (INVALID)
69  0x0c, // SynchExtAbtOnTranslTableWalkL1
70  0x0e, // SynchExtAbtOnTranslTableWalkL2
71  0xff, // SynchExtAbtOnTranslTableWalkL3 (INVALID)
72  0xff, // SynchPtyErrOnTranslTableWalkL0 (INVALID)
73  0x1c, // SynchPtyErrOnTranslTableWalkL1
74  0x1e, // SynchPtyErrOnTranslTableWalkL2
75  0xff, // SynchPtyErrOnTranslTableWalkL3 (INVALID)
76  0xff, // TranslationL0 (INVALID)
77  0x05, // TranslationL1
78  0x07, // TranslationL2
79  0xff, // TranslationL3 (INVALID)
80  0xff, // AccessFlagL0 (INVALID)
81  0x03, // AccessFlagL1
82  0x06, // AccessFlagL2
83  0xff, // AccessFlagL3 (INVALID)
84  0xff, // DomainL0 (INVALID)
85  0x09, // DomainL1
86  0x0b, // DomainL2
87  0xff, // DomainL3 (INVALID)
88  0xff, // PermissionL0 (INVALID)
89  0x0d, // PermissionL1
90  0x0f, // PermissionL2
91  0xff, // PermissionL3 (INVALID)
92  0x02, // DebugEvent
93  0x08, // SynchronousExternalAbort
94  0x10, // TLBConflictAbort
95  0x19, // SynchPtyErrOnMemoryAccess
96  0x16, // AsynchronousExternalAbort
97  0x18, // AsynchPtyErrOnMemoryAccess
98  0xff, // AddressSizeL0 (INVALID)
99  0xff, // AddressSizeL1 (INVALID)
100  0xff, // AddressSizeL2 (INVALID)
101  0xff, // AddressSizeL3 (INVALID)
102  0x40, // PrefetchTLBMiss
103  0x80 // PrefetchUncacheable
104 };
105 
106 static_assert(sizeof(ArmFault::shortDescFaultSources) ==
108  "Invalid size of ArmFault::shortDescFaultSources[]");
109 
110 uint8_t ArmFault::longDescFaultSources[] = {
111  0x21, // AlignmentFault
112  0xff, // InstructionCacheMaintenance (INVALID)
113  0xff, // SynchExtAbtOnTranslTableWalkL0 (INVALID)
114  0x15, // SynchExtAbtOnTranslTableWalkL1
115  0x16, // SynchExtAbtOnTranslTableWalkL2
116  0x17, // SynchExtAbtOnTranslTableWalkL3
117  0xff, // SynchPtyErrOnTranslTableWalkL0 (INVALID)
118  0x1d, // SynchPtyErrOnTranslTableWalkL1
119  0x1e, // SynchPtyErrOnTranslTableWalkL2
120  0x1f, // SynchPtyErrOnTranslTableWalkL3
121  0xff, // TranslationL0 (INVALID)
122  0x05, // TranslationL1
123  0x06, // TranslationL2
124  0x07, // TranslationL3
125  0xff, // AccessFlagL0 (INVALID)
126  0x09, // AccessFlagL1
127  0x0a, // AccessFlagL2
128  0x0b, // AccessFlagL3
129  0xff, // DomainL0 (INVALID)
130  0x3d, // DomainL1
131  0x3e, // DomainL2
132  0xff, // DomainL3 (RESERVED)
133  0xff, // PermissionL0 (INVALID)
134  0x0d, // PermissionL1
135  0x0e, // PermissionL2
136  0x0f, // PermissionL3
137  0x22, // DebugEvent
138  0x10, // SynchronousExternalAbort
139  0x30, // TLBConflictAbort
140  0x18, // SynchPtyErrOnMemoryAccess
141  0x11, // AsynchronousExternalAbort
142  0x19, // AsynchPtyErrOnMemoryAccess
143  0xff, // AddressSizeL0 (INVALID)
144  0xff, // AddressSizeL1 (INVALID)
145  0xff, // AddressSizeL2 (INVALID)
146  0xff, // AddressSizeL3 (INVALID)
147  0x40, // PrefetchTLBMiss
148  0x80 // PrefetchUncacheable
149 };
150 
151 static_assert(sizeof(ArmFault::longDescFaultSources) ==
153  "Invalid size of ArmFault::longDescFaultSources[]");
154 
155 uint8_t ArmFault::aarch64FaultSources[] = {
156  0x21, // AlignmentFault
157  0xff, // InstructionCacheMaintenance (INVALID)
158  0x14, // SynchExtAbtOnTranslTableWalkL0
159  0x15, // SynchExtAbtOnTranslTableWalkL1
160  0x16, // SynchExtAbtOnTranslTableWalkL2
161  0x17, // SynchExtAbtOnTranslTableWalkL3
162  0x1c, // SynchPtyErrOnTranslTableWalkL0
163  0x1d, // SynchPtyErrOnTranslTableWalkL1
164  0x1e, // SynchPtyErrOnTranslTableWalkL2
165  0x1f, // SynchPtyErrOnTranslTableWalkL3
166  0x04, // TranslationL0
167  0x05, // TranslationL1
168  0x06, // TranslationL2
169  0x07, // TranslationL3
170  0x08, // AccessFlagL0
171  0x09, // AccessFlagL1
172  0x0a, // AccessFlagL2
173  0x0b, // AccessFlagL3
174  // @todo: Section & Page Domain Fault in AArch64?
175  0xff, // DomainL0 (INVALID)
176  0xff, // DomainL1 (INVALID)
177  0xff, // DomainL2 (INVALID)
178  0xff, // DomainL3 (INVALID)
179  0x0c, // PermissionL0
180  0x0d, // PermissionL1
181  0x0e, // PermissionL2
182  0x0f, // PermissionL3
183  0x22, // DebugEvent
184  0x10, // SynchronousExternalAbort
185  0x30, // TLBConflictAbort
186  0x18, // SynchPtyErrOnMemoryAccess
187  0xff, // AsynchronousExternalAbort (INVALID)
188  0xff, // AsynchPtyErrOnMemoryAccess (INVALID)
189  0x00, // AddressSizeL0
190  0x01, // AddressSizeL1
191  0x02, // AddressSizeL2
192  0x03, // AddressSizeL3
193  0x40, // PrefetchTLBMiss
194  0x80 // PrefetchUncacheable
195 };
196 
197 static_assert(sizeof(ArmFault::aarch64FaultSources) ==
199  "Invalid size of ArmFault::aarch64FaultSources[]");
200 
201 // Fields: name, offset, cur{ELT,ELH}Offset, lowerEL{64,32}Offset, next mode,
202 // {ARM, Thumb, ARM_ELR, Thumb_ELR} PC offset, hyp trap,
203 // {A, F} disable, class, stat
205  // Some dummy values (the reset vector has an IMPLEMENTATION DEFINED
206  // location in AArch64)
207  "Reset", 0x000, 0x000, 0x000, 0x000, 0x000, MODE_SVC,
208  0, 0, 0, 0, false, true, true, EC_UNKNOWN
209 );
211  "Undefined Instruction", 0x004, 0x000, 0x200, 0x400, 0x600, MODE_UNDEFINED,
212  4, 2, 0, 0, true, false, false, EC_UNKNOWN
213 );
215  "Supervisor Call", 0x008, 0x000, 0x200, 0x400, 0x600, MODE_SVC,
216  4, 2, 4, 2, true, false, false, EC_SVC_TO_HYP
217 );
219  "Secure Monitor Call", 0x008, 0x000, 0x200, 0x400, 0x600, MODE_MON,
220  4, 4, 4, 4, false, true, true, EC_SMC_TO_HYP
221 );
223  "Hypervisor Call", 0x008, 0x000, 0x200, 0x400, 0x600, MODE_HYP,
224  4, 4, 4, 4, true, false, false, EC_HVC
225 );
227  "Prefetch Abort", 0x00C, 0x000, 0x200, 0x400, 0x600, MODE_ABORT,
228  4, 4, 0, 0, true, true, false, EC_PREFETCH_ABORT_TO_HYP
229 );
231  "Data Abort", 0x010, 0x000, 0x200, 0x400, 0x600, MODE_ABORT,
232  8, 8, 0, 0, true, true, false, EC_DATA_ABORT_TO_HYP
233 );
235  "Virtual Data Abort", 0x010, 0x000, 0x200, 0x400, 0x600, MODE_ABORT,
236  8, 8, 0, 0, true, true, false, EC_INVALID
237 );
239  // @todo: double check these values
240  "Hypervisor Trap", 0x014, 0x000, 0x200, 0x400, 0x600, MODE_HYP,
241  0, 0, 0, 0, false, false, false, EC_UNKNOWN
242 );
244  "Secure Monitor Trap", 0x004, 0x000, 0x200, 0x400, 0x600, MODE_MON,
245  4, 2, 0, 0, false, false, false, EC_UNKNOWN
246 );
248  "IRQ", 0x018, 0x080, 0x280, 0x480, 0x680, MODE_IRQ,
249  4, 4, 0, 0, false, true, false, EC_UNKNOWN
250 );
252  "Virtual IRQ", 0x018, 0x080, 0x280, 0x480, 0x680, MODE_IRQ,
253  4, 4, 0, 0, false, true, false, EC_INVALID
254 );
256  "FIQ", 0x01C, 0x100, 0x300, 0x500, 0x700, MODE_FIQ,
257  4, 4, 0, 0, false, true, true, EC_UNKNOWN
258 );
260  "Virtual FIQ", 0x01C, 0x100, 0x300, 0x500, 0x700, MODE_FIQ,
261  4, 4, 0, 0, false, true, true, EC_INVALID
262 );
264  "Illegal Inst Set State Fault", 0x004, 0x000, 0x200, 0x400, 0x600, MODE_UNDEFINED,
265  4, 2, 0, 0, true, false, false, EC_ILLEGAL_INST
266 );
268  // Some dummy values (SupervisorTrap is AArch64-only)
269  "Supervisor Trap", 0x014, 0x000, 0x200, 0x400, 0x600, MODE_SVC,
270  0, 0, 0, 0, false, false, false, EC_UNKNOWN
271 );
273  // Some dummy values (PCAlignmentFault is AArch64-only)
274  "PC Alignment Fault", 0x000, 0x000, 0x200, 0x400, 0x600, MODE_SVC,
275  0, 0, 0, 0, true, false, false, EC_PC_ALIGNMENT
276 );
278  // Some dummy values (SPAlignmentFault is AArch64-only)
279  "SP Alignment Fault", 0x000, 0x000, 0x200, 0x400, 0x600, MODE_SVC,
280  0, 0, 0, 0, true, false, false, EC_STACK_PTR_ALIGNMENT
281 );
283  // Some dummy values (SError is AArch64-only)
284  "SError", 0x000, 0x180, 0x380, 0x580, 0x780, MODE_SVC,
285  0, 0, 0, 0, false, true, true, EC_SERROR
286 );
288  // Some dummy values (SoftwareBreakpoint is AArch64-only)
289  "Software Breakpoint", 0x000, 0x000, 0x200, 0x400, 0x600, MODE_SVC,
290  0, 0, 0, 0, true, false, false, EC_SOFTWARE_BREAKPOINT
291 );
293  "Hardware Breakpoint", 0x000, 0x000, 0x200, 0x400, 0x600, MODE_SVC,
294  0, 0, 0, 0, true, false, false, EC_HW_BREAKPOINT
295 );
297  "Watchpoint", 0x000, 0x000, 0x200, 0x400, 0x600, MODE_SVC,
298  0, 0, 0, 0, true, false, false, EC_WATCHPOINT
299 );
301  "SoftwareStep", 0x000, 0x000, 0x200, 0x400, 0x600, MODE_SVC,
302  0, 0, 0, 0, true, false, false, EC_SOFTWARE_STEP
303 );
305  // Some dummy values
306  "ArmSev Flush", 0x000, 0x000, 0x000, 0x000, 0x000, MODE_SVC,
307  0, 0, 0, 0, false, true, true, EC_UNKNOWN
308 );
309 
310 Addr
312 {
313  Addr base;
314 
315  // Check for invalid modes
316  CPSR cpsr = tc->readMiscRegNoEffect(MISCREG_CPSR);
317  assert(ArmSystem::haveEL(tc, EL3) || cpsr.mode != MODE_MON);
318  assert(ArmSystem::haveEL(tc, EL2) || cpsr.mode != MODE_HYP);
319 
320  switch (cpsr.mode)
321  {
322  case MODE_MON:
324  break;
325  case MODE_HYP:
327  break;
328  default:
329  SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR);
330  if (sctlr.v) {
331  base = HighVecs;
332  } else {
333  base = ArmSystem::haveEL(tc, EL3) ?
334  tc->readMiscReg(MISCREG_VBAR) : 0;
335  }
336  break;
337  }
338 
339  return base + offset(tc);
340 }
341 
342 Addr
344 {
345  Addr vbar;
346  switch (toEL) {
347  case EL3:
348  assert(ArmSystem::haveEL(tc, EL3));
349  vbar = tc->readMiscReg(MISCREG_VBAR_EL3);
350  break;
351  case EL2:
352  assert(ArmSystem::haveEL(tc, EL2));
353  vbar = tc->readMiscReg(MISCREG_VBAR_EL2);
354  break;
355  case EL1:
356  vbar = tc->readMiscReg(MISCREG_VBAR_EL1);
357  break;
358  default:
359  panic("Invalid target exception level");
360  break;
361  }
362  return vbar + offset64(tc);
363 }
364 
367 {
368  switch (toEL) {
369  case EL1:
370  return MISCREG_ESR_EL1;
371  case EL2:
372  return MISCREG_ESR_EL2;
373  case EL3:
374  return MISCREG_ESR_EL3;
375  default:
376  panic("Invalid exception level");
377  break;
378  }
379 }
380 
383 {
384  switch (toEL) {
385  case EL1:
386  return MISCREG_FAR_EL1;
387  case EL2:
388  return MISCREG_FAR_EL2;
389  case EL3:
390  return MISCREG_FAR_EL3;
391  default:
392  panic("Invalid exception level");
393  break;
394  }
395 }
396 
397 void
399 {
400  uint32_t value;
401  uint32_t exc_class = (uint32_t) ec(tc);
402  uint32_t issVal = iss();
403 
404  assert(!from64 || ArmSystem::highestELIs64(tc));
405 
406  value = exc_class << 26;
407 
408  // HSR.IL not valid for Prefetch Aborts (0x20, 0x21) and Data Aborts (0x24,
409  // 0x25) for which the ISS information is not valid (ARMv7).
410  // @todo: ARMv8 revises AArch32 functionality: when HSR.IL is not
411  // valid it is treated as RES1.
412  if (to64) {
413  value |= 1 << 25;
414  } else if ((bits(exc_class, 5, 3) != 4) ||
415  (bits(exc_class, 2) && bits(issVal, 24))) {
416  if (!machInst.thumb || machInst.bigThumb)
417  value |= 1 << 25;
418  }
419  // Condition code valid for EC[5:4] nonzero
420  if (!from64 && ((bits(exc_class, 5, 4) == 0) &&
421  (bits(exc_class, 3, 0) != 0))) {
422  if (!machInst.thumb) {
423  uint32_t cond;
424  ConditionCode condCode = (ConditionCode) (uint32_t) machInst.condCode;
425  // If its on unconditional instruction report with a cond code of
426  // 0xE, ie the unconditional code
427  cond = (condCode == COND_UC) ? COND_AL : condCode;
428  value |= cond << 20;
429  value |= 1 << 24;
430  }
431  value |= bits(issVal, 19, 0);
432  } else {
433  value |= issVal;
434  }
435  tc->setMiscReg(syndrome_reg, value);
436 }
437 
438 void
440 {
441  CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
442 
443  // Determine source exception level and mode
444  fromMode = (OperatingMode) (uint8_t) cpsr.mode;
446  if (opModeIs64(fromMode))
447  from64 = true;
448 
449  // Determine target exception level (aarch64) or target execution
450  // mode (aarch32).
451  if (ArmSystem::haveEL(tc, EL3) && routeToMonitor(tc)) {
452  toMode = MODE_MON;
453  toEL = EL3;
454  } else if (ArmSystem::haveEL(tc, EL2) && routeToHyp(tc)) {
455  toMode = MODE_HYP;
456  toEL = EL2;
457  hypRouted = true;
458  } else {
459  toMode = nextMode();
461  }
462 
463  if (fromEL > toEL)
464  toEL = fromEL;
465 
466  // Check for Set Priviledge Access Never, if PAN is supported
467  AA64MMFR1 mmfr1 = tc->readMiscReg(MISCREG_ID_AA64MMFR1_EL1);
468  if (mmfr1.pan) {
469  if (toEL == EL1) {
470  const SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR_EL1);
471  span = !sctlr.span;
472  }
473 
474  const HCR hcr = tc->readMiscRegNoEffect(MISCREG_HCR_EL2);
475  if (toEL == EL2 && hcr.e2h && hcr.tge) {
476  const SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR_EL2);
477  span = !sctlr.span;
478  }
479  }
480 
481  to64 = ELIs64(tc, toEL);
482 
483  // The fault specific informations have been updated; it is
484  // now possible to use them inside the fault.
485  faultUpdated = true;
486 }
487 
488 void
490 {
491  // Update fault state informations, like the starting mode (aarch32)
492  // or EL (aarch64) and the ending mode or EL.
493  // From the update function we are also evaluating if the fault must
494  // be handled in AArch64 mode (to64).
495  update(tc);
496 
497  if (from64 != to64) {
498  // Switching modes, sync up versions of the vector register file.
499  if (from64) {
500  syncVecRegsToElems(tc);
501  } else {
502  syncVecElemsToRegs(tc);
503  }
504  }
505 
506  if (to64) {
507  // Invoke exception handler in AArch64 state
508  invoke64(tc, inst);
509  } else {
510  // Invoke exception handler in AArch32 state
511  invoke32(tc, inst);
512  }
513 }
514 
515 void
517 {
518  if (vectorCatch(tc, inst))
519  return;
520 
521  // ARMv7 (ARM ARM issue C B1.9)
522  bool have_security = ArmSystem::haveEL(tc, EL3);
523 
524  FaultBase::invoke(tc);
525  if (!FullSystem)
526  return;
527 
528  SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR);
529  SCR scr = tc->readMiscReg(MISCREG_SCR);
530  CPSR saved_cpsr = tc->readMiscReg(MISCREG_CPSR);
531  saved_cpsr.nz = tc->readCCReg(CCREG_NZ);
532  saved_cpsr.c = tc->readCCReg(CCREG_C);
533  saved_cpsr.v = tc->readCCReg(CCREG_V);
534  saved_cpsr.ge = tc->readCCReg(CCREG_GE);
535 
536  [[maybe_unused]] Addr cur_pc = tc->pcState().as<PCState>().pc();
537  ITSTATE it = tc->pcState().as<PCState>().itstate();
538  saved_cpsr.it2 = it.top6;
539  saved_cpsr.it1 = it.bottom2;
540 
541  // if we have a valid instruction then use it to annotate this fault with
542  // extra information. This is used to generate the correct fault syndrome
543  // information
544  [[maybe_unused]] ArmStaticInst *arm_inst = instrAnnotate(inst);
545 
546  // Ensure Secure state if initially in Monitor mode
547  if (have_security && saved_cpsr.mode == MODE_MON) {
548  SCR scr = tc->readMiscRegNoEffect(MISCREG_SCR);
549  if (scr.ns) {
550  scr.ns = 0;
552  }
553  }
554 
555  CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
556  cpsr.mode = toMode;
557 
558  // some bits are set differently if we have been routed to hyp mode
559  if (cpsr.mode == MODE_HYP) {
560  SCTLR hsctlr = tc->readMiscReg(MISCREG_HSCTLR);
561  cpsr.t = hsctlr.te;
562  cpsr.e = hsctlr.ee;
563  if (!scr.ea) {cpsr.a = 1;}
564  if (!scr.fiq) {cpsr.f = 1;}
565  if (!scr.irq) {cpsr.i = 1;}
566  } else if (cpsr.mode == MODE_MON) {
567  // Special case handling when entering monitor mode
568  cpsr.t = sctlr.te;
569  cpsr.e = sctlr.ee;
570  cpsr.a = 1;
571  cpsr.f = 1;
572  cpsr.i = 1;
573  } else {
574  cpsr.t = sctlr.te;
575  cpsr.e = sctlr.ee;
576 
577  // The *Disable functions are virtual and different per fault
578  cpsr.a = cpsr.a | abortDisable(tc);
579  cpsr.f = cpsr.f | fiqDisable(tc);
580  cpsr.i = 1;
581  }
582  cpsr.it1 = cpsr.it2 = 0;
583  cpsr.j = 0;
584  cpsr.pan = span ? 1 : saved_cpsr.pan;
585  tc->setMiscReg(MISCREG_CPSR, cpsr);
586 
587  // Make sure mailbox sets to one always
589 
590  // Clear the exclusive monitor
592 
593  if (cpsr.mode == MODE_HYP) {
594  tc->setMiscReg(MISCREG_ELR_HYP, cur_pc +
595  (saved_cpsr.t ? thumbPcOffset(true) : armPcOffset(true)));
596  } else {
597  tc->setIntReg(INTREG_LR, cur_pc +
598  (saved_cpsr.t ? thumbPcOffset(false) : armPcOffset(false)));
599  }
600 
601  switch (cpsr.mode) {
602  case MODE_FIQ:
603  tc->setMiscReg(MISCREG_SPSR_FIQ, saved_cpsr);
604  break;
605  case MODE_IRQ:
606  tc->setMiscReg(MISCREG_SPSR_IRQ, saved_cpsr);
607  break;
608  case MODE_SVC:
609  tc->setMiscReg(MISCREG_SPSR_SVC, saved_cpsr);
610  break;
611  case MODE_MON:
612  assert(have_security);
613  tc->setMiscReg(MISCREG_SPSR_MON, saved_cpsr);
614  break;
615  case MODE_ABORT:
616  tc->setMiscReg(MISCREG_SPSR_ABT, saved_cpsr);
617  break;
618  case MODE_UNDEFINED:
619  tc->setMiscReg(MISCREG_SPSR_UND, saved_cpsr);
620  if (ec(tc) != EC_UNKNOWN)
622  break;
623  case MODE_HYP:
624  assert(ArmSystem::haveEL(tc, EL2));
625  tc->setMiscReg(MISCREG_SPSR_HYP, saved_cpsr);
627  break;
628  default:
629  panic("unknown Mode\n");
630  }
631 
632  Addr new_pc = getVector(tc);
633  DPRINTF(Faults, "Invoking Fault:%s cpsr:%#x PC:%#x lr:%#x newVec: %#x "
634  "%s\n", name(), cpsr, cur_pc, tc->readIntReg(INTREG_LR),
635  new_pc, arm_inst ? csprintf("inst: %#x", arm_inst->encoding()) :
636  std::string());
637  PCState pc(new_pc);
638  pc.thumb(cpsr.t);
639  pc.nextThumb(pc.thumb());
640  pc.jazelle(cpsr.j);
641  pc.nextJazelle(pc.jazelle());
642  pc.aarch64(!cpsr.width);
643  pc.nextAArch64(!cpsr.width);
644  pc.illegalExec(false);
645  tc->pcState(pc);
646 }
647 
648 void
650 {
651  // Determine actual misc. register indices for ELR_ELx and SPSR_ELx
652  MiscRegIndex elr_idx, spsr_idx;
653  switch (toEL) {
654  case EL1:
655  elr_idx = MISCREG_ELR_EL1;
656  spsr_idx = MISCREG_SPSR_EL1;
657  break;
658  case EL2:
659  assert(ArmSystem::haveEL(tc, EL2));
660  elr_idx = MISCREG_ELR_EL2;
661  spsr_idx = MISCREG_SPSR_EL2;
662  break;
663  case EL3:
664  assert(ArmSystem::haveEL(tc, EL3));
665  elr_idx = MISCREG_ELR_EL3;
666  spsr_idx = MISCREG_SPSR_EL3;
667  break;
668  default:
669  panic("Invalid target exception level");
670  break;
671  }
672 
673  // Save process state into SPSR_ELx
674  CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
675  CPSR spsr = cpsr;
676  spsr.nz = tc->readCCReg(CCREG_NZ);
677  spsr.c = tc->readCCReg(CCREG_C);
678  spsr.v = tc->readCCReg(CCREG_V);
679  spsr.ss = isResetSPSR() ? 0: cpsr.ss;
680  if (from64) {
681  // Force some bitfields to 0
682  spsr.q = 0;
683  spsr.it1 = 0;
684  spsr.j = 0;
685  spsr.ge = 0;
686  spsr.it2 = 0;
687  spsr.t = 0;
688  } else {
689  spsr.ge = tc->readCCReg(CCREG_GE);
690  ITSTATE it = tc->pcState().as<PCState>().itstate();
691  spsr.it2 = it.top6;
692  spsr.it1 = it.bottom2;
693  spsr.uao = 0;
694  }
695  tc->setMiscReg(spsr_idx, spsr);
696 
697  // Save preferred return address into ELR_ELx
698  Addr curr_pc = tc->pcState().instAddr();
699  Addr ret_addr = curr_pc;
700  if (from64)
701  ret_addr += armPcElrOffset();
702  else
703  ret_addr += spsr.t ? thumbPcElrOffset() : armPcElrOffset();
704  tc->setMiscReg(elr_idx, ret_addr);
705 
706  Addr vec_address = getVector64(tc);
707 
708  // Update process state
709  OperatingMode64 mode = 0;
710  mode.spX = 1;
711  mode.el = toEL;
712  mode.width = 0;
713  cpsr.mode = mode;
714  cpsr.daif = 0xf;
715  cpsr.il = 0;
716  cpsr.ss = 0;
717  cpsr.pan = span ? 1 : spsr.pan;
718  cpsr.uao = 0;
719  tc->setMiscReg(MISCREG_CPSR, cpsr);
720 
721  // If we have a valid instruction then use it to annotate this fault with
722  // extra information. This is used to generate the correct fault syndrome
723  // information
724  [[maybe_unused]] ArmStaticInst *arm_inst = instrAnnotate(inst);
725 
726  // Set PC to start of exception handler
727  Addr new_pc = purifyTaggedAddr(vec_address, tc, toEL, true);
728  DPRINTF(Faults, "Invoking Fault (AArch64 target EL):%s cpsr:%#x PC:%#x "
729  "elr:%#x newVec: %#x %s\n", name(), cpsr, curr_pc, ret_addr,
730  new_pc, arm_inst ? csprintf("inst: %#x", arm_inst->encoding()) :
731  std::string());
732  PCState pc(new_pc);
733  pc.aarch64(!cpsr.width);
734  pc.nextAArch64(!cpsr.width);
735  pc.illegalExec(false);
736  pc.stepped(false);
737  tc->pcState(pc);
738 
739  // Save exception syndrome
740  if ((nextMode() != MODE_IRQ) && (nextMode() != MODE_FIQ))
742 }
743 
744 bool
746 {
748  VectorCatch* vc = sd->getVectorCatch(tc);
749  if (!vc->isVCMatch()) {
750  Fault fault = sd->testVectorCatch(tc, 0x0, this);
751  if (fault != NoFault)
752  fault->invoke(tc, inst);
753  return true;
754  }
755  return false;
756 }
757 
760 {
761  if (inst) {
762  auto arm_inst = static_cast<ArmStaticInst *>(inst.get());
763  arm_inst->annotateFault(this);
764  return arm_inst;
765  } else {
766  return nullptr;
767  }
768 }
769 
770 Addr
772 {
773  Addr base;
774 
775  // Check for invalid modes
776  [[maybe_unused]] CPSR cpsr = tc->readMiscRegNoEffect(MISCREG_CPSR);
777  assert(ArmSystem::haveEL(tc, EL3) || cpsr.mode != MODE_MON);
778  assert(ArmSystem::haveEL(tc, EL2) || cpsr.mode != MODE_HYP);
779 
780  // RVBAR is aliased (implemented as) MVBAR in gem5, since the two
781  // are mutually exclusive; there is no need to check here for
782  // which register to use since they hold the same value
784 
785  return base + offset(tc);
786 }
787 
788 void
790 {
791  if (FullSystem) {
792  tc->getCpuPtr()->clearInterrupts(tc->threadId());
793  tc->clearArchRegs();
794  }
795  if (!ArmSystem::highestELIs64(tc)) {
796  ArmFault::invoke(tc, inst);
798  getMPIDR(dynamic_cast<ArmSystem*>(tc->getSystemPtr()), tc));
799 
800  // Unless we have SMC code to get us there, boot in HYP!
801  if (ArmSystem::haveEL(tc, EL2) &&
802  !ArmSystem::haveEL(tc, EL3)) {
803  CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
804  cpsr.mode = MODE_HYP;
805  tc->setMiscReg(MISCREG_CPSR, cpsr);
806  }
807  } else {
808  // Advance the PC to the IMPLEMENTATION DEFINED reset value
810  pc.aarch64(true);
811  pc.nextAArch64(true);
812  tc->pcState(pc);
813  }
814 }
815 
816 void
818 {
819  if (FullSystem) {
820  ArmFault::invoke(tc, inst);
821  return;
822  }
823 
824  // If the mnemonic isn't defined this has to be an unknown instruction.
825  assert(unknown || mnemonic != NULL);
826  auto arm_inst = static_cast<ArmStaticInst *>(inst.get());
827  if (disabled) {
828  panic("Attempted to execute disabled instruction "
829  "'%s' (inst 0x%08x)", mnemonic, arm_inst->encoding());
830  } else if (unknown) {
831  panic("Attempted to execute unknown instruction (inst 0x%08x)",
832  arm_inst->encoding());
833  } else {
834  panic("Attempted to execute unimplemented instruction "
835  "'%s' (inst 0x%08x)", mnemonic, arm_inst->encoding());
836  }
837 }
838 
839 bool
841 {
842  HCR hcr = tc->readMiscRegNoEffect(MISCREG_HCR);
843  return fromEL == EL2 ||
844  (EL2Enabled(tc) && (fromEL == EL0) && hcr.tge);
845 }
846 
847 uint32_t
849 {
850 
851  // If UndefinedInstruction is routed to hypervisor, iss field is 0.
852  if (hypRouted) {
853  return 0;
854  }
855 
856  if (overrideEc == EC_INVALID)
857  return issRaw;
858 
859  uint32_t new_iss = 0;
860  uint32_t op0, op1, op2, CRn, CRm, Rt, dir;
861 
862  dir = bits(machInst, 21, 21);
863  op0 = bits(machInst, 20, 19);
864  op1 = bits(machInst, 18, 16);
865  CRn = bits(machInst, 15, 12);
866  CRm = bits(machInst, 11, 8);
867  op2 = bits(machInst, 7, 5);
868  Rt = bits(machInst, 4, 0);
869 
870  new_iss = op0 << 20 | op2 << 17 | op1 << 14 | CRn << 10 |
871  Rt << 5 | CRm << 1 | dir;
872 
873  return new_iss;
874 }
875 
876 void
878 {
879  if (FullSystem) {
880  ArmFault::invoke(tc, inst);
881  return;
882  }
883 
884  // Advance the PC since that won't happen automatically.
885  PCState pc = tc->pcState().as<PCState>();
886  assert(inst);
887  inst->advancePC(pc);
888  tc->pcState(pc);
889 
890  // As of now, there isn't a 32 bit thumb version of this instruction.
891  assert(!machInst.bigThumb);
892  tc->getSystemPtr()->workload->syscall(tc);
893 }
894 
895 bool
897 {
898  HCR hcr = tc->readMiscRegNoEffect(MISCREG_HCR);
899  return fromEL == EL2 ||
900  (EL2Enabled(tc) && fromEL == EL0 && hcr.tge);
901 }
902 
905 {
906  return (overrideEc != EC_INVALID) ? overrideEc :
907  (from64 ? EC_SVC_64 : vals.ec);
908 }
909 
910 uint32_t
912 {
913  // Even if we have a 24 bit imm from an arm32 instruction then we only use
914  // the bottom 16 bits for the ISS value (it doesn't hurt for AArch64 SVC).
915  return issRaw & 0xFFFF;
916 }
917 
918 uint32_t
920 {
921  if (from64)
922  return bits(machInst, 20, 5);
923  return 0;
924 }
925 
928 {
929  // If UndefinedInstruction is routed to hypervisor,
930  // HSR.EC field is 0.
931  if (hypRouted)
932  return EC_UNKNOWN;
933  else
934  return (overrideEc != EC_INVALID) ? overrideEc : vals.ec;
935 }
936 
937 
938 HypervisorCall::HypervisorCall(ExtMachInst _machInst, uint32_t _imm) :
939  ArmFaultVals<HypervisorCall>(_machInst, _imm)
940 {
941  bStep = true;
942 }
943 
944 bool
946 {
947  return from64 && fromEL == EL3;
948 }
949 
950 bool
952 {
953  return !from64 || fromEL != EL3;
954 }
955 
958 {
959  return from64 ? EC_HVC_64 : vals.ec;
960 }
961 
964 {
965  return (overrideEc != EC_INVALID) ? overrideEc : vals.ec;
966 }
967 
968 template<class T>
971 {
972  bool isHypTrap = false;
973 
974  // Normally we just use the exception vector from the table at the top if
975  // this file, however if this exception has caused a transition to hype
976  // mode, and its an exception type that would only do this if it has been
977  // trapped then we use the hyp trap vector instead of the normal vector
978  if (vals.hypTrappable) {
979  CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
980  if (cpsr.mode == MODE_HYP) {
981  CPSR spsr = tc->readMiscReg(MISCREG_SPSR_HYP);
982  isHypTrap = spsr.mode != MODE_HYP;
983  }
984  }
985  return isHypTrap ? 0x14 : vals.offset;
986 }
987 
988 template<class T>
991 {
992  if (toEL == fromEL) {
993  if (opModeIsT(fromMode))
994  return vals.currELTOffset;
995  return vals.currELHOffset;
996  } else {
997  bool lower_32 = false;
998  if (toEL == EL3) {
999  if (EL2Enabled(tc))
1000  lower_32 = ELIs32(tc, EL2);
1001  else
1002  lower_32 = ELIs32(tc, EL1);
1003  } else if (ELIsInHost(tc, fromEL) && fromEL == EL0 && toEL == EL2) {
1004  lower_32 = ELIs32(tc, EL0);
1005  } else {
1006  lower_32 = ELIs32(tc, static_cast<ExceptionLevel>(toEL - 1));
1007  }
1008 
1009  if (lower_32)
1010  return vals.lowerEL32Offset;
1011  return vals.lowerEL64Offset;
1012  }
1013 }
1014 
1015 // void
1016 // SupervisorCall::setSyndrome64(ThreadContext *tc, MiscRegIndex esr_idx)
1017 // {
1018 // ESR esr = 0;
1019 // esr.ec = machInst.aarch64 ? SvcAArch64 : SvcAArch32;
1020 // esr.il = !machInst.thumb;
1021 // if (machInst.aarch64)
1022 // esr.imm16 = bits(machInst.instBits, 20, 5);
1023 // else if (machInst.thumb)
1024 // esr.imm16 = bits(machInst.instBits, 7, 0);
1025 // else
1026 // esr.imm16 = bits(machInst.instBits, 15, 0);
1027 // tc->setMiscReg(esr_idx, esr);
1028 // }
1029 
1030 void
1032 {
1033  if (FullSystem) {
1034  ArmFault::invoke(tc, inst);
1035  return;
1036  }
1037 }
1038 
1041 {
1042  return (from64 ? EC_SMC_64 : vals.ec);
1043 }
1044 
1045 bool
1047 {
1048  HCR hcr = tc->readMiscRegNoEffect(MISCREG_HCR_EL2);
1049  return EL2Enabled(tc) && currEL(tc) <= EL1 && hcr.tge;
1050 }
1051 
1052 uint32_t
1054 {
1055  // If SupervisorTrap is routed to hypervisor, iss field is 0.
1056  if (hypRouted) {
1057  return 0;
1058  }
1059  return issRaw;
1060 }
1061 
1064 {
1065  if (hypRouted)
1066  return EC_UNKNOWN;
1067  else
1068  return (overrideEc != EC_INVALID) ? overrideEc : vals.ec;
1069 }
1070 
1073 {
1074  return (overrideEc != EC_INVALID) ? overrideEc :
1075  (from64 ? EC_SMC_64 : vals.ec);
1076 }
1077 
1078 template<class T>
1079 void
1081 {
1082  if (tranMethod == ArmFault::UnknownTran) {
1083  tranMethod = longDescFormatInUse(tc) ? ArmFault::LpaeTran
1085 
1086  if ((tranMethod == ArmFault::VmsaTran) && this->routeToMonitor(tc)) {
1087  // See ARM ARM B3-1416
1088  bool override_LPAE = false;
1089  TTBCR ttbcr_s = tc->readMiscReg(MISCREG_TTBCR_S);
1090  [[maybe_unused]] TTBCR ttbcr_ns =
1092  if (ttbcr_s.eae) {
1093  override_LPAE = true;
1094  } else {
1095  // Unimplemented code option, not seen in testing. May need
1096  // extension according to the manual exceprt above.
1097  DPRINTF(Faults, "Warning: Incomplete translation method "
1098  "override detected.\n");
1099  }
1100  if (override_LPAE)
1101  tranMethod = ArmFault::LpaeTran;
1102  }
1103  }
1104 
1105  if (source == ArmFault::AsynchronousExternalAbort) {
1106  tc->getCpuPtr()->clearInterrupt(tc->threadId(), INT_ABT, 0);
1107  }
1108  // Get effective fault source encoding
1109  CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
1110 
1111  // source must be determined BEFORE invoking generic routines which will
1112  // try to set hsr etc. and are based upon source!
1113  ArmFaultVals<T>::invoke(tc, inst);
1114 
1115  if (!this->to64) { // AArch32
1116  FSR fsr = getFsr(tc);
1117  if (cpsr.mode == MODE_HYP) {
1118  tc->setMiscReg(T::HFarIndex, faultAddr);
1119  } else if (stage2) {
1120  tc->setMiscReg(MISCREG_HPFAR, (faultAddr >> 8) & ~0xf);
1121  tc->setMiscReg(T::HFarIndex, OVAddr);
1122  } else if (debugType > ArmFault::NODEBUG) {
1123  DBGDS32 Rext = tc->readMiscReg(MISCREG_DBGDSCRext);
1124  tc->setMiscReg(T::FarIndex, faultAddr);
1125  if (debugType == ArmFault::BRKPOINT){
1126  Rext.moe = 0x1;
1127  } else if (debugType == ArmFault::VECTORCATCH){
1128  Rext.moe = 0x5;
1129  } else if (debugType > ArmFault::VECTORCATCH) {
1130  Rext.moe = 0xa;
1131  fsr.cm = (debugType == ArmFault::WPOINT_CM)? 1 : 0;
1132  }
1133 
1134  tc->setMiscReg(T::FsrIndex, fsr);
1135  tc->setMiscReg(MISCREG_DBGDSCRext, Rext);
1136 
1137  } else {
1138  tc->setMiscReg(T::FsrIndex, fsr);
1139  tc->setMiscReg(T::FarIndex, faultAddr);
1140  }
1141  DPRINTF(Faults, "Abort Fault source=%#x fsr=%#x faultAddr=%#x "\
1142  "tranMethod=%#x\n", source, fsr, faultAddr, tranMethod);
1143  } else { // AArch64
1144  // Set the FAR register. Nothing else to do if we are in AArch64 state
1145  // because the syndrome register has already been set inside invoke64()
1146  if (stage2) {
1147  // stage 2 fault, set HPFAR_EL2 to the faulting IPA
1148  // and FAR_EL2 to the Original VA
1150  tc->setMiscReg(MISCREG_HPFAR_EL2, bits(faultAddr, 47, 12) << 4);
1151 
1152  DPRINTF(Faults, "Abort Fault (Stage 2) VA: 0x%x IPA: 0x%x\n",
1153  OVAddr, faultAddr);
1154  } else {
1155  tc->setMiscReg(AbortFault<T>::getFaultAddrReg64(), faultAddr);
1156  }
1157  }
1158 }
1159 
1160 template<class T>
1161 void
1163 {
1164  srcEncoded = getFaultStatusCode(tc);
1165  if (srcEncoded == ArmFault::FaultSourceInvalid) {
1166  panic("Invalid fault source\n");
1167  }
1168  ArmFault::setSyndrome(tc, syndrome_reg);
1169 }
1170 
1171 template<class T>
1172 uint8_t
1174 {
1175 
1176  panic_if(!this->faultUpdated,
1177  "Trying to use un-updated ArmFault internal variables\n");
1178 
1179  uint8_t fsc = 0;
1180 
1181  if (!this->to64) {
1182  // AArch32
1183  assert(tranMethod != ArmFault::UnknownTran);
1184  if (tranMethod == ArmFault::LpaeTran) {
1185  fsc = ArmFault::longDescFaultSources[source];
1186  } else {
1187  fsc = ArmFault::shortDescFaultSources[source];
1188  }
1189  } else {
1190  // AArch64
1191  fsc = ArmFault::aarch64FaultSources[source];
1192  }
1193 
1194  return fsc;
1195 }
1196 
1197 template<class T>
1198 FSR
1200 {
1201  FSR fsr = 0;
1202 
1203  auto fsc = getFaultStatusCode(tc);
1204 
1205  // AArch32
1206  assert(tranMethod != ArmFault::UnknownTran);
1207  if (tranMethod == ArmFault::LpaeTran) {
1208  fsr.status = fsc;
1209  fsr.lpae = 1;
1210  } else {
1211  fsr.fsLow = bits(fsc, 3, 0);
1212  fsr.fsHigh = bits(fsc, 4);
1213  fsr.domain = static_cast<uint8_t>(domain);
1214  }
1215 
1216  fsr.wnr = (write ? 1 : 0);
1217  fsr.ext = 0;
1218 
1219  return fsr;
1220 }
1221 
1222 template<class T>
1223 bool
1225 {
1226  if (ArmSystem::haveEL(tc, EL3)) {
1227  SCR scr = tc->readMiscRegNoEffect(MISCREG_SCR);
1228  return (!scr.ns || scr.aw);
1229  }
1230  return true;
1231 }
1232 
1233 template<class T>
1234 void
1236 {
1237  switch (id)
1238  {
1239  case ArmFault::S1PTW:
1240  s1ptw = val;
1241  break;
1242  case ArmFault::OVA:
1243  OVAddr = val;
1244  break;
1245 
1246  // Just ignore unknown ID's
1247  default:
1248  break;
1249  }
1250 }
1251 
1252 template<class T>
1253 uint32_t
1255 {
1256  uint32_t val;
1257 
1258  val = srcEncoded & 0x3F;
1259  val |= write << 6;
1260  val |= s1ptw << 7;
1261  return (val);
1262 }
1263 
1264 template<class T>
1265 bool
1267 {
1268  // NOTE: Not relying on LL information being aligned to lowest bits here
1269  return
1270  (source == ArmFault::AlignmentFault) ||
1271  ((source >= ArmFault::TranslationLL) &&
1272  (source < ArmFault::TranslationLL + 4)) ||
1273  ((source >= ArmFault::AccessFlagLL) &&
1274  (source < ArmFault::AccessFlagLL + 4)) ||
1275  ((source >= ArmFault::DomainLL) &&
1276  (source < ArmFault::DomainLL + 4)) ||
1277  ((source >= ArmFault::PermissionLL) &&
1278  (source < ArmFault::PermissionLL + 4));
1279 }
1280 
1281 template<class T>
1282 bool
1284 {
1285  va = (stage2 ? OVAddr : faultAddr);
1286  return true;
1287 }
1288 
1291 {
1292  if (to64) {
1293  // AArch64
1294  if (toEL == fromEL)
1296  else
1298  } else {
1299  // AArch32
1300  // Abort faults have different EC codes depending on whether
1301  // the fault originated within HYP mode, or not. So override
1302  // the method and add the extra adjustment of the EC value.
1303 
1305 
1306  CPSR spsr = tc->readMiscReg(MISCREG_SPSR_HYP);
1307  if (spsr.mode == MODE_HYP) {
1308  ec = ((ExceptionClass) (((uint32_t) ec) + 1));
1309  }
1310  return ec;
1311  }
1312 }
1313 
1314 bool
1316 {
1317  SCR scr = 0;
1318  if (from64)
1320  else
1321  scr = tc->readMiscRegNoEffect(MISCREG_SCR);
1322 
1323  return scr.ea && !isMMUFault();
1324 }
1325 
1326 bool
1328 {
1329  bool toHyp;
1330 
1331  HCR hcr = tc->readMiscRegNoEffect(MISCREG_HCR);
1332  HDCR hdcr = tc->readMiscRegNoEffect(MISCREG_HDCR);
1333 
1334  toHyp = fromEL == EL2;
1335  toHyp |= ArmSystem::haveEL(tc, EL2) && !isSecure(tc) &&
1336  currEL(tc) <= EL1 && (hcr.tge || stage2 ||
1337  (source == DebugEvent && hdcr.tde));
1338  return toHyp;
1339 }
1340 
1343 {
1344  if (to64) {
1345  // AArch64
1347  panic("Asynchronous External Abort should be handled with "
1348  "SystemErrors (SErrors)!");
1349  }
1350  if (toEL == fromEL)
1351  return EC_DATA_ABORT_CURR_EL;
1352  else
1353  return EC_DATA_ABORT_LOWER_EL;
1354  } else {
1355  // AArch32
1356  // Abort faults have different EC codes depending on whether
1357  // the fault originated within HYP mode, or not. So override
1358  // the method and add the extra adjustment of the EC value.
1359 
1361 
1362  CPSR spsr = tc->readMiscReg(MISCREG_SPSR_HYP);
1363  if (spsr.mode == MODE_HYP) {
1364  ec = ((ExceptionClass) (((uint32_t) ec) + 1));
1365  }
1366  return ec;
1367  }
1368 }
1369 
1370 bool
1372 {
1373  SCR scr = 0;
1374  if (from64)
1376  else
1377  scr = tc->readMiscRegNoEffect(MISCREG_SCR);
1378 
1379  return scr.ea && !isMMUFault();
1380 }
1381 
1382 bool
1384 {
1385  bool toHyp;
1386 
1387  HCR hcr = tc->readMiscRegNoEffect(MISCREG_HCR);
1388  HDCR hdcr = tc->readMiscRegNoEffect(MISCREG_HDCR);
1389 
1390  bool amo = hcr.amo;
1391  if (hcr.tge == 1)
1392  amo = (!HaveVirtHostExt(tc) || hcr.e2h == 0);
1393 
1394  // if in Hyp mode then stay in Hyp mode
1395  toHyp = fromEL == EL2 ||
1396  (EL2Enabled(tc) && fromEL <= EL1
1397  && (hcr.tge || stage2 ||
1398  ((source == AsynchronousExternalAbort) && amo) ||
1399  ((fromEL == EL0) && hcr.tge &&
1400  ((source == AlignmentFault) ||
1402  ((source == DebugEvent) && (hdcr.tde || hcr.tge))));
1403  return toHyp;
1404 }
1405 
1406 uint32_t
1408 {
1409  uint32_t val;
1410 
1411  // Add on the data abort specific fields to the generic abort ISS value
1413 
1414  val |= cm << 8;
1415 
1416  // ISS is valid if not caused by a stage 1 page table walk, and when taken
1417  // to AArch64 only when directed to EL2
1418  if (!s1ptw && stage2 && (!to64 || toEL == EL2)) {
1419  val |= isv << 24;
1420  if (isv) {
1421  val |= sas << 22;
1422  val |= sse << 21;
1423  val |= srt << 16;
1424  // AArch64 only. These assignments are safe on AArch32 as well
1425  // because these vars are initialized to false
1426  val |= sf << 15;
1427  val |= ar << 14;
1428  }
1429  }
1430  return (val);
1431 }
1432 
1433 void
1435 {
1437  switch (id)
1438  {
1439  case SAS:
1440  isv = true;
1441  sas = val;
1442  break;
1443  case SSE:
1444  isv = true;
1445  sse = val;
1446  break;
1447  case SRT:
1448  isv = true;
1449  srt = val;
1450  break;
1451  case SF:
1452  isv = true;
1453  sf = val;
1454  break;
1455  case AR:
1456  isv = true;
1457  ar = val;
1458  break;
1459  case CM:
1460  cm = val;
1461  break;
1462  case OFA:
1463  faultAddr = val;
1464  break;
1465  // Just ignore unknown ID's
1466  default:
1467  break;
1468  }
1469 }
1470 
1471 void
1473 {
1475  HCR hcr = tc->readMiscRegNoEffect(MISCREG_HCR);
1476  hcr.va = 0;
1477  tc->setMiscRegNoEffect(MISCREG_HCR, hcr);
1478 }
1479 
1480 bool
1482 {
1483  assert(ArmSystem::haveEL(tc, EL3));
1484  SCR scr = 0;
1485  if (from64)
1487  else
1488  scr = tc->readMiscRegNoEffect(MISCREG_SCR);
1489  return scr.irq;
1490 }
1491 
1492 bool
1494 {
1495  HCR hcr = tc->readMiscRegNoEffect(MISCREG_HCR);
1496  return fromEL == EL2 ||
1497  (EL2Enabled(tc) && fromEL <= EL1 && (hcr.tge || hcr.imo));
1498 }
1499 
1500 bool
1502 {
1503  if (ArmSystem::haveEL(tc, EL3)) {
1504  SCR scr = tc->readMiscRegNoEffect(MISCREG_SCR);
1505  return (!scr.ns || scr.aw);
1506  }
1507  return true;
1508 }
1509 
1511 {}
1512 
1513 bool
1515 {
1516  assert(ArmSystem::haveEL(tc, EL3));
1517  SCR scr = 0;
1518  if (from64)
1520  else
1521  scr = tc->readMiscRegNoEffect(MISCREG_SCR);
1522  return scr.fiq;
1523 }
1524 
1525 bool
1527 {
1528  HCR hcr = tc->readMiscRegNoEffect(MISCREG_HCR);
1529  return fromEL == EL2 ||
1530  (EL2Enabled(tc) && fromEL <= EL1 && (hcr.tge || hcr.fmo));
1531 }
1532 
1533 bool
1535 {
1536  if (ArmSystem::haveEL(tc, EL3)) {
1537  SCR scr = tc->readMiscRegNoEffect(MISCREG_SCR);
1538  return (!scr.ns || scr.aw);
1539  }
1540  return true;
1541 }
1542 
1543 bool
1545 {
1546  if (ArmSystem::haveEL(tc, EL2)) {
1547  return true;
1548  } else if (ArmSystem::haveEL(tc, EL3)) {
1549  SCR scr = tc->readMiscRegNoEffect(MISCREG_SCR);
1550  return (!scr.ns || scr.fw);
1551  }
1552  return true;
1553 }
1554 
1556 {}
1557 
1558 void
1560 {
1562  assert(from64);
1563  // Set the FAR
1565 }
1566 
1567 bool
1569 {
1570  HCR hcr = tc->readMiscRegNoEffect(MISCREG_HCR_EL2);
1571  return fromEL == EL2 || (EL2Enabled(tc) && fromEL <= EL1 && hcr.tge);
1572 }
1573 
1575 {}
1576 
1577 bool
1579 {
1580  assert(from64);
1581  HCR hcr = tc->readMiscRegNoEffect(MISCREG_HCR_EL2);
1582  return EL2Enabled(tc) && currEL(tc) <= EL1 && hcr.tge == 1;
1583 }
1584 
1586 {}
1587 
1588 void
1590 {
1591  tc->getCpuPtr()->clearInterrupt(tc->threadId(), INT_ABT, 0);
1592  ArmFault::invoke(tc, inst);
1593 }
1594 
1595 bool
1597 {
1598  assert(ArmSystem::haveEL(tc, EL3));
1599  assert(from64);
1600  SCR scr = tc->readMiscRegNoEffect(MISCREG_SCR_EL3);
1601  return scr.ea || fromEL == EL3;
1602 }
1603 
1604 bool
1606 {
1607  assert(from64);
1608 
1609  HCR hcr = tc->readMiscRegNoEffect(MISCREG_HCR_EL2);
1610 
1611  return fromEL == EL2 ||
1612  (EL2Enabled(tc) && fromEL <= EL1 && (hcr.tge || hcr.amo));
1613 }
1614 
1615 
1617  : ArmFaultVals<SoftwareBreakpoint>(_mach_inst, _iss)
1618 {}
1619 
1620 bool
1622 {
1623  const HCR hcr = tc->readMiscRegNoEffect(MISCREG_HCR_EL2);
1624  const HDCR mdcr = tc->readMiscRegNoEffect(MISCREG_MDCR_EL2);
1625 
1626  return fromEL == EL2 ||
1627  (EL2Enabled(tc) && fromEL <= EL1 && (hcr.tge || mdcr.tde));
1628 }
1629 
1632 {
1634 }
1635 
1637  : ArmFaultVals<HardwareBreakpoint>(0x0, _iss), vAddr(_vaddr)
1638 {}
1639 
1640 bool
1642 {
1643  const HCR hcr = tc->readMiscRegNoEffect(MISCREG_HCR_EL2);
1644  const HDCR mdcr = tc->readMiscRegNoEffect(MISCREG_MDCR_EL2);
1645 
1646  return EL2Enabled(tc) && fromEL <= EL1 && (hcr.tge || mdcr.tde);
1647 }
1648 
1651 {
1652  // AArch64
1653  if (toEL == fromEL)
1654  return EC_HW_BREAKPOINT_CURR_EL;
1655  else
1657 }
1658 
1659 void
1661 {
1662 
1664  MiscRegIndex elr_idx;
1665  switch (toEL) {
1666  case EL1:
1667  elr_idx = MISCREG_ELR_EL1;
1668  break;
1669  case EL2:
1670  assert(ArmSystem::haveEL(tc, EL2));
1671  elr_idx = MISCREG_ELR_EL2;
1672  break;
1673  case EL3:
1674  assert(ArmSystem::haveEL(tc, EL3));
1675  elr_idx = MISCREG_ELR_EL3;
1676  break;
1677  default:
1678  panic("Invalid target exception level");
1679  break;
1680  }
1681 
1682  tc->setMiscReg(elr_idx, vAddr);
1683 
1684 }
1685 
1687  bool _write, bool _cm)
1688  : ArmFaultVals<Watchpoint>(_mach_inst), vAddr(_vaddr),
1689  write(_write), cm(_cm)
1690 {}
1691 
1692 uint32_t
1694 {
1695  uint32_t iss = 0x0022;
1696 // NV
1697 // if (toEL == EL2)
1698 // iss |= 0x02000;
1699  if (cm)
1700  iss |= 0x00100;
1701  if (write)
1702  iss |= 0x00040;
1703  return iss;
1704 }
1705 
1706 void
1708 {
1710  // Set the FAR
1712 
1713 }
1714 
1715 bool
1717 {
1718  const HCR hcr = tc->readMiscRegNoEffect(MISCREG_HCR_EL2);
1719  const HDCR mdcr = tc->readMiscRegNoEffect(MISCREG_MDCR_EL2);
1720 
1721  return fromEL == EL2 ||
1722  (EL2Enabled(tc) && fromEL <= EL1 && (hcr.tge || mdcr.tde));
1723 }
1724 
1725 void
1727 {
1729  switch (id)
1730  {
1731  case OFA:
1732  vAddr = val;
1733  break;
1734  // Just ignore unknown ID's
1735  default:
1736  break;
1737  }
1738 }
1739 
1742 {
1743  // AArch64
1744  if (toEL == fromEL)
1745  return EC_WATCHPOINT_CURR_EL;
1746  else
1747  return EC_WATCHPOINT_LOWER_EL;
1748 }
1749 
1751  bool _stepped)
1752  : ArmFaultVals<SoftwareStepFault>(_mach_inst), isldx(is_ldx),
1753  stepped(_stepped)
1754 {
1755  bStep = true;
1756 }
1757 
1758 bool
1760 {
1761  const HCR hcr = tc->readMiscRegNoEffect(MISCREG_HCR_EL2);
1762  const HDCR mdcr = tc->readMiscRegNoEffect(MISCREG_MDCR_EL2);
1763 
1764  return fromEL == EL2 ||
1765  (EL2Enabled(tc) && fromEL <= EL1 && (hcr.tge || mdcr.tde));
1766 }
1767 
1770 {
1771  // AArch64
1772  if (toEL == fromEL)
1773  return EC_SOFTWARE_STEP_CURR_EL;
1774  else
1776 }
1777 
1778 uint32_t
1780 {
1781  uint32_t iss= 0x0022;
1782  if (stepped) {
1783  iss |= 0x1000000;
1784  }
1785 
1786  if (isldx) {
1787  iss |= 0x40;
1788  }
1789 
1790  return iss;
1791 
1792 }
1793 
1794 void
1796  DPRINTF(Faults, "Invoking ArmSev Fault\n");
1797  if (!FullSystem)
1798  return;
1799 
1800  // Set sev_mailbox to 1, clear the pending interrupt from remote
1801  // SEV execution and let pipeline continue as pcState is still
1802  // valid.
1804  tc->getCpuPtr()->clearInterrupt(tc->threadId(), INT_SEV, 0);
1805 }
1806 
1807 // Instantiate all the templates to make the linker happy
1808 template class ArmFaultVals<Reset>;
1809 template class ArmFaultVals<UndefinedInstruction>;
1810 template class ArmFaultVals<SupervisorCall>;
1811 template class ArmFaultVals<SecureMonitorCall>;
1812 template class ArmFaultVals<HypervisorCall>;
1813 template class ArmFaultVals<PrefetchAbort>;
1814 template class ArmFaultVals<DataAbort>;
1815 template class ArmFaultVals<VirtualDataAbort>;
1816 template class ArmFaultVals<HypervisorTrap>;
1817 template class ArmFaultVals<Interrupt>;
1818 template class ArmFaultVals<VirtualInterrupt>;
1819 template class ArmFaultVals<FastInterrupt>;
1820 template class ArmFaultVals<VirtualFastInterrupt>;
1821 template class ArmFaultVals<SupervisorTrap>;
1822 template class ArmFaultVals<SecureMonitorTrap>;
1823 template class ArmFaultVals<PCAlignmentFault>;
1824 template class ArmFaultVals<SPAlignmentFault>;
1825 template class ArmFaultVals<SystemError>;
1826 template class ArmFaultVals<SoftwareBreakpoint>;
1827 template class ArmFaultVals<HardwareBreakpoint>;
1828 template class ArmFaultVals<Watchpoint>;
1829 template class ArmFaultVals<SoftwareStepFault>;
1830 template class ArmFaultVals<ArmSev>;
1831 template class AbortFault<PrefetchAbort>;
1832 template class AbortFault<DataAbort>;
1833 template class AbortFault<VirtualDataAbort>;
1834 
1835 
1837 {}
1838 
1839 bool
1841 {
1842  const HCR hcr = tc->readMiscRegNoEffect(MISCREG_HCR_EL2);
1843  return EL2Enabled(tc) && fromEL == EL0 && hcr.tge;
1844 }
1845 
1846 bool
1848 {
1849  auto arm_fault = dynamic_cast<ArmFault *>(fault.get());
1850 
1851  if (arm_fault) {
1852  return arm_fault->getFaultVAddr(va);
1853  } else {
1854  auto pgt_fault = dynamic_cast<GenericPageTableFault *>(fault.get());
1855  if (pgt_fault) {
1856  va = pgt_fault->getFaultVAddr();
1857  return true;
1858  }
1859 
1860  auto align_fault = dynamic_cast<GenericAlignmentFault *>(fault.get());
1861  if (align_fault) {
1862  va = align_fault->getFaultVAddr();
1863  return true;
1864  }
1865 
1866  // Return false since it's not an address triggered exception
1867  return false;
1868  }
1869 }
1870 
1871 } // namespace ArmISA
1872 } // namespace gem5
gem5::ThreadContext::setIntReg
virtual void setIntReg(RegIndex reg_idx, RegVal val)=0
gem5::ArmISA::MISCREG_FAR_EL1
@ MISCREG_FAR_EL1
Definition: misc.hh:649
gem5::ArmISA::MISCREG_CPSR
@ MISCREG_CPSR
Definition: misc.hh:61
gem5::ArmISA::ArmFault::NODEBUG
@ NODEBUG
Definition: faults.hh:159
gem5::ArmISA::ArmFault::fromEL
ExceptionLevel fromEL
Definition: faults.hh:74
gem5::ArmISA::AbortFault::annotate
void annotate(ArmFault::AnnotationIDs id, uint64_t val) override
Definition: faults.cc:1235
gem5::ArmISA::CCREG_C
@ CCREG_C
Definition: cc.hh:50
gem5::ArmISA::AbortFault::setSyndrome
void setSyndrome(ThreadContext *tc, MiscRegIndex syndrome_reg) override
Definition: faults.cc:1162
gem5::ArmISA::ArmFault::FaultVals::ec
const ExceptionClass ec
Definition: faults.hh:194
gem5::ArmISA::ArmFault::NumFaultSources
@ NumFaultSources
Definition: faults.hh:119
gem5::ArmISA::SupervisorTrap::ec
ExceptionClass ec(ThreadContext *tc) const override
Definition: faults.cc:1063
gem5::PCStateBase::instAddr
Addr instAddr() const
Returns the memory address of the instruction this PC points to.
Definition: pcstate.hh:107
gem5::ArmISA::EC_SOFTWARE_STEP
@ EC_SOFTWARE_STEP
Definition: types.hh:335
gem5::ArmISA::EC_PREFETCH_ABORT_TO_HYP
@ EC_PREFETCH_ABORT_TO_HYP
Definition: types.hh:319
gem5::ArmISA::MISCREG_VBAR_EL3
@ MISCREG_VBAR_EL3
Definition: misc.hh:742
gem5::ThreadContext::readMiscReg
virtual RegVal readMiscReg(RegIndex misc_reg)=0
gem5::ArmISA::UndefinedInstruction::mnemonic
const char * mnemonic
Definition: faults.hh:310
gem5::ArmISA::SPAlignmentFault::SPAlignmentFault
SPAlignmentFault()
Definition: faults.cc:1574
gem5::ArmISA::MODE_SVC
@ MODE_SVC
Definition: types.hh:284
gem5::ArmISA::EC_HVC
@ EC_HVC
Definition: types.hh:311
gem5::ArmISA::DataAbort::routeToMonitor
bool routeToMonitor(ThreadContext *tc) const override
Definition: faults.cc:1371
gem5::NoFault
constexpr decltype(nullptr) NoFault
Definition: types.hh:260
gem5::ArmISA::MISCREG_TTBCR_S
@ MISCREG_TTBCR_S
Definition: misc.hh:262
gem5::ThreadContext::getSystemPtr
virtual System * getSystemPtr()=0
gem5::ArmISA::MODE_MON
@ MODE_MON
Definition: types.hh:285
gem5::ArmISA::UndefinedInstruction::ec
ExceptionClass ec(ThreadContext *tc) const override
Definition: faults.cc:927
gem5::ArmISA::ELIs64
bool ELIs64(ThreadContext *tc, ExceptionLevel el)
Definition: utility.cc:290
gem5::ArmISA::SoftwareBreakpoint::routeToHyp
bool routeToHyp(ThreadContext *tc) const override
Definition: faults.cc:1621
gem5::ArmISA::EC_ILLEGAL_INST
@ EC_ILLEGAL_INST
Definition: types.hh:308
gem5::ArmISA::DataAbort::sf
bool sf
Definition: faults.hh:520
gem5::ArmISA::MODE_FIQ
@ MODE_FIQ
Definition: types.hh:282
gem5::ArmISA::EC_WATCHPOINT
@ EC_WATCHPOINT
Definition: types.hh:338
gem5::ArmISA::ArmFault::bStep
bool bStep
Definition: faults.hh:71
gem5::ArmISA::Watchpoint::Watchpoint
Watchpoint(ExtMachInst _mach_inst, Addr _vaddr, bool _write, bool _cm)
Definition: faults.cc:1686
gem5::ArmSystem::highestELIs64
bool highestELIs64() const
Returns true if the register width of the highest implemented exception level is 64 bits (ARMv8)
Definition: system.hh:183
gem5::ArmISA::SelfDebug
Definition: self_debug.hh:277
gem5::ArmISA::ArmFault::FaultSourceInvalid
@ FaultSourceInvalid
Definition: faults.hh:120
gem5::ArmISA::PCAlignmentFault::faultPC
Addr faultPC
The unaligned value of the PC.
Definition: faults.hh:592
gem5::ArmISA::ArmFault::abortDisable
virtual bool abortDisable(ThreadContext *tc)=0
gem5::ArmISA::cm
Bitfield< 13 > cm
Definition: misc_types.hh:429
gem5::ArmISA::EC_HW_BREAKPOINT_LOWER_EL
@ EC_HW_BREAKPOINT_LOWER_EL
Definition: types.hh:333
gem5::ArmISA::ArmStaticInst
Definition: static_inst.hh:65
gem5::ArmISA::ArmFault::BRKPOINT
@ BRKPOINT
Definition: faults.hh:160
gem5::ArmISA::HypervisorCall
Definition: faults.hh:407
gem5::ArmISA::EC_SERROR
@ EC_SERROR
Definition: types.hh:331
gem5::ArmISA::ArmFault::issRaw
uint32_t issRaw
Definition: faults.hh:68
gem5::ArmISA::EC_SVC_TO_HYP
@ EC_SVC_TO_HYP
Definition: types.hh:309
gem5::ArmISA::ArmFault::AR
@ AR
Definition: faults.hh:147
gem5::ArmISA::MISCREG_SPSR_FIQ
@ MISCREG_SPSR_FIQ
Definition: misc.hh:63
gem5::ArmISA::SystemError::SystemError
SystemError()
Definition: faults.cc:1585
gem5::ArmISA::HypervisorTrap::overrideEc
ExceptionClass overrideEc
Definition: faults.hh:422
gem5::ArmISA::MISCREG_MDCR_EL2
@ MISCREG_MDCR_EL2
Definition: misc.hh:587
gem5::ArmISA::EC_DATA_ABORT_LOWER_EL
@ EC_DATA_ABORT_LOWER_EL
Definition: types.hh:325
gem5::ArmISA::ArmFaultVals::vals
static FaultVals vals
Definition: faults.hh:264
gem5::ArmISA::SecureMonitorCall::ec
ExceptionClass ec(ThreadContext *tc) const override
Definition: faults.cc:1040
gem5::ArmISA::condCode
Bitfield< 31, 28 > condCode
Definition: types.hh:111
gem5::ArmISA::ArmFault::from64
bool from64
Definition: faults.hh:72
gem5::ArmISA::MODE_UNDEFINED
@ MODE_UNDEFINED
Definition: types.hh:288
gem5::ArmISA::HardwareBreakpoint::routeToHyp
bool routeToHyp(ThreadContext *tc) const override
Definition: faults.cc:1641
gem5::PCStateBase::as
Target & as()
Definition: pcstate.hh:72
gem5::ArmISA::MODE_IRQ
@ MODE_IRQ
Definition: types.hh:283
gem5::ArmISA::ArmFault::VECTORCATCH
@ VECTORCATCH
Definition: faults.hh:161
gem5::ArmISA::MISCREG_SCR_EL3
@ MISCREG_SCR_EL3
Definition: misc.hh:593
gem5::ArmISA::domain
Bitfield< 7, 4 > domain
Definition: misc_types.hh:424
gem5::ArmISA::HypervisorTrap::ec
ExceptionClass ec(ThreadContext *tc) const override
Definition: faults.cc:963
gem5::ThreadContext::pcState
virtual const PCStateBase & pcState() const =0
gem5::ArmISA::UndefinedInstruction::overrideEc
ExceptionClass overrideEc
Definition: faults.hh:309
gem5::ArmISA::CCREG_NZ
@ CCREG_NZ
Definition: cc.hh:49
gem5::ArmISA::UndefinedInstruction::disabled
bool disabled
Definition: faults.hh:308
gem5::ArmISA::ArmFault::SynchronousExternalAbort
@ SynchronousExternalAbort
Definition: faults.hh:106
gem5::ArmISA::EC_HVC_64
@ EC_HVC_64
Definition: types.hh:315
gem5::ArmISA::ArmFault::LpaeTran
@ LpaeTran
Definition: faults.hh:152
gem5::ArmISA::ArmFault::faultUpdated
bool faultUpdated
Definition: faults.hh:82
gem5::ArmISA::ArmFault::SSE
@ SSE
Definition: faults.hh:137
gem5::ArmISA::MISCREG_VBAR_EL2
@ MISCREG_VBAR_EL2
Definition: misc.hh:740
gem5::ArmISA::UndefinedInstruction::unknown
bool unknown
Definition: faults.hh:307
gem5::ArmISA::MISCREG_HSCTLR
@ MISCREG_HSCTLR
Definition: misc.hh:246
gem5::ArmISA::MISCREG_ESR_EL2
@ MISCREG_ESR_EL2
Definition: misc.hh:644
gem5::ArmISA::DataAbort::iss
uint32_t iss() const override
Definition: faults.cc:1407
gem5::ArmISA::PCAlignmentFault::routeToHyp
bool routeToHyp(ThreadContext *tc) const override
Definition: faults.cc:1568
gem5::ArmISA::HypervisorCall::routeToHyp
bool routeToHyp(ThreadContext *tc) const override
Definition: faults.cc:951
gem5::X86ISA::val
Bitfield< 63 > val
Definition: misc.hh:775
gem5::ArmISA::ArmFault::armPcElrOffset
virtual uint8_t armPcElrOffset()=0
gem5::ArmISA::Watchpoint::vAddr
Addr vAddr
Definition: faults.hh:645
gem5::ArmISA::AbortFault::getFaultStatusCode
uint8_t getFaultStatusCode(ThreadContext *tc) const
Definition: faults.cc:1173
gem5::ArmISA::PrefetchAbort::routeToMonitor
bool routeToMonitor(ThreadContext *tc) const override
Definition: faults.cc:1315
gem5::ArmISA::opModeIsT
static bool opModeIsT(OperatingMode mode)
Definition: types.hh:376
gem5::ArmISA::ArmFault::DomainLL
@ DomainLL
Definition: faults.hh:103
gem5::ArmISA::MISCREG_LOCKFLAG
@ MISCREG_LOCKFLAG
Definition: misc.hh:83
gem5::ArmISA::Interrupt::routeToMonitor
bool routeToMonitor(ThreadContext *tc) const override
Definition: faults.cc:1481
gem5::ArmISA::EL1
@ EL1
Definition: types.hh:267
gem5::ArmISA::EC_SOFTWARE_BREAKPOINT
@ EC_SOFTWARE_BREAKPOINT
Definition: types.hh:341
gem5::ArmISA::ArmFault::offset64
virtual FaultOffset offset64(ThreadContext *tc)=0
gem5::ArmISA::ArmFault::DebugEvent
@ DebugEvent
Definition: faults.hh:105
gem5::System::workload
Workload * workload
OS kernel.
Definition: system.hh:330
gem5::ArmISA::Watchpoint::routeToHyp
bool routeToHyp(ThreadContext *tc) const override
Definition: faults.cc:1716
gem5::ArmISA::opModeToEL
static ExceptionLevel opModeToEL(OperatingMode mode)
Definition: types.hh:383
gem5::ArmISA::MISCREG_SPSR_MON
@ MISCREG_SPSR_MON
Definition: misc.hh:66
gem5::ArmISA::ELIsInHost
bool ELIsInHost(ThreadContext *tc, ExceptionLevel el)
Returns true if the current exception level el is executing a Host OS or an application of a Host OS ...
Definition: utility.cc:304
gem5::ArmISA::Watchpoint
Definition: faults.hh:642
gem5::csprintf
std::string csprintf(const char *format, const Args &...args)
Definition: cprintf.hh:161
gem5::ArmISA::SupervisorTrap::iss
uint32_t iss() const override
Definition: faults.cc:1053
gem5::RefCountingPtr::get
T * get() const
Directly access the pointer itself without taking a reference.
Definition: refcnt.hh:227
gem5::X86ISA::base
Bitfield< 51, 12 > base
Definition: pagetable.hh:141
gem5::ArmISA::HardwareBreakpoint::vAddr
Addr vAddr
Definition: faults.hh:633
gem5::ArmISA::VirtualDataAbort::invoke
void invoke(ThreadContext *tc, const StaticInstPtr &inst) override
Definition: faults.cc:1472
gem5::ArmISA::SoftwareStepFault::isldx
bool isldx
Definition: faults.hh:662
system.hh
gem5::ArmISA::ArmStaticInst::encoding
MachInst encoding() const
Returns the real encoding of the instruction: the machInst field is in fact always 64 bit wide and co...
Definition: static_inst.hh:565
gem5::ArmISA::ArmFault::setSyndrome
virtual void setSyndrome(ThreadContext *tc, MiscRegIndex syndrome_reg)
Definition: faults.cc:398
gem5::ArmISA::ArmFault::to64
bool to64
Definition: faults.hh:73
gem5::ArmISA::MISCREG_SCTLR
@ MISCREG_SCTLR
Definition: misc.hh:235
gem5::ArmISA::getFaultVAddr
bool getFaultVAddr(Fault fault, Addr &va)
Returns true if the fault passed as a first argument was triggered by a memory access,...
Definition: faults.cc:1847
gem5::PowerISA::PCState
Definition: pcstate.hh:42
gem5::ArmISA::SoftwareBreakpoint::ec
ExceptionClass ec(ThreadContext *tc) const override
Definition: faults.cc:1631
gem5::ArmISA::SystemError::routeToHyp
bool routeToHyp(ThreadContext *tc) const override
Definition: faults.cc:1605
gem5::ArmISA::ArmFault::getVector64
Addr getVector64(ThreadContext *tc)
Definition: faults.cc:343
gem5::ArmISA::SystemError::routeToMonitor
bool routeToMonitor(ThreadContext *tc) const override
Definition: faults.cc:1596
gem5::StaticInst::advancePC
virtual void advancePC(PCStateBase &pc_state) const =0
gem5::ArmISA::ArmFault::PermissionLL
@ PermissionLL
Definition: faults.hh:104
gem5::FaultBase::name
virtual FaultName name() const =0
gem5::ThreadContext::readCCReg
virtual RegVal readCCReg(RegIndex reg_idx) const =0
gem5::ArmISA::EC_WATCHPOINT_LOWER_EL
@ EC_WATCHPOINT_LOWER_EL
Definition: types.hh:339
gem5::ArmISA::ArmFault::AsynchronousExternalAbort
@ AsynchronousExternalAbort
Definition: faults.hh:109
gem5::ArmISA::PCAlignmentFault::invoke
void invoke(ThreadContext *tc, const StaticInstPtr &inst=nullStaticInstPtr) override
Definition: faults.cc:1559
gem5::RefCountingPtr< StaticInst >
gem5::ArmISA::ArmFault::VmsaTran
@ VmsaTran
Definition: faults.hh:153
gem5::ArmISA::AbortFault::getFsr
FSR getFsr(ThreadContext *tc) const override
Definition: faults.cc:1199
gem5::ArmISA::MISCREG_DBGDSCRext
@ MISCREG_DBGDSCRext
Definition: misc.hh:103
gem5::ArmISA::EC_SMC_64
@ EC_SMC_64
Definition: types.hh:316
gem5::ArmISA::purifyTaggedAddr
Addr purifyTaggedAddr(Addr addr, ThreadContext *tc, ExceptionLevel el, TCR tcr, bool is_instr)
Removes the tag from tagged addresses if that mode is enabled.
Definition: utility.cc:469
gem5::ArmISA::SupervisorCall::iss
uint32_t iss() const override
Definition: faults.cc:911
gem5::ArmISA::ArmFault::OFA
@ OFA
Definition: faults.hh:140
gem5::ArmISA::ArmFault::iss
virtual uint32_t iss() const =0
gem5::GenericPageTableFault
Definition: faults.hh:116
gem5::ArmISA::FastInterrupt::abortDisable
bool abortDisable(ThreadContext *tc) override
Definition: faults.cc:1534
gem5::ArmISA::INT_ABT
@ INT_ABT
Definition: interrupts.hh:61
gem5::ArmISA::Watchpoint::invoke
void invoke(ThreadContext *tc, const StaticInstPtr &inst=nullStaticInstPtr) override
Definition: faults.cc:1707
gem5::ArmISA::amo
Bitfield< 5 > amo
Definition: misc_types.hh:280
gem5::ArmISA::ArmFault::instrAnnotate
ArmStaticInst * instrAnnotate(const StaticInstPtr &inst)
Definition: faults.cc:759
gem5::ArmISA::MISCREG_ELR_EL1
@ MISCREG_ELR_EL1
Definition: misc.hh:614
gem5::ArmISA::ArmFault::thumbPcElrOffset
virtual uint8_t thumbPcElrOffset()=0
gem5::ArmISA::ArmFaultVals
Definition: faults.hh:261
interrupts.hh
gem5::ThreadContext
ThreadContext is the external interface to all thread state for anything outside of the CPU.
Definition: thread_context.hh:94
gem5::ArmISA::EC_UNKNOWN
@ EC_UNKNOWN
Definition: types.hh:296
gem5::ArmISA::MODE_HYP
@ MODE_HYP
Definition: types.hh:287
gem5::ArmISA::ArmFault::offset
virtual FaultOffset offset(ThreadContext *tc)=0
gem5::ArmISA::MISCREG_SCTLR_EL1
@ MISCREG_SCTLR_EL1
Definition: misc.hh:579
gem5::ArmISA::SoftwareStepFault
Definition: faults.hh:659
gem5::ArmISA::HardwareBreakpoint
Definition: faults.hh:630
gem5::ArmISA::ArmFault::thumbPcOffset
virtual uint8_t thumbPcOffset(bool isHyp)=0
gem5::Fault
std::shared_ptr< FaultBase > Fault
Definition: types.hh:255
gem5::ArmISA::MISCREG_HDCR
@ MISCREG_HDCR
Definition: misc.hh:250
gem5::ArmISA::HaveVirtHostExt
bool HaveVirtHostExt(ThreadContext *tc)
Definition: utility.cc:232
gem5::ArmISA::EC_SOFTWARE_BREAKPOINT_64
@ EC_SOFTWARE_BREAKPOINT_64
Definition: types.hh:343
gem5::ArmISA::ArmFault::getSyndromeReg64
MiscRegIndex getSyndromeReg64() const
Definition: faults.cc:366
gem5::ArmISA::SecureMonitorCall::invoke
void invoke(ThreadContext *tc, const StaticInstPtr &inst=nullStaticInstPtr) override
Definition: faults.cc:1031
DPRINTF
#define DPRINTF(x,...)
Definition: trace.hh:186
gem5::ArmISA::ArmFault::toEL
ExceptionLevel toEL
Definition: faults.hh:75
gem5::ArmISA::MISCREG_MVBAR
@ MISCREG_MVBAR
Definition: misc.hh:394
gem5::ArmISA::DataAbort::ec
ExceptionClass ec(ThreadContext *tc) const override
Definition: faults.cc:1342
gem5::ArmISA::SecureMonitorTrap::ec
ExceptionClass ec(ThreadContext *tc) const override
Definition: faults.cc:1072
gem5::ArmISA::FastInterrupt::routeToHyp
bool routeToHyp(ThreadContext *tc) const override
Definition: faults.cc:1526
gem5::ArmISA::ArmFault::hypRouted
bool hypRouted
Definition: faults.hh:84
gem5::ArmISA::EL2
@ EL2
Definition: types.hh:268
gem5::ArmISA::MISCREG_SPSR_IRQ
@ MISCREG_SPSR_IRQ
Definition: misc.hh:64
gem5::ArmISA::SupervisorCall::invoke
void invoke(ThreadContext *tc, const StaticInstPtr &inst=nullStaticInstPtr) override
Definition: faults.cc:877
gem5::ArmISA::MISCREG_SCTLR_EL2
@ MISCREG_SCTLR_EL2
Definition: misc.hh:584
gem5::ArmISA::COND_UC
@ COND_UC
Definition: cc.hh:84
gem5::ArmISA::ArmFault::shortDescFaultSources
static uint8_t shortDescFaultSources[NumFaultSources]
Encodings of the fault sources when the short-desc.
Definition: faults.hh:125
gem5::ArmISA::DataAbort::sas
uint8_t sas
Definition: faults.hh:514
isa.hh
gem5::ArmISA::ELIs32
bool ELIs32(ThreadContext *tc, ExceptionLevel el)
Definition: utility.cc:296
gem5::ArmISA::ArmFault::update
void update(ThreadContext *tc)
Definition: faults.cc:439
gem5::ArmISA::ArmFaultVals::offset64
FaultOffset offset64(ThreadContext *tc) override
Definition: faults.cc:990
gem5::ArmISA::syncVecElemsToRegs
void syncVecElemsToRegs(ThreadContext *tc)
Definition: utility.cc:1358
gem5::ArmISA::ArmFault::getFaultVAddr
virtual bool getFaultVAddr(Addr &va) const
Definition: faults.hh:256
gem5::ArmISA::MISCREG_VMPIDR
@ MISCREG_VMPIDR
Definition: misc.hh:234
gem5::ArmISA::Watchpoint::cm
bool cm
Definition: faults.hh:647
gem5::ArmISA::SecureMonitorCall::iss
uint32_t iss() const override
Definition: faults.cc:919
gem5::ArmISA::UndefinedInstruction::routeToHyp
bool routeToHyp(ThreadContext *tc) const override
Definition: faults.cc:840
gem5::ArmISA::AbortFault::iss
uint32_t iss() const override
Definition: faults.cc:1254
gem5::ArmISA::AbortFault::abortDisable
bool abortDisable(ThreadContext *tc) override
Definition: faults.cc:1224
gem5::ArmISA::UndefinedInstruction::invoke
void invoke(ThreadContext *tc, const StaticInstPtr &inst=nullStaticInstPtr) override
Definition: faults.cc:817
gem5::ArmISA::EL2Enabled
bool EL2Enabled(ThreadContext *tc)
Definition: utility.cc:282
gem5::ArmISA::SupervisorTrap::overrideEc
ExceptionClass overrideEc
Definition: faults.hh:377
gem5::PowerISA::AlignmentFault
Definition: faults.hh:82
gem5::ArmISA::MISCREG_SPSR_EL2
@ MISCREG_SPSR_EL2
Definition: misc.hh:625
gem5::ArmISA::DataAbort::srt
uint8_t srt
Definition: faults.hh:516
gem5::ArmISA::VirtualInterrupt::VirtualInterrupt
VirtualInterrupt()
Definition: faults.cc:1510
gem5::ArmISA::DataAbort::annotate
void annotate(AnnotationIDs id, uint64_t val) override
Definition: faults.cc:1434
gem5::ArmISA::ArmFault::SF
@ SF
Definition: faults.hh:146
gem5::bits
constexpr T bits(T val, unsigned first, unsigned last)
Extract the bitfield from position 'first' to 'last' (inclusive) from 'val' and right justify it.
Definition: bitfield.hh:76
compiler.hh
gem5::GenericAlignmentFault
Definition: faults.hh:128
gem5::ArmISA::EL3
@ EL3
Definition: types.hh:269
gem5::ArmISA::ArmFault::nextMode
virtual OperatingMode nextMode()=0
gem5::ArmISA::FastInterrupt::fiqDisable
bool fiqDisable(ThreadContext *tc) override
Definition: faults.cc:1544
gem5::ThreadContext::readMiscRegNoEffect
virtual RegVal readMiscRegNoEffect(RegIndex misc_reg) const =0
faults.hh
gem5::ArmISA::DataAbort::cm
uint8_t cm
Definition: faults.hh:517
gem5::ArmISA::MISCREG_ID_AA64MMFR1_EL1
@ MISCREG_ID_AA64MMFR1_EL1
Definition: misc.hh:570
gem5::ArmISA::MISCREG_SPSR_EL1
@ MISCREG_SPSR_EL1
Definition: misc.hh:612
gem5::ArmISA::COND_AL
@ COND_AL
Definition: cc.hh:83
gem5::PowerISA::INTREG_LR
@ INTREG_LR
Definition: int.hh:64
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::ThreadContext::readIntReg
virtual RegVal readIntReg(RegIndex reg_idx) const =0
gem5::ArmISA::SoftwareBreakpoint::SoftwareBreakpoint
SoftwareBreakpoint(ExtMachInst _mach_inst, uint32_t _iss)
Definition: faults.cc:1616
gem5::ArmISA::SoftwareBreakpoint
System error (AArch64 only)
Definition: faults.hh:621
gem5::ArmISA::ArmFaultVals< Reset >::offset
FaultOffset offset(ThreadContext *tc) override
Definition: faults.cc:970
gem5::ArmISA::SoftwareStepFault::iss
uint32_t iss() const override
Definition: faults.cc:1779
gem5::ArmISA::HypervisorCall::ec
ExceptionClass ec(ThreadContext *tc) const override
Definition: faults.cc:957
gem5::ArmISA::MiscRegIndex
MiscRegIndex
Definition: misc.hh:59
gem5::ArmISA::HardwareBreakpoint::ec
ExceptionClass ec(ThreadContext *tc) const override
Definition: faults.cc:1650
gem5::ArmISA::isSecure
bool isSecure(ThreadContext *tc)
Definition: utility.cc:73
gem5::ArmISA::CCREG_GE
@ CCREG_GE
Definition: cc.hh:52
gem5::ArmISA::va
Bitfield< 8 > va
Definition: misc_types.hh:276
gem5::FaultBase::invoke
virtual void invoke(ThreadContext *tc, const StaticInstPtr &inst=nullStaticInstPtr)
Definition: faults.cc:58
gem5::ArmISA::AbortFault::getFaultVAddr
bool getFaultVAddr(Addr &va) const override
Definition: faults.cc:1283
utility.hh
gem5::ArmISA::ExceptionClass
ExceptionClass
Definition: types.hh:293
gem5::ArmISA::SoftwareStepFault::routeToHyp
bool routeToHyp(ThreadContext *tc) const override
Definition: faults.cc:1759
full_system.hh
gem5::ArmISA::ArmFault::getFaultAddrReg64
MiscRegIndex getFaultAddrReg64() const
Definition: faults.cc:382
gem5::ArmISA::HardwareBreakpoint::HardwareBreakpoint
HardwareBreakpoint(Addr _vaddr, uint32_t _iss)
Definition: faults.cc:1636
gem5::ArmISA::Reset::getVector
Addr getVector(ThreadContext *tc) override
Definition: faults.cc:771
gem5::ArmISA::currEL
ExceptionLevel currEL(const ThreadContext *tc)
Returns the current Exception Level (EL) of the provided ThreadContext.
Definition: utility.cc:128
gem5::ArmISA::ArmFault
Definition: faults.hh:64
gem5::ArmISA::AbortFault< DataAbort >::faultAddr
Addr faultAddr
The virtual address the fault occured at.
Definition: faults.hh:444
gem5::ArmISA::FaultOffset
Addr FaultOffset
Definition: faults.hh:60
gem5::X86ISA::ExtMachInst
Definition: types.hh:206
gem5::FullSystem
bool FullSystem
The FullSystem variable can be used to determine the current mode of simulation.
Definition: root.cc:220
gem5::MipsISA::FaultVals
MipsFaultBase::FaultVals FaultVals
Definition: faults.cc:46
gem5::ArmISA::ArmFault::aarch64FaultSources
static uint8_t aarch64FaultSources[NumFaultSources]
Encodings of the fault sources in AArch64 state.
Definition: faults.hh:130
gem5::ArmISA::MISCREG_SPSR_EL3
@ MISCREG_SPSR_EL3
Definition: misc.hh:632
gem5::ArmISA::SupervisorCall::overrideEc
ExceptionClass overrideEc
Definition: faults.hh:339
gem5::ArmISA::EC_SOFTWARE_STEP_LOWER_EL
@ EC_SOFTWARE_STEP_LOWER_EL
Definition: types.hh:336
gem5::ArmISA::PrefetchAbort::routeToHyp
bool routeToHyp(ThreadContext *tc) const override
Definition: faults.cc:1327
gem5::ArmISA::EC_PREFETCH_ABORT_CURR_EL
@ EC_PREFETCH_ABORT_CURR_EL
Definition: types.hh:322
gem5::ArmISA::EL0
@ EL0
Definition: types.hh:266
panic_if
#define panic_if(cond,...)
Conditional panic macro that checks the supplied condition and only panics if the condition is true a...
Definition: logging.hh:204
gem5::ArmSystem
Definition: system.hh:91
gem5::ArmISA::SupervisorCall::routeToHyp
bool routeToHyp(ThreadContext *tc) const override
Definition: faults.cc:896
gem5::ArmISA::ArmFault::invoke64
void invoke64(ThreadContext *tc, const StaticInstPtr &inst=nullStaticInstPtr)
Definition: faults.cc:649
gem5::ArmISA::ArmFault::invoke
void invoke(ThreadContext *tc, const StaticInstPtr &inst=nullStaticInstPtr) override
Definition: faults.cc:489
gem5::ArmISA::MISCREG_HCR
@ MISCREG_HCR
Definition: misc.hh:248
gem5::ArmISA::SupervisorTrap::routeToHyp
bool routeToHyp(ThreadContext *tc) const override
Definition: faults.cc:1046
gem5::ArmISA::syncVecRegsToElems
void syncVecRegsToElems(ThreadContext *tc)
Definition: utility.cc:1345
gem5::ArmISA::DataAbort::isv
bool isv
Definition: faults.hh:513
gem5::ArmISA::MISCREG_TTBCR_NS
@ MISCREG_TTBCR_NS
Definition: misc.hh:261
gem5::ArmISA::Watchpoint::annotate
void annotate(AnnotationIDs id, uint64_t val) override
Definition: faults.cc:1726
gem5::ArmISA::VectorCatch::isVCMatch
bool isVCMatch() const
Definition: self_debug.hh:257
gem5::ArmISA::VectorCatch
Definition: self_debug.hh:242
gem5::ArmISA::ArmFault::AlignmentFault
@ AlignmentFault
Definition: faults.hh:97
gem5::ArmISA::AbortFault::isMMUFault
bool isMMUFault() const
Definition: faults.cc:1266
gem5::ArmISA::ArmFault::getVector
virtual Addr getVector(ThreadContext *tc)
Definition: faults.cc:311
gem5::ArmISA::ArmFault::isResetSPSR
bool isResetSPSR()
Definition: faults.hh:233
gem5::ArmISA::MISCREG_SPSR_SVC
@ MISCREG_SPSR_SVC
Definition: misc.hh:65
gem5::ArmISA::ArmFault::CM
@ CM
Definition: faults.hh:139
base.hh
gem5::ArmISA::EC_PREFETCH_ABORT_LOWER_EL
@ EC_PREFETCH_ABORT_LOWER_EL
Definition: types.hh:320
gem5::ArmISA::Watchpoint::iss
uint32_t iss() const override
Definition: faults.cc:1693
gem5::ArmISA::AbortFault::invoke
void invoke(ThreadContext *tc, const StaticInstPtr &inst=nullStaticInstPtr) override
Definition: faults.cc:1080
gem5::ArmISA::HighVecs
const uint32_t HighVecs
Definition: faults.cc:63
gem5::ArmISA::ArmFault::span
bool span
Definition: faults.hh:85
gem5::ArmISA::EC_HW_BREAKPOINT_CURR_EL
@ EC_HW_BREAKPOINT_CURR_EL
Definition: types.hh:334
gem5::ArmISA::ArmFault::TranslationLL
@ TranslationLL
Definition: faults.hh:101
gem5::ArmISA::AbortFault< PrefetchAbort >::stage2
bool stage2
Definition: faults.hh:455
gem5::ArmISA::SoftwareStepFault::SoftwareStepFault
SoftwareStepFault(ExtMachInst _mach_inst, bool is_ldx, bool stepped)
Definition: faults.cc:1750
gem5::ArmISA::ArmFault::WPOINT_CM
@ WPOINT_CM
Definition: faults.hh:162
gem5::ArmISA::ConditionCode
ConditionCode
Definition: cc.hh:67
gem5::ArmISA::ArmFaultVals::ec
ExceptionClass ec(ThreadContext *tc) const override
Definition: faults.hh:290
gem5::ThreadContext::setMiscReg
virtual void setMiscReg(RegIndex misc_reg, RegVal val)=0
static_inst.hh
gem5::ArmISA::ISA::getSelfDebug
SelfDebug * getSelfDebug() const
Definition: isa.hh:633
gem5::ArmISA::ArmFault::ec
virtual ExceptionClass ec(ThreadContext *tc) const =0
gem5::MipsISA::pc
Bitfield< 4 > pc
Definition: pra_constants.hh:243
gem5::ArmISA::ArmFault::AnnotationIDs
AnnotationIDs
Definition: faults.hh:132
gem5::ArmISA::MISCREG_SCR
@ MISCREG_SCR
Definition: misc.hh:243
gem5::ArmISA::MISCREG_ESR_EL3
@ MISCREG_ESR_EL3
Definition: misc.hh:648
gem5::ArmISA::MISCREG_ELR_EL2
@ MISCREG_ELR_EL2
Definition: misc.hh:626
gem5::ArmISA::longDescFormatInUse
bool longDescFormatInUse(ThreadContext *tc)
Definition: utility.cc:135
gem5::ArmISA::EC_DATA_ABORT_TO_HYP
@ EC_DATA_ABORT_TO_HYP
Definition: types.hh:324
gem5::ArmISA::ArmFault::annotate
virtual void annotate(AnnotationIDs id, uint64_t val)
Definition: faults.hh:238
gem5::ArmISA::EC_PC_ALIGNMENT
@ EC_PC_ALIGNMENT
Definition: types.hh:323
gem5::ArmSystem::resetAddr
Addr resetAddr() const
Returns the reset address if the highest implemented exception level is 64 bits (ARMv8)
Definition: system.hh:198
gem5::ArmISA::ArmFault::AccessFlagLL
@ AccessFlagLL
Definition: faults.hh:102
gem5::ArmISA::SoftwareStepFault::ec
ExceptionClass ec(ThreadContext *tc) const override
Definition: faults.cc:1769
gem5::ArmISA::UndefinedInstruction::iss
uint32_t iss() const override
Definition: faults.cc:848
gem5::ArmISA::MISCREG_SPSR_ABT
@ MISCREG_SPSR_ABT
Definition: misc.hh:67
gem5::ArmISA::EC_INVALID
@ EC_INVALID
Definition: types.hh:295
gem5::ArmISA::MISCREG_ELR_HYP
@ MISCREG_ELR_HYP
Definition: misc.hh:70
gem5::ArmISA::FastInterrupt::routeToMonitor
bool routeToMonitor(ThreadContext *tc) const override
Definition: faults.cc:1514
gem5::ArmISA::ArmFault::S1PTW
@ S1PTW
Definition: faults.hh:134
gem5::ArmISA::Reset::invoke
void invoke(ThreadContext *tc, const StaticInstPtr &inst=nullStaticInstPtr) override
Definition: faults.cc:789
gem5::ArmISA::sd
Bitfield< 4 > sd
Definition: misc_types.hh:775
gem5::ArmISA::MISCREG_HVBAR
@ MISCREG_HVBAR
Definition: misc.hh:397
gem5::ArmISA::HypervisorCall::HypervisorCall
HypervisorCall(ExtMachInst _machInst, uint32_t _imm)
Definition: faults.cc:938
gem5::ThreadContext::getCpuPtr
virtual BaseCPU * getCpuPtr()=0
gem5::ArmISA::ArmSev::invoke
void invoke(ThreadContext *tc, const StaticInstPtr &inst=nullStaticInstPtr) override
Definition: faults.cc:1795
gem5::ArmISA::MISCREG_VBAR
@ MISCREG_VBAR
Definition: misc.hh:391
gem5::ArmISA::ArmFault::toMode
OperatingMode toMode
Definition: faults.hh:77
gem5::ArmISA::ArmFault::routeToHyp
virtual bool routeToHyp(ThreadContext *tc) const
Definition: faults.hh:243
gem5::ThreadContext::clearArchRegs
virtual void clearArchRegs()=0
gem5::ArmISA::MISCREG_HSR
@ MISCREG_HSR
Definition: misc.hh:282
gem5::ArmISA::MISCREG_SEV_MAILBOX
@ MISCREG_SEV_MAILBOX
Definition: misc.hh:92
gem5::ArmISA::ArmFault::SRT
@ SRT
Definition: faults.hh:138
gem5::ArmISA::HardwareBreakpoint::invoke
void invoke(ThreadContext *tc, const StaticInstPtr &inst=nullStaticInstPtr) override
Definition: faults.cc:1660
gem5::ThreadContext::threadId
virtual int threadId() const =0
gem5::ArmISA::DataAbort::sse
uint8_t sse
Definition: faults.hh:515
trace.hh
gem5::ArmISA::MISCREG_ELR_EL3
@ MISCREG_ELR_EL3
Definition: misc.hh:633
gem5::ArmISA::ArmFault::vectorCatch
bool vectorCatch(ThreadContext *tc, const StaticInstPtr &inst)
Definition: faults.cc:745
gem5::ArmISA::Interrupt::routeToHyp
bool routeToHyp(ThreadContext *tc) const override
Definition: faults.cc:1493
gem5::ArmISA::PrefetchAbort::ec
ExceptionClass ec(ThreadContext *tc) const override
Definition: faults.cc:1290
gem5::ArmISA::DataAbort::routeToHyp
bool routeToHyp(ThreadContext *tc) const override
Definition: faults.cc:1383
gem5::ArmISA::HypervisorCall::routeToMonitor
bool routeToMonitor(ThreadContext *tc) const override
Definition: faults.cc:945
gem5::ArmISA::DataAbort::ar
bool ar
Definition: faults.hh:521
gem5::ArmISA::IllegalInstSetStateFault::routeToHyp
bool routeToHyp(ThreadContext *tc) const override
Definition: faults.cc:1840
gem5::ArmISA::SystemError::invoke
void invoke(ThreadContext *tc, const StaticInstPtr &inst=nullStaticInstPtr) override
Definition: faults.cc:1589
gem5::ArmISA::EC_SMC_TO_HYP
@ EC_SMC_TO_HYP
Definition: types.hh:312
self_debug.hh
gem5::ArmISA::ArmFault::machInst
ExtMachInst machInst
Definition: faults.hh:67
gem5::ArmSystem::haveEL
static bool haveEL(ThreadContext *tc, ArmISA::ExceptionLevel el)
Return true if the system implements a specific exception level.
Definition: system.cc:131
gem5::ArmISA::MODE_ABORT
@ MODE_ABORT
Definition: types.hh:286
gem5::ArmISA::MISCREG_HCR_EL2
@ MISCREG_HCR_EL2
Definition: misc.hh:586
gem5::ArmISA::ArmFault::armPcOffset
virtual uint8_t armPcOffset(bool isHyp)=0
gem5::ArmISA::SPAlignmentFault::routeToHyp
bool routeToHyp(ThreadContext *tc) const override
Definition: faults.cc:1578
gem5::ArmISA::EC_SOFTWARE_STEP_CURR_EL
@ EC_SOFTWARE_STEP_CURR_EL
Definition: types.hh:337
gem5::ArmISA::ArmFault::fromMode
OperatingMode fromMode
Definition: faults.hh:76
gem5::ArmISA::EC_SVC_64
@ EC_SVC_64
Definition: types.hh:314
gem5::ArmISA::MISCREG_FAR_EL2
@ MISCREG_FAR_EL2
Definition: misc.hh:651
gem5::ArmISA::MISCREG_FAR_EL3
@ MISCREG_FAR_EL3
Definition: misc.hh:653
gem5::ArmISA::SupervisorCall::ec
ExceptionClass ec(ThreadContext *tc) const override
Definition: faults.cc:904
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: tlb.cc:60
gem5::ArmISA::ArmFault::invoke32
void invoke32(ThreadContext *tc, const StaticInstPtr &inst=nullStaticInstPtr)
Definition: faults.cc:516
gem5::ArmISA::MISCREG_HPFAR_EL2
@ MISCREG_HPFAR_EL2
Definition: misc.hh:652
gem5::ArmISA::ArmFault::routeToMonitor
virtual bool routeToMonitor(ThreadContext *tc) const =0
gem5::ArmISA::IllegalInstSetStateFault::IllegalInstSetStateFault
IllegalInstSetStateFault()
Definition: faults.cc:1836
gem5::ArmISA::itstate
Bitfield< 55, 48 > itstate
Definition: types.hh:70
gem5::ArmISA::AbortFault< PrefetchAbort >::source
uint8_t source
Definition: faults.hh:453
gem5::ArmISA::EC_HW_BREAKPOINT
@ EC_HW_BREAKPOINT
Definition: types.hh:332
gem5::ArmISA::MISCREG_HPFAR
@ MISCREG_HPFAR
Definition: misc.hh:291
gem5::ArmISA::MISCREG_ESR_EL1
@ MISCREG_ESR_EL1
Definition: misc.hh:639
gem5::ArmISA::cond
cond
Definition: pcstate.hh:62
gem5::ArmISA::CCREG_V
@ CCREG_V
Definition: cc.hh:51
gem5::ArmISA::MISCREG_VBAR_EL1
@ MISCREG_VBAR_EL1
Definition: misc.hh:736
gem5::ArmISA::ArmFault::longDescFaultSources
static uint8_t longDescFaultSources[NumFaultSources]
Encodings of the fault sources when the long-desc.
Definition: faults.hh:128
gem5::ArmISA::AbortFault
Definition: faults.hh:435
gem5::ArmISA::ArmFault::SAS
@ SAS
Definition: faults.hh:136
gem5::ArmISA::MISCREG_SPSR_HYP
@ MISCREG_SPSR_HYP
Definition: misc.hh:68
gem5::ArmISA::ArmStaticInst::annotateFault
virtual void annotateFault(ArmFault *fault)
Definition: static_inst.hh:543
thread_context.hh
gem5::ArmISA::ArmFault::UnknownTran
@ UnknownTran
Definition: faults.hh:154
gem5::ArmISA::OperatingMode
OperatingMode
Definition: types.hh:272
gem5::ArmISA::ArmFault::OVA
@ OVA
Definition: faults.hh:135
gem5::ArmISA::EC_STACK_PTR_ALIGNMENT
@ EC_STACK_PTR_ALIGNMENT
Definition: types.hh:328
gem5::ArmISA::EC_WATCHPOINT_CURR_EL
@ EC_WATCHPOINT_CURR_EL
Definition: types.hh:340
gem5::ArmISA::SoftwareStepFault::stepped
bool stepped
Definition: faults.hh:663
gem5::Workload::syscall
virtual void syscall(ThreadContext *tc)
Definition: workload.hh:109
gem5::ArmISA::AbortFault< DataAbort >::s1ptw
bool s1ptw
Definition: faults.hh:456
gem5::ArmISA::VirtualFastInterrupt::VirtualFastInterrupt
VirtualFastInterrupt()
Definition: faults.cc:1555
gem5::ArmISA::SecureMonitorTrap::overrideEc
ExceptionClass overrideEc
Definition: faults.hh:395
gem5::ArmISA::EC_DATA_ABORT_CURR_EL
@ EC_DATA_ABORT_CURR_EL
Definition: types.hh:327
gem5::ArmISA::getMPIDR
RegVal getMPIDR(ArmSystem *arm_sys, ThreadContext *tc)
This helper function is returning the value of MPIDR_EL1.
Definition: utility.cc:170
gem5::ArmISA::Interrupt::abortDisable
bool abortDisable(ThreadContext *tc) override
Definition: faults.cc:1501
gem5::ArmISA::ExceptionLevel
ExceptionLevel
Definition: types.hh:264
panic
#define panic(...)
This implements a cprintf based panic() function.
Definition: logging.hh:178
gem5::ArmISA::Watchpoint::ec
ExceptionClass ec(ThreadContext *tc) const override
Definition: faults.cc:1741
gem5::ArmISA::mode
Bitfield< 4, 0 > mode
Definition: misc_types.hh:74
gem5::ArmISA::INT_SEV
@ INT_SEV
Definition: interrupts.hh:64
gem5::ThreadContext::setMiscRegNoEffect
virtual void setMiscRegNoEffect(RegIndex misc_reg, RegVal val)=0
gem5::ArmISA::ArmFault::fiqDisable
virtual bool fiqDisable(ThreadContext *tc)=0
gem5::ArmISA::Watchpoint::write
bool write
Definition: faults.hh:646
gem5::ArmISA::MISCREG_SPSR_UND
@ MISCREG_SPSR_UND
Definition: misc.hh:69

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