gem5  v22.0.0.2
faults.cc
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41 
42 #include "arch/arm/faults.hh"
43 
45 #include "arch/arm/interrupts.hh"
46 #include "arch/arm/isa.hh"
47 #include "arch/arm/self_debug.hh"
48 #include "arch/arm/system.hh"
49 #include "arch/arm/utility.hh"
50 #include "base/compiler.hh"
51 #include "base/trace.hh"
52 #include "cpu/base.hh"
53 #include "cpu/thread_context.hh"
54 #include "debug/Faults.hh"
55 #include "sim/full_system.hh"
56 
57 namespace gem5
58 {
59 
60 namespace ArmISA
61 {
62 
63 const uint32_t HighVecs = 0xFFFF0000;
64 
66  0x01, // AlignmentFault
67  0x04, // InstructionCacheMaintenance
68  0xff, // SynchExtAbtOnTranslTableWalkL0 (INVALID)
69  0x0c, // SynchExtAbtOnTranslTableWalkL1
70  0x0e, // SynchExtAbtOnTranslTableWalkL2
71  0xff, // SynchExtAbtOnTranslTableWalkL3 (INVALID)
72  0xff, // SynchPtyErrOnTranslTableWalkL0 (INVALID)
73  0x1c, // SynchPtyErrOnTranslTableWalkL1
74  0x1e, // SynchPtyErrOnTranslTableWalkL2
75  0xff, // SynchPtyErrOnTranslTableWalkL3 (INVALID)
76  0xff, // TranslationL0 (INVALID)
77  0x05, // TranslationL1
78  0x07, // TranslationL2
79  0xff, // TranslationL3 (INVALID)
80  0xff, // AccessFlagL0 (INVALID)
81  0x03, // AccessFlagL1
82  0x06, // AccessFlagL2
83  0xff, // AccessFlagL3 (INVALID)
84  0xff, // DomainL0 (INVALID)
85  0x09, // DomainL1
86  0x0b, // DomainL2
87  0xff, // DomainL3 (INVALID)
88  0xff, // PermissionL0 (INVALID)
89  0x0d, // PermissionL1
90  0x0f, // PermissionL2
91  0xff, // PermissionL3 (INVALID)
92  0x02, // DebugEvent
93  0x08, // SynchronousExternalAbort
94  0x10, // TLBConflictAbort
95  0x19, // SynchPtyErrOnMemoryAccess
96  0x16, // AsynchronousExternalAbort
97  0x18, // AsynchPtyErrOnMemoryAccess
98  0xff, // AddressSizeL0 (INVALID)
99  0xff, // AddressSizeL1 (INVALID)
100  0xff, // AddressSizeL2 (INVALID)
101  0xff, // AddressSizeL3 (INVALID)
102  0x40, // PrefetchTLBMiss
103  0x80 // PrefetchUncacheable
104 };
105 
106 static_assert(sizeof(ArmFault::shortDescFaultSources) ==
108  "Invalid size of ArmFault::shortDescFaultSources[]");
109 
110 uint8_t ArmFault::longDescFaultSources[] = {
111  0x21, // AlignmentFault
112  0xff, // InstructionCacheMaintenance (INVALID)
113  0xff, // SynchExtAbtOnTranslTableWalkL0 (INVALID)
114  0x15, // SynchExtAbtOnTranslTableWalkL1
115  0x16, // SynchExtAbtOnTranslTableWalkL2
116  0x17, // SynchExtAbtOnTranslTableWalkL3
117  0xff, // SynchPtyErrOnTranslTableWalkL0 (INVALID)
118  0x1d, // SynchPtyErrOnTranslTableWalkL1
119  0x1e, // SynchPtyErrOnTranslTableWalkL2
120  0x1f, // SynchPtyErrOnTranslTableWalkL3
121  0xff, // TranslationL0 (INVALID)
122  0x05, // TranslationL1
123  0x06, // TranslationL2
124  0x07, // TranslationL3
125  0xff, // AccessFlagL0 (INVALID)
126  0x09, // AccessFlagL1
127  0x0a, // AccessFlagL2
128  0x0b, // AccessFlagL3
129  0xff, // DomainL0 (INVALID)
130  0x3d, // DomainL1
131  0x3e, // DomainL2
132  0xff, // DomainL3 (RESERVED)
133  0xff, // PermissionL0 (INVALID)
134  0x0d, // PermissionL1
135  0x0e, // PermissionL2
136  0x0f, // PermissionL3
137  0x22, // DebugEvent
138  0x10, // SynchronousExternalAbort
139  0x30, // TLBConflictAbort
140  0x18, // SynchPtyErrOnMemoryAccess
141  0x11, // AsynchronousExternalAbort
142  0x19, // AsynchPtyErrOnMemoryAccess
143  0xff, // AddressSizeL0 (INVALID)
144  0xff, // AddressSizeL1 (INVALID)
145  0xff, // AddressSizeL2 (INVALID)
146  0xff, // AddressSizeL3 (INVALID)
147  0x40, // PrefetchTLBMiss
148  0x80 // PrefetchUncacheable
149 };
150 
151 static_assert(sizeof(ArmFault::longDescFaultSources) ==
153  "Invalid size of ArmFault::longDescFaultSources[]");
154 
155 uint8_t ArmFault::aarch64FaultSources[] = {
156  0x21, // AlignmentFault
157  0xff, // InstructionCacheMaintenance (INVALID)
158  0x14, // SynchExtAbtOnTranslTableWalkL0
159  0x15, // SynchExtAbtOnTranslTableWalkL1
160  0x16, // SynchExtAbtOnTranslTableWalkL2
161  0x17, // SynchExtAbtOnTranslTableWalkL3
162  0x1c, // SynchPtyErrOnTranslTableWalkL0
163  0x1d, // SynchPtyErrOnTranslTableWalkL1
164  0x1e, // SynchPtyErrOnTranslTableWalkL2
165  0x1f, // SynchPtyErrOnTranslTableWalkL3
166  0x04, // TranslationL0
167  0x05, // TranslationL1
168  0x06, // TranslationL2
169  0x07, // TranslationL3
170  0x08, // AccessFlagL0
171  0x09, // AccessFlagL1
172  0x0a, // AccessFlagL2
173  0x0b, // AccessFlagL3
174  // @todo: Section & Page Domain Fault in AArch64?
175  0xff, // DomainL0 (INVALID)
176  0xff, // DomainL1 (INVALID)
177  0xff, // DomainL2 (INVALID)
178  0xff, // DomainL3 (INVALID)
179  0x0c, // PermissionL0
180  0x0d, // PermissionL1
181  0x0e, // PermissionL2
182  0x0f, // PermissionL3
183  0x22, // DebugEvent
184  0x10, // SynchronousExternalAbort
185  0x30, // TLBConflictAbort
186  0x18, // SynchPtyErrOnMemoryAccess
187  0xff, // AsynchronousExternalAbort (INVALID)
188  0xff, // AsynchPtyErrOnMemoryAccess (INVALID)
189  0x00, // AddressSizeL0
190  0x01, // AddressSizeL1
191  0x02, // AddressSizeL2
192  0x03, // AddressSizeL3
193  0x40, // PrefetchTLBMiss
194  0x80 // PrefetchUncacheable
195 };
196 
197 static_assert(sizeof(ArmFault::aarch64FaultSources) ==
199  "Invalid size of ArmFault::aarch64FaultSources[]");
200 
201 // Fields: name, offset, cur{ELT,ELH}Offset, lowerEL{64,32}Offset, next mode,
202 // {ARM, Thumb, ARM_ELR, Thumb_ELR} PC offset, hyp trap,
203 // {A, F} disable, class, stat
205  // Some dummy values (the reset vector has an IMPLEMENTATION DEFINED
206  // location in AArch64)
207  "Reset", 0x000, 0x000, 0x000, 0x000, 0x000, MODE_SVC,
208  0, 0, 0, 0, false, true, true, EC_UNKNOWN
209 );
211  "Undefined Instruction", 0x004, 0x000, 0x200, 0x400, 0x600, MODE_UNDEFINED,
212  4, 2, 0, 0, true, false, false, EC_UNKNOWN
213 );
215  "Supervisor Call", 0x008, 0x000, 0x200, 0x400, 0x600, MODE_SVC,
216  4, 2, 4, 2, true, false, false, EC_SVC_TO_HYP
217 );
219  "Secure Monitor Call", 0x008, 0x000, 0x200, 0x400, 0x600, MODE_MON,
220  4, 4, 4, 4, false, true, true, EC_SMC_TO_HYP
221 );
223  "Hypervisor Call", 0x008, 0x000, 0x200, 0x400, 0x600, MODE_HYP,
224  4, 4, 4, 4, true, false, false, EC_HVC
225 );
227  "Prefetch Abort", 0x00C, 0x000, 0x200, 0x400, 0x600, MODE_ABORT,
228  4, 4, 0, 0, true, true, false, EC_PREFETCH_ABORT_TO_HYP
229 );
231  "Data Abort", 0x010, 0x000, 0x200, 0x400, 0x600, MODE_ABORT,
232  8, 8, 0, 0, true, true, false, EC_DATA_ABORT_TO_HYP
233 );
235  "Virtual Data Abort", 0x010, 0x000, 0x200, 0x400, 0x600, MODE_ABORT,
236  8, 8, 0, 0, true, true, false, EC_INVALID
237 );
239  // @todo: double check these values
240  "Hypervisor Trap", 0x014, 0x000, 0x200, 0x400, 0x600, MODE_HYP,
241  0, 0, 0, 0, false, false, false, EC_UNKNOWN
242 );
244  "Secure Monitor Trap", 0x004, 0x000, 0x200, 0x400, 0x600, MODE_MON,
245  4, 2, 0, 0, false, false, false, EC_UNKNOWN
246 );
248  "IRQ", 0x018, 0x080, 0x280, 0x480, 0x680, MODE_IRQ,
249  4, 4, 0, 0, false, true, false, EC_UNKNOWN
250 );
252  "Virtual IRQ", 0x018, 0x080, 0x280, 0x480, 0x680, MODE_IRQ,
253  4, 4, 0, 0, false, true, false, EC_INVALID
254 );
256  "FIQ", 0x01C, 0x100, 0x300, 0x500, 0x700, MODE_FIQ,
257  4, 4, 0, 0, false, true, true, EC_UNKNOWN
258 );
260  "Virtual FIQ", 0x01C, 0x100, 0x300, 0x500, 0x700, MODE_FIQ,
261  4, 4, 0, 0, false, true, true, EC_INVALID
262 );
264  "Illegal Inst Set State Fault", 0x004, 0x000, 0x200, 0x400, 0x600, MODE_UNDEFINED,
265  4, 2, 0, 0, true, false, false, EC_ILLEGAL_INST
266 );
268  // Some dummy values (SupervisorTrap is AArch64-only)
269  "Supervisor Trap", 0x014, 0x000, 0x200, 0x400, 0x600, MODE_SVC,
270  0, 0, 0, 0, false, false, false, EC_UNKNOWN
271 );
273  // Some dummy values (PCAlignmentFault is AArch64-only)
274  "PC Alignment Fault", 0x000, 0x000, 0x200, 0x400, 0x600, MODE_SVC,
275  0, 0, 0, 0, true, false, false, EC_PC_ALIGNMENT
276 );
278  // Some dummy values (SPAlignmentFault is AArch64-only)
279  "SP Alignment Fault", 0x000, 0x000, 0x200, 0x400, 0x600, MODE_SVC,
280  0, 0, 0, 0, true, false, false, EC_STACK_PTR_ALIGNMENT
281 );
283  // Some dummy values (SError is AArch64-only)
284  "SError", 0x000, 0x180, 0x380, 0x580, 0x780, MODE_SVC,
285  0, 0, 0, 0, false, true, true, EC_SERROR
286 );
288  // Some dummy values (SoftwareBreakpoint is AArch64-only)
289  "Software Breakpoint", 0x000, 0x000, 0x200, 0x400, 0x600, MODE_SVC,
290  0, 0, 0, 0, true, false, false, EC_SOFTWARE_BREAKPOINT
291 );
293  "Hardware Breakpoint", 0x000, 0x000, 0x200, 0x400, 0x600, MODE_SVC,
294  0, 0, 0, 0, true, false, false, EC_HW_BREAKPOINT
295 );
297  "Watchpoint", 0x000, 0x000, 0x200, 0x400, 0x600, MODE_SVC,
298  0, 0, 0, 0, true, false, false, EC_WATCHPOINT
299 );
301  "SoftwareStep", 0x000, 0x000, 0x200, 0x400, 0x600, MODE_SVC,
302  0, 0, 0, 0, true, false, false, EC_SOFTWARE_STEP
303 );
305  // Some dummy values
306  "ArmSev Flush", 0x000, 0x000, 0x000, 0x000, 0x000, MODE_SVC,
307  0, 0, 0, 0, false, true, true, EC_UNKNOWN
308 );
309 
310 Addr
312 {
313  Addr base;
314 
315  // Check for invalid modes
316  CPSR cpsr = tc->readMiscRegNoEffect(MISCREG_CPSR);
317  assert(ArmSystem::haveEL(tc, EL3) || cpsr.mode != MODE_MON);
318  assert(ArmSystem::haveEL(tc, EL2) || cpsr.mode != MODE_HYP);
319 
320  switch (cpsr.mode)
321  {
322  case MODE_MON:
324  break;
325  case MODE_HYP:
327  break;
328  default:
329  SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR);
330  if (sctlr.v) {
331  base = HighVecs;
332  } else {
333  base = ArmSystem::haveEL(tc, EL3) ?
334  tc->readMiscReg(MISCREG_VBAR) : 0;
335  }
336  break;
337  }
338 
339  return base + offset(tc);
340 }
341 
342 Addr
344 {
345  Addr vbar;
346  switch (toEL) {
347  case EL3:
348  assert(ArmSystem::haveEL(tc, EL3));
349  vbar = tc->readMiscReg(MISCREG_VBAR_EL3);
350  break;
351  case EL2:
352  assert(ArmSystem::haveEL(tc, EL2));
353  vbar = tc->readMiscReg(MISCREG_VBAR_EL2);
354  break;
355  case EL1:
356  vbar = tc->readMiscReg(MISCREG_VBAR_EL1);
357  break;
358  default:
359  panic("Invalid target exception level");
360  break;
361  }
362  return vbar + offset64(tc);
363 }
364 
367 {
368  switch (toEL) {
369  case EL1:
370  return MISCREG_ESR_EL1;
371  case EL2:
372  return MISCREG_ESR_EL2;
373  case EL3:
374  return MISCREG_ESR_EL3;
375  default:
376  panic("Invalid exception level");
377  break;
378  }
379 }
380 
383 {
384  switch (toEL) {
385  case EL1:
386  return MISCREG_FAR_EL1;
387  case EL2:
388  return MISCREG_FAR_EL2;
389  case EL3:
390  return MISCREG_FAR_EL3;
391  default:
392  panic("Invalid exception level");
393  break;
394  }
395 }
396 
397 void
399 {
400  ESR esr = 0;
401  uint32_t exc_class = (uint32_t) ec(tc);
402  uint32_t iss_val = iss();
403 
404  assert(!from64 || ArmSystem::highestELIs64(tc));
405 
406  esr.ec = exc_class;
407  esr.il = il(tc);
408 
409  // Condition code valid for EC[5:4] nonzero
410  if (!from64 && ((bits(exc_class, 5, 4) == 0) &&
411  (bits(exc_class, 3, 0) != 0))) {
412 
413  if (!machInst.thumb) {
414  ConditionCode cond_code = (ConditionCode) (uint32_t) machInst.condCode;
415  // If its on unconditional instruction report with a cond code of
416  // 0xE, ie the unconditional code
417  esr.cond_iss.cv = 1;
418  esr.cond_iss.cond = (cond_code == COND_UC) ? COND_AL : cond_code;
419  }
420  esr.cond_iss.iss = bits(iss_val, 19, 0);
421  } else {
422  esr.iss = iss_val;
423  }
424  tc->setMiscReg(syndrome_reg, esr);
425 }
426 
427 void
429 {
430  CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
431 
432  // Determine source exception level and mode
433  fromMode = (OperatingMode) (uint8_t) cpsr.mode;
435  if (opModeIs64(fromMode))
436  from64 = true;
437 
438  // Determine target exception level (aarch64) or target execution
439  // mode (aarch32).
440  if (ArmSystem::haveEL(tc, EL3) && routeToMonitor(tc)) {
441  toMode = MODE_MON;
442  toEL = EL3;
443  } else if (ArmSystem::haveEL(tc, EL2) && routeToHyp(tc)) {
444  toMode = MODE_HYP;
445  toEL = EL2;
446  hypRouted = true;
447  } else {
448  toMode = nextMode();
450  }
451 
452  if (fromEL > toEL)
453  toEL = fromEL;
454 
455  // Check for Set Priviledge Access Never, if PAN is supported
456  if (HaveExt(tc, ArmExtension::FEAT_PAN)) {
457  if (toEL == EL1) {
458  const SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR_EL1);
459  span = !sctlr.span;
460  }
461 
462  const HCR hcr = tc->readMiscRegNoEffect(MISCREG_HCR_EL2);
463  if (toEL == EL2 && hcr.e2h && hcr.tge) {
464  const SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR_EL2);
465  span = !sctlr.span;
466  }
467  }
468 
469  to64 = ELIs64(tc, toEL);
470 
471  // The fault specific informations have been updated; it is
472  // now possible to use them inside the fault.
473  faultUpdated = true;
474 }
475 
476 void
478 {
479  // Update fault state informations, like the starting mode (aarch32)
480  // or EL (aarch64) and the ending mode or EL.
481  // From the update function we are also evaluating if the fault must
482  // be handled in AArch64 mode (to64).
483  update(tc);
484 
485  if (from64 != to64) {
486  // Switching modes, sync up versions of the vector register file.
487  if (from64) {
488  syncVecRegsToElems(tc);
489  } else {
490  syncVecElemsToRegs(tc);
491  }
492  }
493 
494  if (to64) {
495  // Invoke exception handler in AArch64 state
496  invoke64(tc, inst);
497  } else {
498  // Invoke exception handler in AArch32 state
499  invoke32(tc, inst);
500  }
501 }
502 
503 void
505 {
506  if (vectorCatch(tc, inst))
507  return;
508 
509  // ARMv7 (ARM ARM issue C B1.9)
510  bool have_security = ArmSystem::haveEL(tc, EL3);
511 
512  FaultBase::invoke(tc);
513  if (!FullSystem)
514  return;
515 
516  SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR);
517  SCR scr = tc->readMiscReg(MISCREG_SCR);
518  CPSR saved_cpsr = tc->readMiscReg(MISCREG_CPSR);
519  saved_cpsr.nz = tc->getReg(cc_reg::Nz);
520  saved_cpsr.c = tc->getReg(cc_reg::C);
521  saved_cpsr.v = tc->getReg(cc_reg::V);
522  saved_cpsr.ge = tc->getReg(cc_reg::Ge);
523 
524  [[maybe_unused]] Addr cur_pc = tc->pcState().as<PCState>().pc();
525  ITSTATE it = tc->pcState().as<PCState>().itstate();
526  saved_cpsr.it2 = it.top6;
527  saved_cpsr.it1 = it.bottom2;
528 
529  // if we have a valid instruction then use it to annotate this fault with
530  // extra information. This is used to generate the correct fault syndrome
531  // information
532  [[maybe_unused]] ArmStaticInst *arm_inst = instrAnnotate(inst);
533 
534  // Ensure Secure state if initially in Monitor mode
535  if (have_security && saved_cpsr.mode == MODE_MON) {
536  SCR scr = tc->readMiscRegNoEffect(MISCREG_SCR);
537  if (scr.ns) {
538  scr.ns = 0;
540  }
541  }
542 
543  CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
544  cpsr.mode = toMode;
545 
546  // some bits are set differently if we have been routed to hyp mode
547  if (cpsr.mode == MODE_HYP) {
548  SCTLR hsctlr = tc->readMiscReg(MISCREG_HSCTLR);
549  cpsr.t = hsctlr.te;
550  cpsr.e = hsctlr.ee;
551  if (!scr.ea) {cpsr.a = 1;}
552  if (!scr.fiq) {cpsr.f = 1;}
553  if (!scr.irq) {cpsr.i = 1;}
554  } else if (cpsr.mode == MODE_MON) {
555  // Special case handling when entering monitor mode
556  cpsr.t = sctlr.te;
557  cpsr.e = sctlr.ee;
558  cpsr.a = 1;
559  cpsr.f = 1;
560  cpsr.i = 1;
561  } else {
562  cpsr.t = sctlr.te;
563  cpsr.e = sctlr.ee;
564 
565  // The *Disable functions are virtual and different per fault
566  cpsr.a = cpsr.a | abortDisable(tc);
567  cpsr.f = cpsr.f | fiqDisable(tc);
568  cpsr.i = 1;
569  }
570  cpsr.it1 = cpsr.it2 = 0;
571  cpsr.j = 0;
572  cpsr.pan = span ? 1 : saved_cpsr.pan;
573  tc->setMiscReg(MISCREG_CPSR, cpsr);
574 
575  // Make sure mailbox sets to one always
577 
578  // Clear the exclusive monitor
580 
581  if (cpsr.mode == MODE_HYP) {
582  tc->setMiscReg(MISCREG_ELR_HYP, cur_pc +
583  (saved_cpsr.t ? thumbPcOffset(true) : armPcOffset(true)));
584  } else {
585  tc->setReg(int_reg::Lr, cur_pc +
586  (saved_cpsr.t ? thumbPcOffset(false) : armPcOffset(false)));
587  }
588 
589  switch (cpsr.mode) {
590  case MODE_FIQ:
591  tc->setMiscReg(MISCREG_SPSR_FIQ, saved_cpsr);
592  break;
593  case MODE_IRQ:
594  tc->setMiscReg(MISCREG_SPSR_IRQ, saved_cpsr);
595  break;
596  case MODE_SVC:
597  tc->setMiscReg(MISCREG_SPSR_SVC, saved_cpsr);
598  break;
599  case MODE_MON:
600  assert(have_security);
601  tc->setMiscReg(MISCREG_SPSR_MON, saved_cpsr);
602  break;
603  case MODE_ABORT:
604  tc->setMiscReg(MISCREG_SPSR_ABT, saved_cpsr);
605  break;
606  case MODE_UNDEFINED:
607  tc->setMiscReg(MISCREG_SPSR_UND, saved_cpsr);
608  if (ec(tc) != EC_UNKNOWN)
610  break;
611  case MODE_HYP:
612  assert(ArmSystem::haveEL(tc, EL2));
613  tc->setMiscReg(MISCREG_SPSR_HYP, saved_cpsr);
615  break;
616  default:
617  panic("unknown Mode\n");
618  }
619 
620  Addr new_pc = getVector(tc);
621  DPRINTF(Faults, "Invoking Fault:%s cpsr:%#x PC:%#x lr:%#x newVec: %#x "
622  "%s\n", name(), cpsr, cur_pc, tc->getReg(int_reg::Lr),
623  new_pc, arm_inst ? csprintf("inst: %#x", arm_inst->encoding()) :
624  std::string());
625  PCState pc(new_pc);
626  pc.thumb(cpsr.t);
627  pc.nextThumb(pc.thumb());
628  pc.jazelle(cpsr.j);
629  pc.nextJazelle(pc.jazelle());
630  pc.aarch64(!cpsr.width);
631  pc.nextAArch64(!cpsr.width);
632  pc.illegalExec(false);
633  tc->pcState(pc);
634 }
635 
636 void
638 {
639  // Determine actual misc. register indices for ELR_ELx and SPSR_ELx
640  MiscRegIndex elr_idx, spsr_idx;
641  switch (toEL) {
642  case EL1:
643  elr_idx = MISCREG_ELR_EL1;
644  spsr_idx = MISCREG_SPSR_EL1;
645  break;
646  case EL2:
647  assert(ArmSystem::haveEL(tc, EL2));
648  elr_idx = MISCREG_ELR_EL2;
649  spsr_idx = MISCREG_SPSR_EL2;
650  break;
651  case EL3:
652  assert(ArmSystem::haveEL(tc, EL3));
653  elr_idx = MISCREG_ELR_EL3;
654  spsr_idx = MISCREG_SPSR_EL3;
655  break;
656  default:
657  panic("Invalid target exception level");
658  break;
659  }
660 
661  // Save process state into SPSR_ELx
662  CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
663  CPSR spsr = cpsr;
664  spsr.nz = tc->getReg(cc_reg::Nz);
665  spsr.c = tc->getReg(cc_reg::C);
666  spsr.v = tc->getReg(cc_reg::V);
667  spsr.ss = isResetSPSR() ? 0: cpsr.ss;
668  if (from64) {
669  // Force some bitfields to 0
670  spsr.q = 0;
671  spsr.it1 = 0;
672  spsr.j = 0;
673  spsr.ge = 0;
674  spsr.it2 = 0;
675  spsr.t = 0;
676  } else {
677  spsr.ge = tc->getReg(cc_reg::Ge);
678  ITSTATE it = tc->pcState().as<PCState>().itstate();
679  spsr.it2 = it.top6;
680  spsr.it1 = it.bottom2;
681  spsr.uao = 0;
682  }
683  tc->setMiscReg(spsr_idx, spsr);
684 
685  // Save preferred return address into ELR_ELx
686  Addr curr_pc = tc->pcState().instAddr();
687  Addr ret_addr = curr_pc;
688  if (from64)
689  ret_addr += armPcElrOffset();
690  else
691  ret_addr += spsr.t ? thumbPcElrOffset() : armPcElrOffset();
692  tc->setMiscReg(elr_idx, ret_addr);
693 
694  Addr vec_address = getVector64(tc);
695 
696  // Update process state
697  OperatingMode64 mode = 0;
698  mode.spX = 1;
699  mode.el = toEL;
700  mode.width = 0;
701  cpsr.mode = mode;
702  cpsr.daif = 0xf;
703  cpsr.il = 0;
704  cpsr.ss = 0;
705  cpsr.pan = span ? 1 : spsr.pan;
706  cpsr.uao = 0;
707  tc->setMiscReg(MISCREG_CPSR, cpsr);
708 
709  // If we have a valid instruction then use it to annotate this fault with
710  // extra information. This is used to generate the correct fault syndrome
711  // information
712  [[maybe_unused]] ArmStaticInst *arm_inst = instrAnnotate(inst);
713 
714  // Set PC to start of exception handler
715  Addr new_pc = purifyTaggedAddr(vec_address, tc, toEL, true);
716  DPRINTF(Faults, "Invoking Fault (AArch64 target EL):%s cpsr:%#x PC:%#x "
717  "elr:%#x newVec: %#x %s\n", name(), cpsr, curr_pc, ret_addr,
718  new_pc, arm_inst ? csprintf("inst: %#x", arm_inst->encoding()) :
719  std::string());
720  PCState pc(new_pc);
721  pc.aarch64(!cpsr.width);
722  pc.nextAArch64(!cpsr.width);
723  pc.illegalExec(false);
724  pc.stepped(false);
725  tc->pcState(pc);
726 
727  // Save exception syndrome
728  if ((nextMode() != MODE_IRQ) && (nextMode() != MODE_FIQ))
730 }
731 
732 bool
734 {
736  VectorCatch* vc = sd->getVectorCatch(tc);
737  if (!vc->isVCMatch()) {
738  Fault fault = sd->testVectorCatch(tc, 0x0, this);
739  if (fault != NoFault)
740  fault->invoke(tc, inst);
741  return true;
742  }
743  return false;
744 }
745 
748 {
749  if (inst) {
750  auto arm_inst = static_cast<ArmStaticInst *>(inst.get());
751  arm_inst->annotateFault(this);
752  return arm_inst;
753  } else {
754  return nullptr;
755  }
756 }
757 
758 Addr
760 {
761  Addr base;
762 
763  // Check for invalid modes
764  [[maybe_unused]] CPSR cpsr = tc->readMiscRegNoEffect(MISCREG_CPSR);
765  assert(ArmSystem::haveEL(tc, EL3) || cpsr.mode != MODE_MON);
766  assert(ArmSystem::haveEL(tc, EL2) || cpsr.mode != MODE_HYP);
767 
768  // RVBAR is aliased (implemented as) MVBAR in gem5, since the two
769  // are mutually exclusive; there is no need to check here for
770  // which register to use since they hold the same value
772 
773  return base + offset(tc);
774 }
775 
776 void
778 {
779  if (FullSystem) {
780  tc->getCpuPtr()->clearInterrupts(tc->threadId());
781  tc->clearArchRegs();
782  }
783  if (!ArmSystem::highestELIs64(tc)) {
784  ArmFault::invoke(tc, inst);
786  getMPIDR(dynamic_cast<ArmSystem*>(tc->getSystemPtr()), tc));
787 
788  // Unless we have SMC code to get us there, boot in HYP!
789  if (ArmSystem::haveEL(tc, EL2) &&
790  !ArmSystem::haveEL(tc, EL3)) {
791  CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
792  cpsr.mode = MODE_HYP;
793  tc->setMiscReg(MISCREG_CPSR, cpsr);
794  }
795  } else {
796  // Advance the PC to the IMPLEMENTATION DEFINED reset value
798  pc.aarch64(true);
799  pc.nextAArch64(true);
800  tc->pcState(pc);
801  }
802 }
803 
804 void
806 {
807  if (FullSystem) {
808  ArmFault::invoke(tc, inst);
809  return;
810  }
811 
812  // If the mnemonic isn't defined this has to be an unknown instruction.
813  assert(unknown || mnemonic != NULL);
814  auto arm_inst = static_cast<ArmStaticInst *>(inst.get());
815  if (disabled) {
816  panic("Attempted to execute disabled instruction "
817  "'%s' (inst 0x%08x)", mnemonic, arm_inst->encoding());
818  } else if (unknown) {
819  panic("Attempted to execute unknown instruction (inst 0x%08x)",
820  arm_inst->encoding());
821  } else {
822  panic("Attempted to execute unimplemented instruction "
823  "'%s' (inst 0x%08x)", mnemonic, arm_inst->encoding());
824  }
825 }
826 
827 bool
829 {
830  HCR hcr = tc->readMiscRegNoEffect(MISCREG_HCR);
831  return fromEL == EL2 ||
832  (EL2Enabled(tc) && (fromEL == EL0) && hcr.tge);
833 }
834 
835 uint32_t
837 {
838 
839  // If UndefinedInstruction is routed to hypervisor, iss field is 0.
840  if (hypRouted) {
841  return 0;
842  }
843 
844  if (overrideEc == EC_INVALID)
845  return issRaw;
846 
847  uint32_t new_iss = 0;
848  uint32_t op0, op1, op2, CRn, CRm, Rt, dir;
849 
850  dir = bits(machInst, 21, 21);
851  op0 = bits(machInst, 20, 19);
852  op1 = bits(machInst, 18, 16);
853  CRn = bits(machInst, 15, 12);
854  CRm = bits(machInst, 11, 8);
855  op2 = bits(machInst, 7, 5);
856  Rt = bits(machInst, 4, 0);
857 
858  new_iss = op0 << 20 | op2 << 17 | op1 << 14 | CRn << 10 |
859  Rt << 5 | CRm << 1 | dir;
860 
861  return new_iss;
862 }
863 
864 void
866 {
867  if (FullSystem) {
868  ArmFault::invoke(tc, inst);
869  return;
870  }
871 
872  // Advance the PC since that won't happen automatically.
873  PCState pc = tc->pcState().as<PCState>();
874  assert(inst);
875  inst->advancePC(pc);
876  tc->pcState(pc);
877 
878  // As of now, there isn't a 32 bit thumb version of this instruction.
879  assert(!machInst.bigThumb);
880  tc->getSystemPtr()->workload->syscall(tc);
881 }
882 
883 bool
885 {
886  HCR hcr = tc->readMiscRegNoEffect(MISCREG_HCR);
887  return fromEL == EL2 ||
888  (EL2Enabled(tc) && fromEL == EL0 && hcr.tge);
889 }
890 
893 {
894  return (overrideEc != EC_INVALID) ? overrideEc :
895  (from64 ? EC_SVC_64 : vals.ec);
896 }
897 
898 uint32_t
900 {
901  // Even if we have a 24 bit imm from an arm32 instruction then we only use
902  // the bottom 16 bits for the ISS value (it doesn't hurt for AArch64 SVC).
903  return issRaw & 0xFFFF;
904 }
905 
906 uint32_t
908 {
909  if (from64)
910  return bits(machInst, 20, 5);
911  return 0;
912 }
913 
916 {
917  // If UndefinedInstruction is routed to hypervisor,
918  // HSR.EC field is 0.
919  if (hypRouted)
920  return EC_UNKNOWN;
921  else
922  return (overrideEc != EC_INVALID) ? overrideEc : vals.ec;
923 }
924 
925 
926 HypervisorCall::HypervisorCall(ExtMachInst mach_inst, uint32_t _imm) :
927  ArmFaultVals<HypervisorCall>(mach_inst, _imm)
928 {
929  bStep = true;
930 }
931 
932 bool
934 {
935  return from64 && fromEL == EL3;
936 }
937 
938 bool
940 {
941  return !from64 || fromEL != EL3;
942 }
943 
946 {
947  return from64 ? EC_HVC_64 : vals.ec;
948 }
949 
952 {
953  return (overrideEc != EC_INVALID) ? overrideEc : vals.ec;
954 }
955 
956 template<class T>
959 {
960  bool isHypTrap = false;
961 
962  // Normally we just use the exception vector from the table at the top if
963  // this file, however if this exception has caused a transition to hype
964  // mode, and its an exception type that would only do this if it has been
965  // trapped then we use the hyp trap vector instead of the normal vector
966  if (vals.hypTrappable) {
967  CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
968  if (cpsr.mode == MODE_HYP) {
969  CPSR spsr = tc->readMiscReg(MISCREG_SPSR_HYP);
970  isHypTrap = spsr.mode != MODE_HYP;
971  }
972  }
973  return isHypTrap ? 0x14 : vals.offset;
974 }
975 
976 template<class T>
979 {
980  if (toEL == fromEL) {
981  if (opModeIsT(fromMode))
982  return vals.currELTOffset;
983  return vals.currELHOffset;
984  } else {
985  bool lower_32 = false;
986  if (toEL == EL3) {
987  if (EL2Enabled(tc))
988  lower_32 = ELIs32(tc, EL2);
989  else
990  lower_32 = ELIs32(tc, EL1);
991  } else if (ELIsInHost(tc, fromEL) && fromEL == EL0 && toEL == EL2) {
992  lower_32 = ELIs32(tc, EL0);
993  } else {
994  lower_32 = ELIs32(tc, static_cast<ExceptionLevel>(toEL - 1));
995  }
996 
997  if (lower_32)
998  return vals.lowerEL32Offset;
999  return vals.lowerEL64Offset;
1000  }
1001 }
1002 
1003 // void
1004 // SupervisorCall::setSyndrome64(ThreadContext *tc, MiscRegIndex esr_idx)
1005 // {
1006 // ESR esr = 0;
1007 // esr.ec = machInst.aarch64 ? SvcAArch64 : SvcAArch32;
1008 // esr.il = !machInst.thumb;
1009 // if (machInst.aarch64)
1010 // esr.imm16 = bits(machInst.instBits, 20, 5);
1011 // else if (machInst.thumb)
1012 // esr.imm16 = bits(machInst.instBits, 7, 0);
1013 // else
1014 // esr.imm16 = bits(machInst.instBits, 15, 0);
1015 // tc->setMiscReg(esr_idx, esr);
1016 // }
1017 
1018 void
1020 {
1021  if (FullSystem) {
1022  ArmFault::invoke(tc, inst);
1023  return;
1024  }
1025 }
1026 
1029 {
1030  return (from64 ? EC_SMC_64 : vals.ec);
1031 }
1032 
1033 bool
1035 {
1036  HCR hcr = tc->readMiscRegNoEffect(MISCREG_HCR_EL2);
1037  return EL2Enabled(tc) && currEL(tc) <= EL1 && hcr.tge;
1038 }
1039 
1040 uint32_t
1042 {
1043  // If SupervisorTrap is routed to hypervisor, iss field is 0.
1044  if (hypRouted) {
1045  return 0;
1046  }
1047  return issRaw;
1048 }
1049 
1052 {
1053  if (hypRouted)
1054  return EC_UNKNOWN;
1055  else
1056  return (overrideEc != EC_INVALID) ? overrideEc : vals.ec;
1057 }
1058 
1061 {
1062  return (overrideEc != EC_INVALID) ? overrideEc :
1063  (from64 ? EC_SMC_64 : vals.ec);
1064 }
1065 
1066 template<class T>
1067 void
1069 {
1070  if (tranMethod == ArmFault::UnknownTran) {
1071  tranMethod = longDescFormatInUse(tc) ? ArmFault::LpaeTran
1073 
1074  if ((tranMethod == ArmFault::VmsaTran) && this->routeToMonitor(tc)) {
1075  // See ARM ARM B3-1416
1076  bool override_LPAE = false;
1077  TTBCR ttbcr_s = tc->readMiscReg(MISCREG_TTBCR_S);
1078  [[maybe_unused]] TTBCR ttbcr_ns =
1080  if (ttbcr_s.eae) {
1081  override_LPAE = true;
1082  } else {
1083  // Unimplemented code option, not seen in testing. May need
1084  // extension according to the manual exceprt above.
1085  DPRINTF(Faults, "Warning: Incomplete translation method "
1086  "override detected.\n");
1087  }
1088  if (override_LPAE)
1089  tranMethod = ArmFault::LpaeTran;
1090  }
1091  }
1092 
1093  if (source == ArmFault::AsynchronousExternalAbort) {
1094  tc->getCpuPtr()->clearInterrupt(tc->threadId(), INT_ABT, 0);
1095  }
1096  // Get effective fault source encoding
1097  CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
1098 
1099  // source must be determined BEFORE invoking generic routines which will
1100  // try to set hsr etc. and are based upon source!
1101  ArmFaultVals<T>::invoke(tc, inst);
1102 
1103  if (!this->to64) { // AArch32
1104  FSR fsr = getFsr(tc);
1105  if (cpsr.mode == MODE_HYP) {
1106  tc->setMiscReg(T::HFarIndex, faultAddr);
1107  } else if (stage2) {
1108  tc->setMiscReg(MISCREG_HPFAR, (faultAddr >> 8) & ~0xf);
1109  tc->setMiscReg(T::HFarIndex, OVAddr);
1110  } else if (debugType > ArmFault::NODEBUG) {
1111  DBGDS32 Rext = tc->readMiscReg(MISCREG_DBGDSCRext);
1112  tc->setMiscReg(T::FarIndex, faultAddr);
1113  if (debugType == ArmFault::BRKPOINT){
1114  Rext.moe = 0x1;
1115  } else if (debugType == ArmFault::VECTORCATCH){
1116  Rext.moe = 0x5;
1117  } else if (debugType > ArmFault::VECTORCATCH) {
1118  Rext.moe = 0xa;
1119  fsr.cm = (debugType == ArmFault::WPOINT_CM)? 1 : 0;
1120  }
1121 
1122  tc->setMiscReg(T::FsrIndex, fsr);
1123  tc->setMiscReg(MISCREG_DBGDSCRext, Rext);
1124 
1125  } else {
1126  tc->setMiscReg(T::FsrIndex, fsr);
1127  tc->setMiscReg(T::FarIndex, faultAddr);
1128  }
1129  DPRINTF(Faults, "Abort Fault source=%#x fsr=%#x faultAddr=%#x "\
1130  "tranMethod=%#x\n", source, fsr, faultAddr, tranMethod);
1131  } else { // AArch64
1132  // Set the FAR register. Nothing else to do if we are in AArch64 state
1133  // because the syndrome register has already been set inside invoke64()
1134  if (stage2) {
1135  // stage 2 fault, set HPFAR_EL2 to the faulting IPA
1136  // and FAR_EL2 to the Original VA
1138  tc->setMiscReg(MISCREG_HPFAR_EL2, bits(faultAddr, 47, 12) << 4);
1139 
1140  DPRINTF(Faults, "Abort Fault (Stage 2) VA: 0x%x IPA: 0x%x\n",
1141  OVAddr, faultAddr);
1142  } else {
1143  tc->setMiscReg(AbortFault<T>::getFaultAddrReg64(), faultAddr);
1144  }
1145  }
1146 }
1147 
1148 template<class T>
1149 void
1151 {
1152  srcEncoded = getFaultStatusCode(tc);
1153  if (srcEncoded == ArmFault::FaultSourceInvalid) {
1154  panic("Invalid fault source\n");
1155  }
1156  ArmFault::setSyndrome(tc, syndrome_reg);
1157 }
1158 
1159 template<class T>
1160 uint8_t
1162 {
1163 
1164  panic_if(!this->faultUpdated,
1165  "Trying to use un-updated ArmFault internal variables\n");
1166 
1167  uint8_t fsc = 0;
1168 
1169  if (!this->to64) {
1170  // AArch32
1171  assert(tranMethod != ArmFault::UnknownTran);
1172  if (tranMethod == ArmFault::LpaeTran) {
1173  fsc = ArmFault::longDescFaultSources[source];
1174  } else {
1175  fsc = ArmFault::shortDescFaultSources[source];
1176  }
1177  } else {
1178  // AArch64
1179  fsc = ArmFault::aarch64FaultSources[source];
1180  }
1181 
1182  return fsc;
1183 }
1184 
1185 template<class T>
1186 FSR
1188 {
1189  FSR fsr = 0;
1190 
1191  auto fsc = getFaultStatusCode(tc);
1192 
1193  // AArch32
1194  assert(tranMethod != ArmFault::UnknownTran);
1195  if (tranMethod == ArmFault::LpaeTran) {
1196  fsr.status = fsc;
1197  fsr.lpae = 1;
1198  } else {
1199  fsr.fsLow = bits(fsc, 3, 0);
1200  fsr.fsHigh = bits(fsc, 4);
1201  fsr.domain = static_cast<uint8_t>(domain);
1202  }
1203 
1204  fsr.wnr = (write ? 1 : 0);
1205  fsr.ext = 0;
1206 
1207  return fsr;
1208 }
1209 
1210 template<class T>
1211 bool
1213 {
1214  if (ArmSystem::haveEL(tc, EL3)) {
1215  SCR scr = tc->readMiscRegNoEffect(MISCREG_SCR);
1216  return (!scr.ns || scr.aw);
1217  }
1218  return true;
1219 }
1220 
1221 template<class T>
1222 void
1224 {
1225  switch (id)
1226  {
1227  case ArmFault::S1PTW:
1228  s1ptw = val;
1229  break;
1230  case ArmFault::OVA:
1231  OVAddr = val;
1232  break;
1233 
1234  // Just ignore unknown ID's
1235  default:
1236  break;
1237  }
1238 }
1239 
1240 template<class T>
1241 bool
1243 {
1244  // NOTE: Not relying on LL information being aligned to lowest bits here
1245  return
1246  (source == ArmFault::AlignmentFault) ||
1247  ((source >= ArmFault::TranslationLL) &&
1248  (source < ArmFault::TranslationLL + 4)) ||
1249  ((source >= ArmFault::AccessFlagLL) &&
1250  (source < ArmFault::AccessFlagLL + 4)) ||
1251  ((source >= ArmFault::DomainLL) &&
1252  (source < ArmFault::DomainLL + 4)) ||
1253  ((source >= ArmFault::PermissionLL) &&
1254  (source < ArmFault::PermissionLL + 4));
1255 }
1256 
1257 template<class T>
1258 bool
1260 {
1261  va = (stage2 ? OVAddr : faultAddr);
1262  return true;
1263 }
1264 
1267 {
1268  if (to64) {
1269  // AArch64
1270  if (toEL == fromEL)
1272  else
1274  } else {
1275  // AArch32
1276  // Abort faults have different EC codes depending on whether
1277  // the fault originated within HYP mode, or not. So override
1278  // the method and add the extra adjustment of the EC value.
1279 
1281 
1282  CPSR spsr = tc->readMiscReg(MISCREG_SPSR_HYP);
1283  if (spsr.mode == MODE_HYP) {
1284  ec = ((ExceptionClass) (((uint32_t) ec) + 1));
1285  }
1286  return ec;
1287  }
1288 }
1289 
1290 uint32_t
1292 {
1293  ESR esr = 0;
1294  auto& iss = esr.instruction_abort_iss;
1295 
1296  iss.ifsc = srcEncoded & 0x3F;
1297  iss.s1ptw = s1ptw;
1298 
1299  return iss;
1300 }
1301 
1302 bool
1304 {
1305  SCR scr = 0;
1306  if (from64)
1308  else
1309  scr = tc->readMiscRegNoEffect(MISCREG_SCR);
1310 
1311  return scr.ea && !isMMUFault();
1312 }
1313 
1314 bool
1316 {
1317  bool toHyp;
1318 
1319  HCR hcr = tc->readMiscRegNoEffect(MISCREG_HCR);
1320  HDCR hdcr = tc->readMiscRegNoEffect(MISCREG_HDCR);
1321 
1322  toHyp = fromEL == EL2;
1323  toHyp |= ArmSystem::haveEL(tc, EL2) && !isSecure(tc) &&
1324  currEL(tc) <= EL1 && (hcr.tge || stage2 ||
1325  (source == DebugEvent && hdcr.tde));
1326  return toHyp;
1327 }
1328 
1331 {
1332  if (to64) {
1333  // AArch64
1335  panic("Asynchronous External Abort should be handled with "
1336  "SystemErrors (SErrors)!");
1337  }
1338  if (toEL == fromEL)
1339  return EC_DATA_ABORT_CURR_EL;
1340  else
1341  return EC_DATA_ABORT_LOWER_EL;
1342  } else {
1343  // AArch32
1344  // Abort faults have different EC codes depending on whether
1345  // the fault originated within HYP mode, or not. So override
1346  // the method and add the extra adjustment of the EC value.
1347 
1349 
1350  CPSR spsr = tc->readMiscReg(MISCREG_SPSR_HYP);
1351  if (spsr.mode == MODE_HYP) {
1352  ec = ((ExceptionClass) (((uint32_t) ec) + 1));
1353  }
1354  return ec;
1355  }
1356 }
1357 
1358 bool
1360 {
1361  return !isv? true : AbortFault<DataAbort>::il(tc);
1362 }
1363 
1364 bool
1366 {
1367  SCR scr = 0;
1368  if (from64)
1370  else
1371  scr = tc->readMiscRegNoEffect(MISCREG_SCR);
1372 
1373  return scr.ea && !isMMUFault();
1374 }
1375 
1376 bool
1378 {
1379  bool toHyp;
1380 
1381  HCR hcr = tc->readMiscRegNoEffect(MISCREG_HCR);
1382  HDCR hdcr = tc->readMiscRegNoEffect(MISCREG_HDCR);
1383 
1384  bool amo = hcr.amo;
1385  if (hcr.tge == 1)
1386  amo = (!HaveExt(tc, ArmExtension::FEAT_VHE) || hcr.e2h == 0);
1387 
1388  // if in Hyp mode then stay in Hyp mode
1389  toHyp = fromEL == EL2 ||
1390  (EL2Enabled(tc) && fromEL <= EL1
1391  && (hcr.tge || stage2 ||
1392  ((source == AsynchronousExternalAbort) && amo) ||
1393  ((fromEL == EL0) && hcr.tge &&
1394  ((source == AlignmentFault) ||
1396  ((source == DebugEvent) && (hdcr.tde || hcr.tge))));
1397  return toHyp;
1398 }
1399 
1400 uint32_t
1402 {
1403  ESR esr = 0;
1404  auto& iss = esr.data_abort_iss;
1405 
1406  iss.dfsc = srcEncoded & 0x3F;
1407  iss.wnr = write;
1408  iss.s1ptw = s1ptw;
1409  iss.cm = cm;
1410 
1411  // ISS is valid if not caused by a stage 1 page table walk, and when taken
1412  // to AArch64 only when directed to EL2
1413  if (!s1ptw && stage2 && (!to64 || toEL == EL2)) {
1414  iss.isv = isv;
1415  if (isv) {
1416  iss.sas = sas;
1417  iss.sse = sse;
1418  iss.srt = srt;
1419  // AArch64 only. These assignments are safe on AArch32 as well
1420  // because these vars are initialized to false
1421  iss.sf = sf;
1422  iss.ar = ar;
1423  }
1424  }
1425  return iss;
1426 }
1427 
1428 void
1430 {
1432  switch (id)
1433  {
1434  case SAS:
1435  isv = true;
1436  sas = val;
1437  break;
1438  case SSE:
1439  isv = true;
1440  sse = val;
1441  break;
1442  case SRT:
1443  isv = true;
1444  srt = val;
1445  break;
1446  case SF:
1447  isv = true;
1448  sf = val;
1449  break;
1450  case AR:
1451  isv = true;
1452  ar = val;
1453  break;
1454  case CM:
1455  cm = val;
1456  break;
1457  case OFA:
1458  faultAddr = val;
1459  break;
1460  // Just ignore unknown ID's
1461  default:
1462  break;
1463  }
1464 }
1465 
1466 void
1468 {
1470  HCR hcr = tc->readMiscRegNoEffect(MISCREG_HCR);
1471  hcr.va = 0;
1472  tc->setMiscRegNoEffect(MISCREG_HCR, hcr);
1473 }
1474 
1475 bool
1477 {
1478  assert(ArmSystem::haveEL(tc, EL3));
1479  SCR scr = 0;
1480  if (from64)
1482  else
1483  scr = tc->readMiscRegNoEffect(MISCREG_SCR);
1484  return scr.irq;
1485 }
1486 
1487 bool
1489 {
1490  HCR hcr = tc->readMiscRegNoEffect(MISCREG_HCR);
1491  return fromEL == EL2 ||
1492  (EL2Enabled(tc) && fromEL <= EL1 && (hcr.tge || hcr.imo));
1493 }
1494 
1495 bool
1497 {
1498  if (ArmSystem::haveEL(tc, EL3)) {
1499  SCR scr = tc->readMiscRegNoEffect(MISCREG_SCR);
1500  return (!scr.ns || scr.aw);
1501  }
1502  return true;
1503 }
1504 
1506 {}
1507 
1508 bool
1510 {
1511  assert(ArmSystem::haveEL(tc, EL3));
1512  SCR scr = 0;
1513  if (from64)
1515  else
1516  scr = tc->readMiscRegNoEffect(MISCREG_SCR);
1517  return scr.fiq;
1518 }
1519 
1520 bool
1522 {
1523  HCR hcr = tc->readMiscRegNoEffect(MISCREG_HCR);
1524  return fromEL == EL2 ||
1525  (EL2Enabled(tc) && fromEL <= EL1 && (hcr.tge || hcr.fmo));
1526 }
1527 
1528 bool
1530 {
1531  if (ArmSystem::haveEL(tc, EL3)) {
1532  SCR scr = tc->readMiscRegNoEffect(MISCREG_SCR);
1533  return (!scr.ns || scr.aw);
1534  }
1535  return true;
1536 }
1537 
1538 bool
1540 {
1541  if (ArmSystem::haveEL(tc, EL2)) {
1542  return true;
1543  } else if (ArmSystem::haveEL(tc, EL3)) {
1544  SCR scr = tc->readMiscRegNoEffect(MISCREG_SCR);
1545  return (!scr.ns || scr.fw);
1546  }
1547  return true;
1548 }
1549 
1551 {}
1552 
1553 void
1555 {
1557  assert(from64);
1558  // Set the FAR
1560 }
1561 
1562 bool
1564 {
1565  HCR hcr = tc->readMiscRegNoEffect(MISCREG_HCR_EL2);
1566  return fromEL == EL2 || (EL2Enabled(tc) && fromEL <= EL1 && hcr.tge);
1567 }
1568 
1570 {}
1571 
1572 bool
1574 {
1575  assert(from64);
1576  HCR hcr = tc->readMiscRegNoEffect(MISCREG_HCR_EL2);
1577  return EL2Enabled(tc) && currEL(tc) <= EL1 && hcr.tge == 1;
1578 }
1579 
1581 {}
1582 
1583 void
1585 {
1586  tc->getCpuPtr()->clearInterrupt(tc->threadId(), INT_ABT, 0);
1587  ArmFault::invoke(tc, inst);
1588 }
1589 
1590 bool
1592 {
1593  assert(ArmSystem::haveEL(tc, EL3));
1594  assert(from64);
1595  SCR scr = tc->readMiscRegNoEffect(MISCREG_SCR_EL3);
1596  return scr.ea || fromEL == EL3;
1597 }
1598 
1599 bool
1601 {
1602  assert(from64);
1603 
1604  HCR hcr = tc->readMiscRegNoEffect(MISCREG_HCR_EL2);
1605 
1606  return fromEL == EL2 ||
1607  (EL2Enabled(tc) && fromEL <= EL1 && (hcr.tge || hcr.amo));
1608 }
1609 
1610 
1612  : ArmFaultVals<SoftwareBreakpoint>(mach_inst, _iss)
1613 {}
1614 
1615 bool
1617 {
1618  const HCR hcr = tc->readMiscRegNoEffect(MISCREG_HCR_EL2);
1619  const HDCR mdcr = tc->readMiscRegNoEffect(MISCREG_MDCR_EL2);
1620 
1621  return fromEL == EL2 ||
1622  (EL2Enabled(tc) && fromEL <= EL1 && (hcr.tge || mdcr.tde));
1623 }
1624 
1627 {
1629 }
1630 
1632  : ArmFaultVals<HardwareBreakpoint>(0x0, _iss), vAddr(vaddr)
1633 {}
1634 
1635 bool
1637 {
1638  const HCR hcr = tc->readMiscRegNoEffect(MISCREG_HCR_EL2);
1639  const HDCR mdcr = tc->readMiscRegNoEffect(MISCREG_MDCR_EL2);
1640 
1641  return EL2Enabled(tc) && fromEL <= EL1 && (hcr.tge || mdcr.tde);
1642 }
1643 
1646 {
1647  // AArch64
1648  if (toEL == fromEL)
1649  return EC_HW_BREAKPOINT_CURR_EL;
1650  else
1652 }
1653 
1654 void
1656 {
1657 
1659  MiscRegIndex elr_idx;
1660  switch (toEL) {
1661  case EL1:
1662  elr_idx = MISCREG_ELR_EL1;
1663  break;
1664  case EL2:
1665  assert(ArmSystem::haveEL(tc, EL2));
1666  elr_idx = MISCREG_ELR_EL2;
1667  break;
1668  case EL3:
1669  assert(ArmSystem::haveEL(tc, EL3));
1670  elr_idx = MISCREG_ELR_EL3;
1671  break;
1672  default:
1673  panic("Invalid target exception level");
1674  break;
1675  }
1676 
1677  tc->setMiscReg(elr_idx, vAddr);
1678 
1679 }
1680 
1682  bool _write, bool _cm)
1683  : ArmFaultVals<Watchpoint>(mach_inst), vAddr(_vaddr),
1684  write(_write), cm(_cm)
1685 {}
1686 
1687 uint32_t
1689 {
1690  ESR esr = 0;
1691  auto& iss = esr.watchpoint_iss;
1692  iss.dfsc = 0b100010;
1693  iss.cm = cm;
1694  iss.wnr = write;
1695  return iss;
1696 }
1697 
1698 void
1700 {
1702  // Set the FAR
1704 
1705 }
1706 
1707 bool
1709 {
1710  const HCR hcr = tc->readMiscRegNoEffect(MISCREG_HCR_EL2);
1711  const HDCR mdcr = tc->readMiscRegNoEffect(MISCREG_MDCR_EL2);
1712 
1713  return fromEL == EL2 ||
1714  (EL2Enabled(tc) && fromEL <= EL1 && (hcr.tge || mdcr.tde));
1715 }
1716 
1717 void
1719 {
1721  switch (id)
1722  {
1723  case OFA:
1724  vAddr = val;
1725  break;
1726  // Just ignore unknown ID's
1727  default:
1728  break;
1729  }
1730 }
1731 
1734 {
1735  // AArch64
1736  if (toEL == fromEL)
1737  return EC_WATCHPOINT_CURR_EL;
1738  else
1739  return EC_WATCHPOINT_LOWER_EL;
1740 }
1741 
1743  bool _stepped)
1744  : ArmFaultVals<SoftwareStepFault>(mach_inst), isldx(is_ldx),
1745  stepped(_stepped)
1746 {
1747  bStep = true;
1748 }
1749 
1750 bool
1752 {
1753  const HCR hcr = tc->readMiscRegNoEffect(MISCREG_HCR_EL2);
1754  const HDCR mdcr = tc->readMiscRegNoEffect(MISCREG_MDCR_EL2);
1755 
1756  return fromEL == EL2 ||
1757  (EL2Enabled(tc) && fromEL <= EL1 && (hcr.tge || mdcr.tde));
1758 }
1759 
1762 {
1763  // AArch64
1764  if (toEL == fromEL)
1765  return EC_SOFTWARE_STEP_CURR_EL;
1766  else
1768 }
1769 
1770 uint32_t
1772 {
1773  ESR esr = 0;
1774  auto& iss = esr.software_step_iss;
1775  iss.ifsc = 0b100010;
1776  iss.isv = stepped;
1777  iss.ex = isldx;
1778  return iss;
1779 }
1780 
1781 void
1783 {
1784  DPRINTF(Faults, "Invoking ArmSev Fault\n");
1785  if (!FullSystem)
1786  return;
1787 
1788  // Set sev_mailbox to 1, clear the pending interrupt from remote
1789  // SEV execution and let pipeline continue as pcState is still
1790  // valid.
1792  tc->getCpuPtr()->clearInterrupt(tc->threadId(), INT_SEV, 0);
1793 }
1794 
1795 // Instantiate all the templates to make the linker happy
1796 template class ArmFaultVals<Reset>;
1797 template class ArmFaultVals<UndefinedInstruction>;
1798 template class ArmFaultVals<SupervisorCall>;
1799 template class ArmFaultVals<SecureMonitorCall>;
1800 template class ArmFaultVals<HypervisorCall>;
1801 template class ArmFaultVals<PrefetchAbort>;
1802 template class ArmFaultVals<DataAbort>;
1803 template class ArmFaultVals<VirtualDataAbort>;
1804 template class ArmFaultVals<HypervisorTrap>;
1805 template class ArmFaultVals<Interrupt>;
1806 template class ArmFaultVals<VirtualInterrupt>;
1807 template class ArmFaultVals<FastInterrupt>;
1808 template class ArmFaultVals<VirtualFastInterrupt>;
1809 template class ArmFaultVals<SupervisorTrap>;
1810 template class ArmFaultVals<SecureMonitorTrap>;
1811 template class ArmFaultVals<PCAlignmentFault>;
1812 template class ArmFaultVals<SPAlignmentFault>;
1813 template class ArmFaultVals<SystemError>;
1814 template class ArmFaultVals<SoftwareBreakpoint>;
1815 template class ArmFaultVals<HardwareBreakpoint>;
1816 template class ArmFaultVals<Watchpoint>;
1817 template class ArmFaultVals<SoftwareStepFault>;
1818 template class ArmFaultVals<ArmSev>;
1819 template class AbortFault<PrefetchAbort>;
1820 template class AbortFault<DataAbort>;
1821 template class AbortFault<VirtualDataAbort>;
1822 
1823 
1825 {}
1826 
1827 bool
1829 {
1830  const HCR hcr = tc->readMiscRegNoEffect(MISCREG_HCR_EL2);
1831  return EL2Enabled(tc) && fromEL == EL0 && hcr.tge;
1832 }
1833 
1834 bool
1836 {
1837  auto arm_fault = dynamic_cast<ArmFault *>(fault.get());
1838 
1839  if (arm_fault) {
1840  return arm_fault->getFaultVAddr(va);
1841  } else {
1842  auto pgt_fault = dynamic_cast<GenericPageTableFault *>(fault.get());
1843  if (pgt_fault) {
1844  va = pgt_fault->getFaultVAddr();
1845  return true;
1846  }
1847 
1848  auto align_fault = dynamic_cast<GenericAlignmentFault *>(fault.get());
1849  if (align_fault) {
1850  va = align_fault->getFaultVAddr();
1851  return true;
1852  }
1853 
1854  // Return false since it's not an address triggered exception
1855  return false;
1856  }
1857 }
1858 
1859 } // namespace ArmISA
1860 } // namespace gem5
gem5::ArmISA::MISCREG_FAR_EL1
@ MISCREG_FAR_EL1
Definition: misc.hh:650
gem5::ArmISA::MISCREG_CPSR
@ MISCREG_CPSR
Definition: misc.hh:61
gem5::ArmISA::ArmFault::NODEBUG
@ NODEBUG
Definition: faults.hh:159
gem5::ArmISA::ArmFault::fromEL
ExceptionLevel fromEL
Definition: faults.hh:74
gem5::ArmISA::AbortFault::annotate
void annotate(ArmFault::AnnotationIDs id, uint64_t val) override
Definition: faults.cc:1223
gem5::ArmISA::AbortFault::setSyndrome
void setSyndrome(ThreadContext *tc, MiscRegIndex syndrome_reg) override
Definition: faults.cc:1150
gem5::ArmISA::ArmFault::FaultVals::ec
const ExceptionClass ec
Definition: faults.hh:194
gem5::ArmISA::ArmFault::NumFaultSources
@ NumFaultSources
Definition: faults.hh:119
gem5::ArmISA::SupervisorTrap::ec
ExceptionClass ec(ThreadContext *tc) const override
Syndrome methods.
Definition: faults.cc:1051
gem5::PCStateBase::instAddr
Addr instAddr() const
Returns the memory address of the instruction this PC points to.
Definition: pcstate.hh:107
gem5::ArmISA::EC_SOFTWARE_STEP
@ EC_SOFTWARE_STEP
Definition: types.hh:342
gem5::ArmISA::EC_PREFETCH_ABORT_TO_HYP
@ EC_PREFETCH_ABORT_TO_HYP
Definition: types.hh:326
gem5::ArmISA::MISCREG_VBAR_EL3
@ MISCREG_VBAR_EL3
Definition: misc.hh:743
gem5::ThreadContext::readMiscReg
virtual RegVal readMiscReg(RegIndex misc_reg)=0
gem5::ArmISA::UndefinedInstruction::mnemonic
const char * mnemonic
Definition: faults.hh:330
gem5::ArmISA::SPAlignmentFault::SPAlignmentFault
SPAlignmentFault()
Definition: faults.cc:1569
gem5::ArmISA::MODE_SVC
@ MODE_SVC
Definition: types.hh:291
gem5::ArmISA::EC_HVC
@ EC_HVC
Definition: types.hh:318
gem5::ArmISA::DataAbort::routeToMonitor
bool routeToMonitor(ThreadContext *tc) const override
Definition: faults.cc:1365
gem5::NoFault
constexpr decltype(nullptr) NoFault
Definition: types.hh:253
gem5::ArmISA::MISCREG_TTBCR_S
@ MISCREG_TTBCR_S
Definition: misc.hh:263
gem5::ThreadContext::getSystemPtr
virtual System * getSystemPtr()=0
gem5::ArmISA::MODE_MON
@ MODE_MON
Definition: types.hh:292
gem5::ArmISA::UndefinedInstruction::ec
ExceptionClass ec(ThreadContext *tc) const override
Syndrome methods.
Definition: faults.cc:915
gem5::ArmISA::ELIs64
bool ELIs64(ThreadContext *tc, ExceptionLevel el)
Definition: utility.cc:273
gem5::ArmISA::SoftwareBreakpoint::routeToHyp
bool routeToHyp(ThreadContext *tc) const override
Definition: faults.cc:1616
gem5::ArmISA::EC_ILLEGAL_INST
@ EC_ILLEGAL_INST
Definition: types.hh:315
gem5::ArmISA::DataAbort::sf
bool sf
Definition: faults.hh:555
gem5::ArmISA::MODE_FIQ
@ MODE_FIQ
Definition: types.hh:289
gem5::ArmISA::EC_WATCHPOINT
@ EC_WATCHPOINT
Definition: types.hh:345
gem5::ArmISA::ArmFault::bStep
bool bStep
Definition: faults.hh:71
gem5::ArmSystem::highestELIs64
bool highestELIs64() const
Returns true if the register width of the highest implemented exception level is 64 bits (ARMv8)
Definition: system.hh:183
gem5::ArmISA::SelfDebug
Definition: self_debug.hh:277
gem5::ArmISA::ArmFault::FaultSourceInvalid
@ FaultSourceInvalid
Definition: faults.hh:120
gem5::ArmISA::PCAlignmentFault::faultPC
Addr faultPC
The unaligned value of the PC.
Definition: faults.hh:630
gem5::ArmISA::ArmFault::abortDisable
virtual bool abortDisable(ThreadContext *tc)=0
gem5::ArmISA::EC_HW_BREAKPOINT_LOWER_EL
@ EC_HW_BREAKPOINT_LOWER_EL
Definition: types.hh:340
gem5::ArmISA::ArmStaticInst
Definition: static_inst.hh:65
gem5::ArmISA::ArmFault::BRKPOINT
@ BRKPOINT
Definition: faults.hh:160
gem5::ArmISA::HypervisorCall
Definition: faults.hh:436
gem5::ArmISA::EC_SERROR
@ EC_SERROR
Definition: types.hh:338
gem5::ArmISA::ArmFault::issRaw
uint32_t issRaw
Definition: faults.hh:68
gem5::ArmISA::ArmFaultVals::il
bool il(ThreadContext *tc) const override
Definition: faults.hh:306
gem5::ArmISA::EC_SVC_TO_HYP
@ EC_SVC_TO_HYP
Definition: types.hh:316
gem5::ArmISA::ArmFault::AR
@ AR
Definition: faults.hh:147
gem5::ArmISA::MISCREG_SPSR_FIQ
@ MISCREG_SPSR_FIQ
Definition: misc.hh:63
gem5::ArmISA::SystemError::SystemError
SystemError()
Definition: faults.cc:1580
gem5::ThreadContext::getReg
virtual RegVal getReg(const RegId &reg) const
Definition: thread_context.cc:171
gem5::ArmISA::HypervisorTrap::overrideEc
ExceptionClass overrideEc
Definition: faults.hh:453
gem5::ArmISA::MISCREG_MDCR_EL2
@ MISCREG_MDCR_EL2
Definition: misc.hh:588
gem5::ArmISA::EC_DATA_ABORT_LOWER_EL
@ EC_DATA_ABORT_LOWER_EL
Definition: types.hh:332
gem5::ArmISA::ArmFaultVals::vals
static FaultVals vals
Definition: faults.hh:266
gem5::ArmISA::SecureMonitorCall::ec
ExceptionClass ec(ThreadContext *tc) const override
Syndrome methods.
Definition: faults.cc:1028
gem5::ArmISA::ArmFault::from64
bool from64
Definition: faults.hh:72
gem5::ArmISA::MODE_UNDEFINED
@ MODE_UNDEFINED
Definition: types.hh:295
gem5::ArmISA::HardwareBreakpoint::routeToHyp
bool routeToHyp(ThreadContext *tc) const override
Definition: faults.cc:1636
gem5::PCStateBase::as
Target & as()
Definition: pcstate.hh:72
gem5::ArmISA::MODE_IRQ
@ MODE_IRQ
Definition: types.hh:290
gem5::ArmISA::ArmFault::VECTORCATCH
@ VECTORCATCH
Definition: faults.hh:161
gem5::ArmISA::MISCREG_SCR_EL3
@ MISCREG_SCR_EL3
Definition: misc.hh:594
gem5::ArmISA::domain
Bitfield< 7, 4 > domain
Definition: misc_types.hh:424
gem5::ArmISA::HypervisorTrap::ec
ExceptionClass ec(ThreadContext *tc) const override
Syndrome methods.
Definition: faults.cc:951
gem5::ThreadContext::pcState
virtual const PCStateBase & pcState() const =0
gem5::ArmISA::UndefinedInstruction::overrideEc
ExceptionClass overrideEc
Definition: faults.hh:329
gem5::ArmISA::UndefinedInstruction::disabled
bool disabled
Definition: faults.hh:328
gem5::ArmISA::ArmFault::SynchronousExternalAbort
@ SynchronousExternalAbort
Definition: faults.hh:106
gem5::ArmISA::EC_HVC_64
@ EC_HVC_64
Definition: types.hh:322
gem5::ArmISA::ArmFault::LpaeTran
@ LpaeTran
Definition: faults.hh:152
gem5::ArmISA::ArmFault::faultUpdated
bool faultUpdated
Definition: faults.hh:82
gem5::ArmISA::ArmFault::SSE
@ SSE
Definition: faults.hh:137
gem5::ArmISA::MISCREG_VBAR_EL2
@ MISCREG_VBAR_EL2
Definition: misc.hh:741
gem5::ArmISA::UndefinedInstruction::unknown
bool unknown
Definition: faults.hh:327
gem5::ArmISA::MISCREG_HSCTLR
@ MISCREG_HSCTLR
Definition: misc.hh:247
gem5::ArmISA::MISCREG_ESR_EL2
@ MISCREG_ESR_EL2
Definition: misc.hh:645
gem5::ArmISA::DataAbort::iss
uint32_t iss() const override
Definition: faults.cc:1401
gem5::ArmISA::PCAlignmentFault::routeToHyp
bool routeToHyp(ThreadContext *tc) const override
Definition: faults.cc:1563
gem5::ArmISA::HypervisorCall::routeToHyp
bool routeToHyp(ThreadContext *tc) const override
Definition: faults.cc:939
gem5::X86ISA::val
Bitfield< 63 > val
Definition: misc.hh:769
gem5::ArmISA::ArmFault::armPcElrOffset
virtual uint8_t armPcElrOffset()=0
gem5::ArmISA::Watchpoint::vAddr
Addr vAddr
Definition: faults.hh:696
gem5::ArmISA::AbortFault::getFaultStatusCode
uint8_t getFaultStatusCode(ThreadContext *tc) const
Definition: faults.cc:1161
gem5::ArmISA::PrefetchAbort::routeToMonitor
bool routeToMonitor(ThreadContext *tc) const override
Definition: faults.cc:1303
gem5::ArmISA::opModeIsT
static bool opModeIsT(OperatingMode mode)
Definition: types.hh:383
gem5::ArmISA::ArmFault::DomainLL
@ DomainLL
Definition: faults.hh:103
gem5::ArmISA::MISCREG_LOCKFLAG
@ MISCREG_LOCKFLAG
Definition: misc.hh:83
gem5::ArmISA::Interrupt::routeToMonitor
bool routeToMonitor(ThreadContext *tc) const override
Definition: faults.cc:1476
gem5::ArmISA::EL1
@ EL1
Definition: types.hh:274
gem5::ArmISA::EC_SOFTWARE_BREAKPOINT
@ EC_SOFTWARE_BREAKPOINT
Definition: types.hh:348
gem5::ArmISA::ArmFault::offset64
virtual FaultOffset offset64(ThreadContext *tc)=0
gem5::ArmISA::ArmFault::DebugEvent
@ DebugEvent
Definition: faults.hh:105
gem5::System::workload
Workload * workload
OS kernel.
Definition: system.hh:330
gem5::ArmISA::Watchpoint::routeToHyp
bool routeToHyp(ThreadContext *tc) const override
Definition: faults.cc:1708
gem5::ArmISA::opModeToEL
static ExceptionLevel opModeToEL(OperatingMode mode)
Definition: types.hh:390
gem5::ArmISA::MISCREG_SPSR_MON
@ MISCREG_SPSR_MON
Definition: misc.hh:66
gem5::ArmISA::ELIsInHost
bool ELIsInHost(ThreadContext *tc, ExceptionLevel el)
Returns true if the current exception level el is executing a Host OS or an application of a Host OS ...
Definition: utility.cc:287
gem5::ArmISA::Watchpoint
Definition: faults.hh:693
gem5::csprintf
std::string csprintf(const char *format, const Args &...args)
Definition: cprintf.hh:161
gem5::ArmISA::SupervisorTrap::iss
uint32_t iss() const override
Definition: faults.cc:1041
gem5::RefCountingPtr::get
T * get() const
Directly access the pointer itself without taking a reference.
Definition: refcnt.hh:227
gem5::X86ISA::base
Bitfield< 51, 12 > base
Definition: pagetable.hh:141
gem5::ArmISA::HardwareBreakpoint::vAddr
Addr vAddr
Definition: faults.hh:681
gem5::ArmISA::ArmFault::thumbPcOffset
virtual uint8_t thumbPcOffset(bool is_hyp)=0
gem5::ArmISA::VirtualDataAbort::invoke
void invoke(ThreadContext *tc, const StaticInstPtr &inst) override
Definition: faults.cc:1467
gem5::ArmISA::SoftwareStepFault::isldx
bool isldx
Definition: faults.hh:716
system.hh
gem5::ArmISA::ArmStaticInst::encoding
MachInst encoding() const
Returns the real encoding of the instruction: the machInst field is in fact always 64 bit wide and co...
Definition: static_inst.hh:565
gem5::ArmISA::ArmFault::setSyndrome
virtual void setSyndrome(ThreadContext *tc, MiscRegIndex syndrome_reg)
Definition: faults.cc:398
gem5::ArmISA::ArmFault::to64
bool to64
Definition: faults.hh:73
gem5::ArmISA::MISCREG_SCTLR
@ MISCREG_SCTLR
Definition: misc.hh:236
gem5::ArmISA::getFaultVAddr
bool getFaultVAddr(Fault fault, Addr &va)
Returns true if the fault passed as a first argument was triggered by a memory access,...
Definition: faults.cc:1835
gem5::PowerISA::PCState
Definition: pcstate.hh:42
gem5::ArmISA::SoftwareBreakpoint::ec
ExceptionClass ec(ThreadContext *tc) const override
Syndrome methods.
Definition: faults.cc:1626
gem5::ArmISA::SystemError::routeToHyp
bool routeToHyp(ThreadContext *tc) const override
Definition: faults.cc:1600
gem5::ArmISA::ArmFault::getVector64
Addr getVector64(ThreadContext *tc)
Definition: faults.cc:343
gem5::ArmISA::SystemError::routeToMonitor
bool routeToMonitor(ThreadContext *tc) const override
Definition: faults.cc:1591
gem5::StaticInst::advancePC
virtual void advancePC(PCStateBase &pc_state) const =0
gem5::ArmISA::ArmFault::PermissionLL
@ PermissionLL
Definition: faults.hh:104
gem5::FaultBase::name
virtual FaultName name() const =0
gem5::ArmISA::EC_WATCHPOINT_LOWER_EL
@ EC_WATCHPOINT_LOWER_EL
Definition: types.hh:346
gem5::ArmISA::ArmFault::AsynchronousExternalAbort
@ AsynchronousExternalAbort
Definition: faults.hh:109
gem5::ArmISA::PCAlignmentFault::invoke
void invoke(ThreadContext *tc, const StaticInstPtr &inst=nullStaticInstPtr) override
Definition: faults.cc:1554
gem5::RefCountingPtr< StaticInst >
gem5::ArmISA::ArmFault::VmsaTran
@ VmsaTran
Definition: faults.hh:153
gem5::ArmISA::AbortFault::getFsr
FSR getFsr(ThreadContext *tc) const override
Definition: faults.cc:1187
gem5::ArmISA::MISCREG_DBGDSCRext
@ MISCREG_DBGDSCRext
Definition: misc.hh:104
gem5::ArmISA::EC_SMC_64
@ EC_SMC_64
Definition: types.hh:323
gem5::ArmISA::purifyTaggedAddr
Addr purifyTaggedAddr(Addr addr, ThreadContext *tc, ExceptionLevel el, TCR tcr, bool is_instr)
Removes the tag from tagged addresses if that mode is enabled.
Definition: utility.cc:470
gem5::ArmISA::SupervisorCall::iss
uint32_t iss() const override
Definition: faults.cc:899
gem5::ArmISA::cc_reg::Nz
constexpr RegId Nz(CCRegClass, _NzIdx)
gem5::ArmISA::ArmFault::OFA
@ OFA
Definition: faults.hh:140
gem5::ArmISA::ArmFault::iss
virtual uint32_t iss() const =0
gem5::GenericPageTableFault
Definition: faults.hh:116
gem5::ArmISA::FastInterrupt::abortDisable
bool abortDisable(ThreadContext *tc) override
Definition: faults.cc:1529
gem5::ArmISA::INT_ABT
@ INT_ABT
Definition: interrupts.hh:62
gem5::ArmISA::Watchpoint::invoke
void invoke(ThreadContext *tc, const StaticInstPtr &inst=nullStaticInstPtr) override
Definition: faults.cc:1699
gem5::ArmISA::amo
Bitfield< 5 > amo
Definition: misc_types.hh:280
gem5::ArmISA::ArmFault::instrAnnotate
ArmStaticInst * instrAnnotate(const StaticInstPtr &inst)
Definition: faults.cc:747
gem5::ArmISA::MISCREG_ELR_EL1
@ MISCREG_ELR_EL1
Definition: misc.hh:615
gem5::ArmISA::ArmFault::thumbPcElrOffset
virtual uint8_t thumbPcElrOffset()=0
gem5::ArmISA::ArmFaultVals
Definition: faults.hh:263
interrupts.hh
gem5::ThreadContext
ThreadContext is the external interface to all thread state for anything outside of the CPU.
Definition: thread_context.hh:94
gem5::ArmISA::EC_UNKNOWN
@ EC_UNKNOWN
Definition: types.hh:303
gem5::ArmISA::MODE_HYP
@ MODE_HYP
Definition: types.hh:294
gem5::ArmISA::ArmFault::offset
virtual FaultOffset offset(ThreadContext *tc)=0
gem5::ArmISA::MISCREG_SCTLR_EL1
@ MISCREG_SCTLR_EL1
Definition: misc.hh:580
gem5::ArmISA::SoftwareStepFault
Definition: faults.hh:713
gem5::ArmISA::HardwareBreakpoint
Definition: faults.hh:678
gem5::Fault
std::shared_ptr< FaultBase > Fault
Definition: types.hh:248
gem5::ArmISA::MISCREG_HDCR
@ MISCREG_HDCR
Definition: misc.hh:251
gem5::ArmISA::EC_SOFTWARE_BREAKPOINT_64
@ EC_SOFTWARE_BREAKPOINT_64
Definition: types.hh:350
gem5::ArmISA::cc_reg::V
constexpr RegId V(CCRegClass, _VIdx)
gem5::ArmISA::ArmFault::getSyndromeReg64
MiscRegIndex getSyndromeReg64() const
Definition: faults.cc:366
gem5::ArmISA::SecureMonitorCall::invoke
void invoke(ThreadContext *tc, const StaticInstPtr &inst=nullStaticInstPtr) override
Definition: faults.cc:1019
DPRINTF
#define DPRINTF(x,...)
Definition: trace.hh:186
gem5::ArmISA::ArmFault::toEL
ExceptionLevel toEL
Definition: faults.hh:75
gem5::ArmISA::MISCREG_MVBAR
@ MISCREG_MVBAR
Definition: misc.hh:395
gem5::ArmISA::DataAbort::ec
ExceptionClass ec(ThreadContext *tc) const override
Syndrome methods.
Definition: faults.cc:1330
gem5::ArmISA::SecureMonitorTrap::ec
ExceptionClass ec(ThreadContext *tc) const override
Syndrome methods.
Definition: faults.cc:1060
gem5::ArmISA::FastInterrupt::routeToHyp
bool routeToHyp(ThreadContext *tc) const override
Definition: faults.cc:1521
gem5::ArmISA::ArmFault::hypRouted
bool hypRouted
Definition: faults.hh:84
gem5::ArmISA::EL2
@ EL2
Definition: types.hh:275
gem5::ArmISA::MISCREG_SPSR_IRQ
@ MISCREG_SPSR_IRQ
Definition: misc.hh:64
gem5::ArmISA::SupervisorCall::invoke
void invoke(ThreadContext *tc, const StaticInstPtr &inst=nullStaticInstPtr) override
Definition: faults.cc:865
gem5::ArmISA::MISCREG_SCTLR_EL2
@ MISCREG_SCTLR_EL2
Definition: misc.hh:585
gem5::ArmISA::COND_UC
@ COND_UC
Definition: cc.hh:99
gem5::ArmISA::ArmFault::shortDescFaultSources
static uint8_t shortDescFaultSources[NumFaultSources]
Encodings of the fault sources when the short-desc.
Definition: faults.hh:125
gem5::ArmISA::DataAbort::sas
uint8_t sas
Definition: faults.hh:549
isa.hh
gem5::ArmISA::s1ptw
Bitfield< 7 > s1ptw
Definition: misc_types.hh:697
gem5::ArmISA::ELIs32
bool ELIs32(ThreadContext *tc, ExceptionLevel el)
Definition: utility.cc:279
gem5::ArmISA::ArmFault::update
void update(ThreadContext *tc)
Definition: faults.cc:428
gem5::ArmISA::ArmFaultVals::offset64
FaultOffset offset64(ThreadContext *tc) override
Definition: faults.cc:978
gem5::ArmISA::syncVecElemsToRegs
void syncVecElemsToRegs(ThreadContext *tc)
Definition: utility.cc:1354
gem5::ArmISA::ArmFault::getFaultVAddr
virtual bool getFaultVAddr(Addr &va) const
Definition: faults.hh:258
gem5::ArmISA::MISCREG_VMPIDR
@ MISCREG_VMPIDR
Definition: misc.hh:235
gem5::ArmISA::Watchpoint::cm
bool cm
Definition: faults.hh:698
gem5::ArmISA::ArmFault::armPcOffset
virtual uint8_t armPcOffset(bool is_hyp)=0
gem5::ArmISA::SecureMonitorCall::iss
uint32_t iss() const override
Definition: faults.cc:907
gem5::ArmISA::UndefinedInstruction::routeToHyp
bool routeToHyp(ThreadContext *tc) const override
Definition: faults.cc:828
gem5::ArmISA::AbortFault::abortDisable
bool abortDisable(ThreadContext *tc) override
Definition: faults.cc:1212
gem5::ArmISA::UndefinedInstruction::invoke
void invoke(ThreadContext *tc, const StaticInstPtr &inst=nullStaticInstPtr) override
Definition: faults.cc:805
gem5::ArmISA::EL2Enabled
bool EL2Enabled(ThreadContext *tc)
Definition: utility.cc:264
gem5::ArmISA::SupervisorTrap::overrideEc
ExceptionClass overrideEc
Definition: faults.hh:403
gem5::PowerISA::AlignmentFault
Definition: faults.hh:82
gem5::ArmISA::MISCREG_SPSR_EL2
@ MISCREG_SPSR_EL2
Definition: misc.hh:626
gem5::ArmISA::DataAbort::srt
uint8_t srt
Definition: faults.hh:551
gem5::ArmISA::VirtualInterrupt::VirtualInterrupt
VirtualInterrupt()
Definition: faults.cc:1505
gem5::ArmISA::DataAbort::annotate
void annotate(AnnotationIDs id, uint64_t val) override
Definition: faults.cc:1429
gem5::ArmISA::ArmFault::SF
@ SF
Definition: faults.hh:146
gem5::bits
constexpr T bits(T val, unsigned first, unsigned last)
Extract the bitfield from position 'first' to 'last' (inclusive) from 'val' and right justify it.
Definition: bitfield.hh:76
compiler.hh
gem5::GenericAlignmentFault
Definition: faults.hh:128
gem5::ArmISA::EL3
@ EL3
Definition: types.hh:276
gem5::ArmISA::DataAbort::il
bool il(ThreadContext *tc) const override
Definition: faults.cc:1359
gem5::ArmISA::ArmFault::nextMode
virtual OperatingMode nextMode()=0
gem5::ArmISA::FastInterrupt::fiqDisable
bool fiqDisable(ThreadContext *tc) override
Definition: faults.cc:1539
gem5::ThreadContext::readMiscRegNoEffect
virtual RegVal readMiscRegNoEffect(RegIndex misc_reg) const =0
faults.hh
gem5::ArmISA::PrefetchAbort::iss
uint32_t iss() const override
Definition: faults.cc:1291
gem5::ArmISA::DataAbort::cm
uint8_t cm
Definition: faults.hh:552
gem5::ArmISA::MISCREG_SPSR_EL1
@ MISCREG_SPSR_EL1
Definition: misc.hh:613
gem5::ArmISA::COND_AL
@ COND_AL
Definition: cc.hh:98
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::ArmISA::SoftwareBreakpoint
Software Breakpoint (AArch64 only)
Definition: faults.hh:668
gem5::ArmISA::ArmFaultVals< Reset >::offset
FaultOffset offset(ThreadContext *tc) override
Definition: faults.cc:958
gem5::ArmISA::cc_reg::C
constexpr RegId C(CCRegClass, _CIdx)
gem5::ArmISA::SoftwareStepFault::iss
uint32_t iss() const override
Definition: faults.cc:1771
gem5::ArmISA::HypervisorCall::ec
ExceptionClass ec(ThreadContext *tc) const override
Syndrome methods.
Definition: faults.cc:945
gem5::ArmISA::MiscRegIndex
MiscRegIndex
Definition: misc.hh:59
gem5::ArmISA::HardwareBreakpoint::ec
ExceptionClass ec(ThreadContext *tc) const override
Syndrome methods.
Definition: faults.cc:1645
gem5::ArmISA::isSecure
bool isSecure(ThreadContext *tc)
Definition: utility.cc:73
gem5::ArmISA::va
Bitfield< 8 > va
Definition: misc_types.hh:276
gem5::FaultBase::invoke
virtual void invoke(ThreadContext *tc, const StaticInstPtr &inst=nullStaticInstPtr)
Definition: faults.cc:58
gem5::ArmISA::AbortFault::getFaultVAddr
bool getFaultVAddr(Addr &va) const override
Definition: faults.cc:1259
utility.hh
gem5::ArmISA::ExceptionClass
ExceptionClass
Definition: types.hh:300
gem5::ArmISA::SoftwareStepFault::routeToHyp
bool routeToHyp(ThreadContext *tc) const override
Definition: faults.cc:1751
full_system.hh
gem5::ArmISA::ArmFault::getFaultAddrReg64
MiscRegIndex getFaultAddrReg64() const
Definition: faults.cc:382
gem5::ArmISA::HardwareBreakpoint::HardwareBreakpoint
HardwareBreakpoint(Addr _vaddr, uint32_t _iss)
Definition: faults.cc:1631
gem5::ArmISA::Reset::getVector
Addr getVector(ThreadContext *tc) override
Definition: faults.cc:759
gem5::ArmISA::currEL
ExceptionLevel currEL(const ThreadContext *tc)
Returns the current Exception Level (EL) of the provided ThreadContext.
Definition: utility.cc:129
gem5::ArmISA::AbortFault< PrefetchAbort >::srcEncoded
uint8_t srcEncoded
Definition: faults.hh:486
gem5::ArmISA::ArmFault
Definition: faults.hh:64
gem5::ArmISA::AbortFault< DataAbort >::faultAddr
Addr faultAddr
The virtual address the fault occured at.
Definition: faults.hh:476
gem5::ArmISA::FaultOffset
Addr FaultOffset
Definition: faults.hh:60
gem5::X86ISA::ExtMachInst
Definition: types.hh:212
gem5::ArmISA::cc_reg::Ge
constexpr RegId Ge(CCRegClass, _GeIdx)
gem5::FullSystem
bool FullSystem
The FullSystem variable can be used to determine the current mode of simulation.
Definition: root.cc:220
gem5::MipsISA::FaultVals
MipsFaultBase::FaultVals FaultVals
Definition: faults.cc:46
gem5::ArmISA::ArmFault::aarch64FaultSources
static uint8_t aarch64FaultSources[NumFaultSources]
Encodings of the fault sources in AArch64 state.
Definition: faults.hh:130
gem5::ArmISA::MISCREG_SPSR_EL3
@ MISCREG_SPSR_EL3
Definition: misc.hh:633
gem5::ArmISA::SupervisorCall::overrideEc
ExceptionClass overrideEc
Definition: faults.hh:361
gem5::ArmISA::Watchpoint::Watchpoint
Watchpoint(ExtMachInst mach_inst, Addr vaddr, bool _write, bool _cm)
Definition: faults.cc:1681
gem5::ArmISA::EC_SOFTWARE_STEP_LOWER_EL
@ EC_SOFTWARE_STEP_LOWER_EL
Definition: types.hh:343
gem5::ArmISA::PrefetchAbort::routeToHyp
bool routeToHyp(ThreadContext *tc) const override
Definition: faults.cc:1315
gem5::ArmISA::EC_PREFETCH_ABORT_CURR_EL
@ EC_PREFETCH_ABORT_CURR_EL
Definition: types.hh:329
gem5::ArmISA::EL0
@ EL0
Definition: types.hh:273
panic_if
#define panic_if(cond,...)
Conditional panic macro that checks the supplied condition and only panics if the condition is true a...
Definition: logging.hh:204
gem5::ArmSystem
Definition: system.hh:91
gem5::ArmISA::SupervisorCall::routeToHyp
bool routeToHyp(ThreadContext *tc) const override
Definition: faults.cc:884
gem5::ArmISA::ArmFault::invoke64
void invoke64(ThreadContext *tc, const StaticInstPtr &inst=nullStaticInstPtr)
Definition: faults.cc:637
gem5::ArmISA::ArmFault::invoke
void invoke(ThreadContext *tc, const StaticInstPtr &inst=nullStaticInstPtr) override
Definition: faults.cc:477
gem5::ArmISA::MISCREG_HCR
@ MISCREG_HCR
Definition: misc.hh:249
gem5::ArmISA::SupervisorTrap::routeToHyp
bool routeToHyp(ThreadContext *tc) const override
Definition: faults.cc:1034
gem5::ArmISA::syncVecRegsToElems
void syncVecRegsToElems(ThreadContext *tc)
Definition: utility.cc:1339
gem5::ArmISA::DataAbort::isv
bool isv
Definition: faults.hh:548
gem5::ArmISA::MISCREG_TTBCR_NS
@ MISCREG_TTBCR_NS
Definition: misc.hh:262
gem5::ArmISA::Watchpoint::annotate
void annotate(AnnotationIDs id, uint64_t val) override
Definition: faults.cc:1718
gem5::ArmISA::VectorCatch::isVCMatch
bool isVCMatch() const
Definition: self_debug.hh:257
gem5::ArmISA::VectorCatch
Definition: self_debug.hh:242
gem5::ArmISA::ArmFault::AlignmentFault
@ AlignmentFault
Definition: faults.hh:97
gem5::ArmISA::AbortFault::isMMUFault
bool isMMUFault() const
Definition: faults.cc:1242
gem5::ArmISA::ArmFault::getVector
virtual Addr getVector(ThreadContext *tc)
Definition: faults.cc:311
gem5::ArmISA::ArmFault::isResetSPSR
bool isResetSPSR()
Definition: faults.hh:234
gem5::ArmISA::MISCREG_SPSR_SVC
@ MISCREG_SPSR_SVC
Definition: misc.hh:65
gem5::ArmISA::ArmFault::CM
@ CM
Definition: faults.hh:139
base.hh
gem5::ArmISA::EC_PREFETCH_ABORT_LOWER_EL
@ EC_PREFETCH_ABORT_LOWER_EL
Definition: types.hh:327
gem5::ArmISA::Watchpoint::iss
uint32_t iss() const override
Definition: faults.cc:1688
gem5::ArmISA::AbortFault::invoke
void invoke(ThreadContext *tc, const StaticInstPtr &inst=nullStaticInstPtr) override
Definition: faults.cc:1068
gem5::ArmISA::HighVecs
const uint32_t HighVecs
Definition: faults.cc:63
gem5::ArmISA::ArmFault::span
bool span
Definition: faults.hh:85
gem5::PowerISA::int_reg::Lr
constexpr RegId Lr(IntRegClass, _LrIdx)
gem5::ArmISA::EC_HW_BREAKPOINT_CURR_EL
@ EC_HW_BREAKPOINT_CURR_EL
Definition: types.hh:341
gem5::ArmISA::ArmFault::TranslationLL
@ TranslationLL
Definition: faults.hh:101
gem5::ArmISA::AbortFault< PrefetchAbort >::stage2
bool stage2
Definition: faults.hh:487
gem5::ArmISA::ArmFault::WPOINT_CM
@ WPOINT_CM
Definition: faults.hh:162
gem5::ArmISA::ConditionCode
ConditionCode
Definition: cc.hh:82
gem5::ArmISA::ArmFaultVals::ec
ExceptionClass ec(ThreadContext *tc) const override
Syndrome methods.
Definition: faults.hh:304
gem5::ThreadContext::setMiscReg
virtual void setMiscReg(RegIndex misc_reg, RegVal val)=0
static_inst.hh
gem5::ArmISA::ISA::getSelfDebug
SelfDebug * getSelfDebug() const
Definition: isa.hh:629
gem5::ArmISA::ArmFault::ec
virtual ExceptionClass ec(ThreadContext *tc) const =0
gem5::ArmISA::SoftwareBreakpoint::SoftwareBreakpoint
SoftwareBreakpoint(ExtMachInst mach_inst, uint32_t _iss)
Definition: faults.cc:1611
gem5::MipsISA::pc
Bitfield< 4 > pc
Definition: pra_constants.hh:243
gem5::ArmISA::ArmFault::AnnotationIDs
AnnotationIDs
Definition: faults.hh:132
gem5::ArmISA::MISCREG_SCR
@ MISCREG_SCR
Definition: misc.hh:244
gem5::ArmISA::MISCREG_ESR_EL3
@ MISCREG_ESR_EL3
Definition: misc.hh:649
gem5::ArmISA::MISCREG_ELR_EL2
@ MISCREG_ELR_EL2
Definition: misc.hh:627
gem5::ArmISA::longDescFormatInUse
bool longDescFormatInUse(ThreadContext *tc)
Definition: utility.cc:136
gem5::ArmISA::EC_DATA_ABORT_TO_HYP
@ EC_DATA_ABORT_TO_HYP
Definition: types.hh:331
gem5::ArmISA::ArmFault::annotate
virtual void annotate(AnnotationIDs id, uint64_t val)
Definition: faults.hh:239
gem5::ArmISA::EC_PC_ALIGNMENT
@ EC_PC_ALIGNMENT
Definition: types.hh:330
gem5::ArmSystem::resetAddr
Addr resetAddr() const
Returns the reset address if the highest implemented exception level is 64 bits (ARMv8)
Definition: system.hh:198
gem5::ArmISA::ArmFault::il
virtual bool il(ThreadContext *tc) const =0
gem5::ArmISA::ArmFault::AccessFlagLL
@ AccessFlagLL
Definition: faults.hh:102
gem5::ArmISA::SoftwareStepFault::ec
ExceptionClass ec(ThreadContext *tc) const override
Syndrome methods.
Definition: faults.cc:1761
gem5::ArmISA::UndefinedInstruction::iss
uint32_t iss() const override
Definition: faults.cc:836
gem5::ArmISA::MISCREG_SPSR_ABT
@ MISCREG_SPSR_ABT
Definition: misc.hh:67
gem5::ArmISA::EC_INVALID
@ EC_INVALID
Definition: types.hh:302
gem5::ArmISA::MISCREG_ELR_HYP
@ MISCREG_ELR_HYP
Definition: misc.hh:70
gem5::ArmISA::FastInterrupt::routeToMonitor
bool routeToMonitor(ThreadContext *tc) const override
Definition: faults.cc:1509
gem5::ArmISA::ArmFault::S1PTW
@ S1PTW
Definition: faults.hh:134
gem5::ArmISA::Reset::invoke
void invoke(ThreadContext *tc, const StaticInstPtr &inst=nullStaticInstPtr) override
Definition: faults.cc:777
gem5::ArmISA::sd
Bitfield< 4 > sd
Definition: misc_types.hh:827
gem5::ArmISA::MISCREG_HVBAR
@ MISCREG_HVBAR
Definition: misc.hh:398
gem5::ThreadContext::getCpuPtr
virtual BaseCPU * getCpuPtr()=0
gem5::ArmISA::cm
Bitfield< 13 > cm
Definition: misc_types.hh:429
gem5::ArmISA::ArmSev::invoke
void invoke(ThreadContext *tc, const StaticInstPtr &inst=nullStaticInstPtr) override
Definition: faults.cc:1782
gem5::ArmISA::MISCREG_VBAR
@ MISCREG_VBAR
Definition: misc.hh:392
gem5::ArmISA::ArmFault::toMode
OperatingMode toMode
Definition: faults.hh:77
gem5::ArmISA::ArmFault::routeToHyp
virtual bool routeToHyp(ThreadContext *tc) const
Definition: faults.hh:244
gem5::ThreadContext::clearArchRegs
virtual void clearArchRegs()=0
gem5::ArmISA::MISCREG_HSR
@ MISCREG_HSR
Definition: misc.hh:283
gem5::ArmISA::MISCREG_SEV_MAILBOX
@ MISCREG_SEV_MAILBOX
Definition: misc.hh:92
gem5::ArmISA::ArmFault::SRT
@ SRT
Definition: faults.hh:138
gem5::ArmISA::HardwareBreakpoint::invoke
void invoke(ThreadContext *tc, const StaticInstPtr &inst=nullStaticInstPtr) override
Definition: faults.cc:1655
gem5::ThreadContext::threadId
virtual int threadId() const =0
gem5::ArmISA::DataAbort::sse
uint8_t sse
Definition: faults.hh:550
trace.hh
gem5::ArmISA::MISCREG_ELR_EL3
@ MISCREG_ELR_EL3
Definition: misc.hh:634
gem5::ArmISA::ArmFault::vectorCatch
bool vectorCatch(ThreadContext *tc, const StaticInstPtr &inst)
Definition: faults.cc:733
gem5::ArmISA::Interrupt::routeToHyp
bool routeToHyp(ThreadContext *tc) const override
Definition: faults.cc:1488
gem5::ArmISA::AbortFault< DataAbort >::write
bool write
Definition: faults.hh:483
gem5::MipsISA::vaddr
vaddr
Definition: pra_constants.hh:278
gem5::ArmISA::PrefetchAbort::ec
ExceptionClass ec(ThreadContext *tc) const override
Syndrome methods.
Definition: faults.cc:1266
gem5::ArmISA::DataAbort::routeToHyp
bool routeToHyp(ThreadContext *tc) const override
Definition: faults.cc:1377
gem5::ArmISA::HypervisorCall::routeToMonitor
bool routeToMonitor(ThreadContext *tc) const override
Definition: faults.cc:933
gem5::ArmISA::DataAbort::ar
bool ar
Definition: faults.hh:556
gem5::ArmISA::IllegalInstSetStateFault::routeToHyp
bool routeToHyp(ThreadContext *tc) const override
Definition: faults.cc:1828
gem5::ArmISA::SystemError::invoke
void invoke(ThreadContext *tc, const StaticInstPtr &inst=nullStaticInstPtr) override
Definition: faults.cc:1584
gem5::ArmISA::EC_SMC_TO_HYP
@ EC_SMC_TO_HYP
Definition: types.hh:319
self_debug.hh
gem5::ArmISA::ArmFault::machInst
ExtMachInst machInst
Definition: faults.hh:67
gem5::ArmSystem::haveEL
static bool haveEL(ThreadContext *tc, ArmISA::ExceptionLevel el)
Return true if the system implements a specific exception level.
Definition: system.cc:131
gem5::ArmISA::MODE_ABORT
@ MODE_ABORT
Definition: types.hh:293
gem5::ArmISA::MISCREG_HCR_EL2
@ MISCREG_HCR_EL2
Definition: misc.hh:587
gem5::ArmISA::SPAlignmentFault::routeToHyp
bool routeToHyp(ThreadContext *tc) const override
Definition: faults.cc:1573
gem5::ArmISA::EC_SOFTWARE_STEP_CURR_EL
@ EC_SOFTWARE_STEP_CURR_EL
Definition: types.hh:344
gem5::ArmISA::ArmFault::fromMode
OperatingMode fromMode
Definition: faults.hh:76
gem5::ArmISA::EC_SVC_64
@ EC_SVC_64
Definition: types.hh:321
gem5::ArmISA::MISCREG_FAR_EL2
@ MISCREG_FAR_EL2
Definition: misc.hh:652
gem5::ArmISA::MISCREG_FAR_EL3
@ MISCREG_FAR_EL3
Definition: misc.hh:654
gem5::ArmISA::SupervisorCall::ec
ExceptionClass ec(ThreadContext *tc) const override
Syndrome methods.
Definition: faults.cc:892
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: gpu_translation_state.hh:37
gem5::ArmISA::ArmFault::invoke32
void invoke32(ThreadContext *tc, const StaticInstPtr &inst=nullStaticInstPtr)
Definition: faults.cc:504
gem5::ArmISA::MISCREG_HPFAR_EL2
@ MISCREG_HPFAR_EL2
Definition: misc.hh:653
gem5::ArmISA::ArmFault::routeToMonitor
virtual bool routeToMonitor(ThreadContext *tc) const =0
gem5::ArmISA::IllegalInstSetStateFault::IllegalInstSetStateFault
IllegalInstSetStateFault()
Definition: faults.cc:1824
gem5::ArmISA::itstate
Bitfield< 55, 48 > itstate
Definition: types.hh:70
gem5::ArmISA::AbortFault< PrefetchAbort >::source
uint8_t source
Definition: faults.hh:485
gem5::ArmISA::EC_HW_BREAKPOINT
@ EC_HW_BREAKPOINT
Definition: types.hh:339
gem5::ArmISA::MISCREG_HPFAR
@ MISCREG_HPFAR
Definition: misc.hh:292
gem5::ArmISA::MISCREG_ESR_EL1
@ MISCREG_ESR_EL1
Definition: misc.hh:640
gem5::ArmISA::MISCREG_VBAR_EL1
@ MISCREG_VBAR_EL1
Definition: misc.hh:737
gem5::ArmISA::ArmFault::longDescFaultSources
static uint8_t longDescFaultSources[NumFaultSources]
Encodings of the fault sources when the long-desc.
Definition: faults.hh:128
gem5::ArmISA::AbortFault
Definition: faults.hh:467
gem5::ArmISA::ArmFault::SAS
@ SAS
Definition: faults.hh:136
gem5::ArmISA::HaveExt
bool HaveExt(ThreadContext *tc, ArmExtension ext)
Returns true if the provided ThreadContext supports the ArmExtension passed as a second argument.
Definition: utility.cc:229
gem5::ArmISA::MISCREG_SPSR_HYP
@ MISCREG_SPSR_HYP
Definition: misc.hh:68
gem5::ArmISA::ArmStaticInst::annotateFault
virtual void annotateFault(ArmFault *fault)
Definition: static_inst.hh:543
thread_context.hh
gem5::ArmISA::ArmFault::UnknownTran
@ UnknownTran
Definition: faults.hh:154
gem5::ArmISA::OperatingMode
OperatingMode
Definition: types.hh:279
gem5::ArmISA::ArmFault::OVA
@ OVA
Definition: faults.hh:135
gem5::ArmISA::EC_STACK_PTR_ALIGNMENT
@ EC_STACK_PTR_ALIGNMENT
Definition: types.hh:335
gem5::ArmISA::EC_WATCHPOINT_CURR_EL
@ EC_WATCHPOINT_CURR_EL
Definition: types.hh:347
gem5::ArmISA::SoftwareStepFault::stepped
bool stepped
Definition: faults.hh:717
gem5::Workload::syscall
virtual void syscall(ThreadContext *tc)
Definition: workload.hh:109
gem5::ArmISA::AbortFault< PrefetchAbort >::s1ptw
bool s1ptw
Definition: faults.hh:488
gem5::ArmISA::VirtualFastInterrupt::VirtualFastInterrupt
VirtualFastInterrupt()
Definition: faults.cc:1550
gem5::ArmISA::SecureMonitorTrap::overrideEc
ExceptionClass overrideEc
Definition: faults.hh:423
gem5::ArmISA::SoftwareStepFault::SoftwareStepFault
SoftwareStepFault(ExtMachInst mach_inst, bool is_ldx, bool stepped)
Definition: faults.cc:1742
gem5::ArmISA::EC_DATA_ABORT_CURR_EL
@ EC_DATA_ABORT_CURR_EL
Definition: types.hh:334
gem5::ArmISA::getMPIDR
RegVal getMPIDR(ArmSystem *arm_sys, ThreadContext *tc)
This helper function is returning the value of MPIDR_EL1.
Definition: utility.cc:171
gem5::ArmISA::Interrupt::abortDisable
bool abortDisable(ThreadContext *tc) override
Definition: faults.cc:1496
gem5::ArmISA::ExceptionLevel
ExceptionLevel
Definition: types.hh:271
panic
#define panic(...)
This implements a cprintf based panic() function.
Definition: logging.hh:178
gem5::ArmISA::Watchpoint::ec
ExceptionClass ec(ThreadContext *tc) const override
Syndrome methods.
Definition: faults.cc:1733
gem5::ArmISA::mode
Bitfield< 4, 0 > mode
Definition: misc_types.hh:74
gem5::ArmISA::HypervisorCall::HypervisorCall
HypervisorCall(ExtMachInst mach_inst, uint32_t _imm)
Definition: faults.cc:926
gem5::ArmISA::INT_SEV
@ INT_SEV
Definition: interrupts.hh:65
gem5::ThreadContext::setMiscRegNoEffect
virtual void setMiscRegNoEffect(RegIndex misc_reg, RegVal val)=0
gem5::ArmISA::ArmFault::fiqDisable
virtual bool fiqDisable(ThreadContext *tc)=0
gem5::ThreadContext::setReg
virtual void setReg(const RegId &reg, RegVal val)
Definition: thread_context.cc:183
gem5::ArmISA::Watchpoint::write
bool write
Definition: faults.hh:697
gem5::ArmISA::MISCREG_SPSR_UND
@ MISCREG_SPSR_UND
Definition: misc.hh:69

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