gem5  v21.1.0.2
faults.cc
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41 
42 #include "arch/arm/faults.hh"
43 
45 #include "arch/arm/interrupts.hh"
46 #include "arch/arm/isa.hh"
47 #include "arch/arm/self_debug.hh"
48 #include "arch/arm/system.hh"
49 #include "arch/arm/utility.hh"
50 #include "base/compiler.hh"
51 #include "base/trace.hh"
52 #include "cpu/base.hh"
53 #include "cpu/thread_context.hh"
54 #include "debug/Faults.hh"
55 #include "sim/full_system.hh"
56 
57 namespace gem5
58 {
59 
60 namespace ArmISA
61 {
62 
63 const uint32_t HighVecs = 0xFFFF0000;
64 
66  0x01, // AlignmentFault
67  0x04, // InstructionCacheMaintenance
68  0xff, // SynchExtAbtOnTranslTableWalkL0 (INVALID)
69  0x0c, // SynchExtAbtOnTranslTableWalkL1
70  0x0e, // SynchExtAbtOnTranslTableWalkL2
71  0xff, // SynchExtAbtOnTranslTableWalkL3 (INVALID)
72  0xff, // SynchPtyErrOnTranslTableWalkL0 (INVALID)
73  0x1c, // SynchPtyErrOnTranslTableWalkL1
74  0x1e, // SynchPtyErrOnTranslTableWalkL2
75  0xff, // SynchPtyErrOnTranslTableWalkL3 (INVALID)
76  0xff, // TranslationL0 (INVALID)
77  0x05, // TranslationL1
78  0x07, // TranslationL2
79  0xff, // TranslationL3 (INVALID)
80  0xff, // AccessFlagL0 (INVALID)
81  0x03, // AccessFlagL1
82  0x06, // AccessFlagL2
83  0xff, // AccessFlagL3 (INVALID)
84  0xff, // DomainL0 (INVALID)
85  0x09, // DomainL1
86  0x0b, // DomainL2
87  0xff, // DomainL3 (INVALID)
88  0xff, // PermissionL0 (INVALID)
89  0x0d, // PermissionL1
90  0x0f, // PermissionL2
91  0xff, // PermissionL3 (INVALID)
92  0x02, // DebugEvent
93  0x08, // SynchronousExternalAbort
94  0x10, // TLBConflictAbort
95  0x19, // SynchPtyErrOnMemoryAccess
96  0x16, // AsynchronousExternalAbort
97  0x18, // AsynchPtyErrOnMemoryAccess
98  0xff, // AddressSizeL0 (INVALID)
99  0xff, // AddressSizeL1 (INVALID)
100  0xff, // AddressSizeL2 (INVALID)
101  0xff, // AddressSizeL3 (INVALID)
102  0x40, // PrefetchTLBMiss
103  0x80 // PrefetchUncacheable
104 };
105 
106 static_assert(sizeof(ArmFault::shortDescFaultSources) ==
108  "Invalid size of ArmFault::shortDescFaultSources[]");
109 
110 uint8_t ArmFault::longDescFaultSources[] = {
111  0x21, // AlignmentFault
112  0xff, // InstructionCacheMaintenance (INVALID)
113  0xff, // SynchExtAbtOnTranslTableWalkL0 (INVALID)
114  0x15, // SynchExtAbtOnTranslTableWalkL1
115  0x16, // SynchExtAbtOnTranslTableWalkL2
116  0x17, // SynchExtAbtOnTranslTableWalkL3
117  0xff, // SynchPtyErrOnTranslTableWalkL0 (INVALID)
118  0x1d, // SynchPtyErrOnTranslTableWalkL1
119  0x1e, // SynchPtyErrOnTranslTableWalkL2
120  0x1f, // SynchPtyErrOnTranslTableWalkL3
121  0xff, // TranslationL0 (INVALID)
122  0x05, // TranslationL1
123  0x06, // TranslationL2
124  0x07, // TranslationL3
125  0xff, // AccessFlagL0 (INVALID)
126  0x09, // AccessFlagL1
127  0x0a, // AccessFlagL2
128  0x0b, // AccessFlagL3
129  0xff, // DomainL0 (INVALID)
130  0x3d, // DomainL1
131  0x3e, // DomainL2
132  0xff, // DomainL3 (RESERVED)
133  0xff, // PermissionL0 (INVALID)
134  0x0d, // PermissionL1
135  0x0e, // PermissionL2
136  0x0f, // PermissionL3
137  0x22, // DebugEvent
138  0x10, // SynchronousExternalAbort
139  0x30, // TLBConflictAbort
140  0x18, // SynchPtyErrOnMemoryAccess
141  0x11, // AsynchronousExternalAbort
142  0x19, // AsynchPtyErrOnMemoryAccess
143  0xff, // AddressSizeL0 (INVALID)
144  0xff, // AddressSizeL1 (INVALID)
145  0xff, // AddressSizeL2 (INVALID)
146  0xff, // AddressSizeL3 (INVALID)
147  0x40, // PrefetchTLBMiss
148  0x80 // PrefetchUncacheable
149 };
150 
151 static_assert(sizeof(ArmFault::longDescFaultSources) ==
153  "Invalid size of ArmFault::longDescFaultSources[]");
154 
155 uint8_t ArmFault::aarch64FaultSources[] = {
156  0x21, // AlignmentFault
157  0xff, // InstructionCacheMaintenance (INVALID)
158  0x14, // SynchExtAbtOnTranslTableWalkL0
159  0x15, // SynchExtAbtOnTranslTableWalkL1
160  0x16, // SynchExtAbtOnTranslTableWalkL2
161  0x17, // SynchExtAbtOnTranslTableWalkL3
162  0x1c, // SynchPtyErrOnTranslTableWalkL0
163  0x1d, // SynchPtyErrOnTranslTableWalkL1
164  0x1e, // SynchPtyErrOnTranslTableWalkL2
165  0x1f, // SynchPtyErrOnTranslTableWalkL3
166  0x04, // TranslationL0
167  0x05, // TranslationL1
168  0x06, // TranslationL2
169  0x07, // TranslationL3
170  0x08, // AccessFlagL0
171  0x09, // AccessFlagL1
172  0x0a, // AccessFlagL2
173  0x0b, // AccessFlagL3
174  // @todo: Section & Page Domain Fault in AArch64?
175  0xff, // DomainL0 (INVALID)
176  0xff, // DomainL1 (INVALID)
177  0xff, // DomainL2 (INVALID)
178  0xff, // DomainL3 (INVALID)
179  0x0c, // PermissionL0
180  0x0d, // PermissionL1
181  0x0e, // PermissionL2
182  0x0f, // PermissionL3
183  0x22, // DebugEvent
184  0x10, // SynchronousExternalAbort
185  0x30, // TLBConflictAbort
186  0x18, // SynchPtyErrOnMemoryAccess
187  0xff, // AsynchronousExternalAbort (INVALID)
188  0xff, // AsynchPtyErrOnMemoryAccess (INVALID)
189  0x00, // AddressSizeL0
190  0x01, // AddressSizeL1
191  0x02, // AddressSizeL2
192  0x03, // AddressSizeL3
193  0x40, // PrefetchTLBMiss
194  0x80 // PrefetchUncacheable
195 };
196 
197 static_assert(sizeof(ArmFault::aarch64FaultSources) ==
199  "Invalid size of ArmFault::aarch64FaultSources[]");
200 
201 // Fields: name, offset, cur{ELT,ELH}Offset, lowerEL{64,32}Offset, next mode,
202 // {ARM, Thumb, ARM_ELR, Thumb_ELR} PC offset, hyp trap,
203 // {A, F} disable, class, stat
205  // Some dummy values (the reset vector has an IMPLEMENTATION DEFINED
206  // location in AArch64)
207  "Reset", 0x000, 0x000, 0x000, 0x000, 0x000, MODE_SVC,
208  0, 0, 0, 0, false, true, true, EC_UNKNOWN
209 );
211  "Undefined Instruction", 0x004, 0x000, 0x200, 0x400, 0x600, MODE_UNDEFINED,
212  4, 2, 0, 0, true, false, false, EC_UNKNOWN
213 );
215  "Supervisor Call", 0x008, 0x000, 0x200, 0x400, 0x600, MODE_SVC,
216  4, 2, 4, 2, true, false, false, EC_SVC_TO_HYP
217 );
219  "Secure Monitor Call", 0x008, 0x000, 0x200, 0x400, 0x600, MODE_MON,
220  4, 4, 4, 4, false, true, true, EC_SMC_TO_HYP
221 );
223  "Hypervisor Call", 0x008, 0x000, 0x200, 0x400, 0x600, MODE_HYP,
224  4, 4, 4, 4, true, false, false, EC_HVC
225 );
227  "Prefetch Abort", 0x00C, 0x000, 0x200, 0x400, 0x600, MODE_ABORT,
228  4, 4, 0, 0, true, true, false, EC_PREFETCH_ABORT_TO_HYP
229 );
231  "Data Abort", 0x010, 0x000, 0x200, 0x400, 0x600, MODE_ABORT,
232  8, 8, 0, 0, true, true, false, EC_DATA_ABORT_TO_HYP
233 );
235  "Virtual Data Abort", 0x010, 0x000, 0x200, 0x400, 0x600, MODE_ABORT,
236  8, 8, 0, 0, true, true, false, EC_INVALID
237 );
239  // @todo: double check these values
240  "Hypervisor Trap", 0x014, 0x000, 0x200, 0x400, 0x600, MODE_HYP,
241  0, 0, 0, 0, false, false, false, EC_UNKNOWN
242 );
244  "Secure Monitor Trap", 0x004, 0x000, 0x200, 0x400, 0x600, MODE_MON,
245  4, 2, 0, 0, false, false, false, EC_UNKNOWN
246 );
248  "IRQ", 0x018, 0x080, 0x280, 0x480, 0x680, MODE_IRQ,
249  4, 4, 0, 0, false, true, false, EC_UNKNOWN
250 );
252  "Virtual IRQ", 0x018, 0x080, 0x280, 0x480, 0x680, MODE_IRQ,
253  4, 4, 0, 0, false, true, false, EC_INVALID
254 );
256  "FIQ", 0x01C, 0x100, 0x300, 0x500, 0x700, MODE_FIQ,
257  4, 4, 0, 0, false, true, true, EC_UNKNOWN
258 );
260  "Virtual FIQ", 0x01C, 0x100, 0x300, 0x500, 0x700, MODE_FIQ,
261  4, 4, 0, 0, false, true, true, EC_INVALID
262 );
264  "Illegal Inst Set State Fault", 0x004, 0x000, 0x200, 0x400, 0x600, MODE_UNDEFINED,
265  4, 2, 0, 0, true, false, false, EC_ILLEGAL_INST
266 );
268  // Some dummy values (SupervisorTrap is AArch64-only)
269  "Supervisor Trap", 0x014, 0x000, 0x200, 0x400, 0x600, MODE_SVC,
270  0, 0, 0, 0, false, false, false, EC_UNKNOWN
271 );
273  // Some dummy values (PCAlignmentFault is AArch64-only)
274  "PC Alignment Fault", 0x000, 0x000, 0x200, 0x400, 0x600, MODE_SVC,
275  0, 0, 0, 0, true, false, false, EC_PC_ALIGNMENT
276 );
278  // Some dummy values (SPAlignmentFault is AArch64-only)
279  "SP Alignment Fault", 0x000, 0x000, 0x200, 0x400, 0x600, MODE_SVC,
280  0, 0, 0, 0, true, false, false, EC_STACK_PTR_ALIGNMENT
281 );
283  // Some dummy values (SError is AArch64-only)
284  "SError", 0x000, 0x180, 0x380, 0x580, 0x780, MODE_SVC,
285  0, 0, 0, 0, false, true, true, EC_SERROR
286 );
288  // Some dummy values (SoftwareBreakpoint is AArch64-only)
289  "Software Breakpoint", 0x000, 0x000, 0x200, 0x400, 0x600, MODE_SVC,
290  0, 0, 0, 0, true, false, false, EC_SOFTWARE_BREAKPOINT
291 );
293  "Hardware Breakpoint", 0x000, 0x000, 0x200, 0x400, 0x600, MODE_SVC,
294  0, 0, 0, 0, true, false, false, EC_HW_BREAKPOINT
295 );
297  "Watchpoint", 0x000, 0x000, 0x200, 0x400, 0x600, MODE_SVC,
298  0, 0, 0, 0, true, false, false, EC_WATCHPOINT
299 );
301  "SoftwareStep", 0x000, 0x000, 0x200, 0x400, 0x600, MODE_SVC,
302  0, 0, 0, 0, true, false, false, EC_SOFTWARE_STEP
303 );
305  // Some dummy values
306  "ArmSev Flush", 0x000, 0x000, 0x000, 0x000, 0x000, MODE_SVC,
307  0, 0, 0, 0, false, true, true, EC_UNKNOWN
308 );
309 
310 Addr
312 {
313  Addr base;
314 
315  // Check for invalid modes
316  CPSR cpsr = tc->readMiscRegNoEffect(MISCREG_CPSR);
317  assert(ArmSystem::haveSecurity(tc) || cpsr.mode != MODE_MON);
318  assert(ArmSystem::haveVirtualization(tc) || cpsr.mode != MODE_HYP);
319 
320  switch (cpsr.mode)
321  {
322  case MODE_MON:
324  break;
325  case MODE_HYP:
327  break;
328  default:
329  SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR);
330  if (sctlr.v) {
331  base = HighVecs;
332  } else {
334  tc->readMiscReg(MISCREG_VBAR) : 0;
335  }
336  break;
337  }
338 
339  return base + offset(tc);
340 }
341 
342 Addr
344 {
345  Addr vbar;
346  switch (toEL) {
347  case EL3:
348  assert(ArmSystem::haveSecurity(tc));
349  vbar = tc->readMiscReg(MISCREG_VBAR_EL3);
350  break;
351  case EL2:
352  assert(ArmSystem::haveVirtualization(tc));
353  vbar = tc->readMiscReg(MISCREG_VBAR_EL2);
354  break;
355  case EL1:
356  vbar = tc->readMiscReg(MISCREG_VBAR_EL1);
357  break;
358  default:
359  panic("Invalid target exception level");
360  break;
361  }
362  return vbar + offset64(tc);
363 }
364 
367 {
368  switch (toEL) {
369  case EL1:
370  return MISCREG_ESR_EL1;
371  case EL2:
372  return MISCREG_ESR_EL2;
373  case EL3:
374  return MISCREG_ESR_EL3;
375  default:
376  panic("Invalid exception level");
377  break;
378  }
379 }
380 
383 {
384  switch (toEL) {
385  case EL1:
386  return MISCREG_FAR_EL1;
387  case EL2:
388  return MISCREG_FAR_EL2;
389  case EL3:
390  return MISCREG_FAR_EL3;
391  default:
392  panic("Invalid exception level");
393  break;
394  }
395 }
396 
397 void
399 {
400  uint32_t value;
401  uint32_t exc_class = (uint32_t) ec(tc);
402  uint32_t issVal = iss();
403 
404  assert(!from64 || ArmSystem::highestELIs64(tc));
405 
406  value = exc_class << 26;
407 
408  // HSR.IL not valid for Prefetch Aborts (0x20, 0x21) and Data Aborts (0x24,
409  // 0x25) for which the ISS information is not valid (ARMv7).
410  // @todo: ARMv8 revises AArch32 functionality: when HSR.IL is not
411  // valid it is treated as RES1.
412  if (to64) {
413  value |= 1 << 25;
414  } else if ((bits(exc_class, 5, 3) != 4) ||
415  (bits(exc_class, 2) && bits(issVal, 24))) {
416  if (!machInst.thumb || machInst.bigThumb)
417  value |= 1 << 25;
418  }
419  // Condition code valid for EC[5:4] nonzero
420  if (!from64 && ((bits(exc_class, 5, 4) == 0) &&
421  (bits(exc_class, 3, 0) != 0))) {
422  if (!machInst.thumb) {
423  uint32_t cond;
424  ConditionCode condCode = (ConditionCode) (uint32_t) machInst.condCode;
425  // If its on unconditional instruction report with a cond code of
426  // 0xE, ie the unconditional code
427  cond = (condCode == COND_UC) ? COND_AL : condCode;
428  value |= cond << 20;
429  value |= 1 << 24;
430  }
431  value |= bits(issVal, 19, 0);
432  } else {
433  value |= issVal;
434  }
435  tc->setMiscReg(syndrome_reg, value);
436 }
437 
438 void
440 {
441  CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
442 
443  // Determine source exception level and mode
444  fromMode = (OperatingMode) (uint8_t) cpsr.mode;
446  if (opModeIs64(fromMode))
447  from64 = true;
448 
449  // Determine target exception level (aarch64) or target execution
450  // mode (aarch32).
451  if (ArmSystem::haveSecurity(tc) && routeToMonitor(tc)) {
452  toMode = MODE_MON;
453  toEL = EL3;
454  } else if (ArmSystem::haveVirtualization(tc) && routeToHyp(tc)) {
455  toMode = MODE_HYP;
456  toEL = EL2;
457  hypRouted = true;
458  } else {
459  toMode = nextMode();
461  }
462 
463  if (fromEL > toEL)
464  toEL = fromEL;
465 
466  // Check for Set Priviledge Access Never, if PAN is supported
467  AA64MMFR1 mmfr1 = tc->readMiscReg(MISCREG_ID_AA64MMFR1_EL1);
468  if (mmfr1.pan) {
469  if (toEL == EL1) {
470  const SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR_EL1);
471  span = !sctlr.span;
472  }
473 
474  const HCR hcr = tc->readMiscRegNoEffect(MISCREG_HCR_EL2);
475  if (toEL == EL2 && hcr.e2h && hcr.tge) {
476  const SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR_EL2);
477  span = !sctlr.span;
478  }
479  }
480 
481  to64 = ELIs64(tc, toEL);
482 
483  // The fault specific informations have been updated; it is
484  // now possible to use them inside the fault.
485  faultUpdated = true;
486 }
487 
488 void
490 {
491  // Update fault state informations, like the starting mode (aarch32)
492  // or EL (aarch64) and the ending mode or EL.
493  // From the update function we are also evaluating if the fault must
494  // be handled in AArch64 mode (to64).
495  update(tc);
496 
497  if (to64) {
498  // Invoke exception handler in AArch64 state
499  invoke64(tc, inst);
500  return;
501  }
502 
503  if (vectorCatch(tc, inst))
504  return;
505 
506  // ARMv7 (ARM ARM issue C B1.9)
507 
508  bool have_security = ArmSystem::haveSecurity(tc);
509 
510  FaultBase::invoke(tc);
511  if (!FullSystem)
512  return;
513  countStat()++;
514 
515  SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR);
516  SCR scr = tc->readMiscReg(MISCREG_SCR);
517  CPSR saved_cpsr = tc->readMiscReg(MISCREG_CPSR);
518  saved_cpsr.nz = tc->readCCReg(CCREG_NZ);
519  saved_cpsr.c = tc->readCCReg(CCREG_C);
520  saved_cpsr.v = tc->readCCReg(CCREG_V);
521  saved_cpsr.ge = tc->readCCReg(CCREG_GE);
522 
523  GEM5_VAR_USED Addr curPc = tc->pcState().pc();
524  ITSTATE it = tc->pcState().itstate();
525  saved_cpsr.it2 = it.top6;
526  saved_cpsr.it1 = it.bottom2;
527 
528  // if we have a valid instruction then use it to annotate this fault with
529  // extra information. This is used to generate the correct fault syndrome
530  // information
531  GEM5_VAR_USED ArmStaticInst *arm_inst = instrAnnotate(inst);
532 
533  // Ensure Secure state if initially in Monitor mode
534  if (have_security && saved_cpsr.mode == MODE_MON) {
535  SCR scr = tc->readMiscRegNoEffect(MISCREG_SCR);
536  if (scr.ns) {
537  scr.ns = 0;
539  }
540  }
541 
542  CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
543  cpsr.mode = toMode;
544 
545  // some bits are set differently if we have been routed to hyp mode
546  if (cpsr.mode == MODE_HYP) {
547  SCTLR hsctlr = tc->readMiscReg(MISCREG_HSCTLR);
548  cpsr.t = hsctlr.te;
549  cpsr.e = hsctlr.ee;
550  if (!scr.ea) {cpsr.a = 1;}
551  if (!scr.fiq) {cpsr.f = 1;}
552  if (!scr.irq) {cpsr.i = 1;}
553  } else if (cpsr.mode == MODE_MON) {
554  // Special case handling when entering monitor mode
555  cpsr.t = sctlr.te;
556  cpsr.e = sctlr.ee;
557  cpsr.a = 1;
558  cpsr.f = 1;
559  cpsr.i = 1;
560  } else {
561  cpsr.t = sctlr.te;
562  cpsr.e = sctlr.ee;
563 
564  // The *Disable functions are virtual and different per fault
565  cpsr.a = cpsr.a | abortDisable(tc);
566  cpsr.f = cpsr.f | fiqDisable(tc);
567  cpsr.i = 1;
568  }
569  cpsr.it1 = cpsr.it2 = 0;
570  cpsr.j = 0;
571  cpsr.pan = span ? 1 : saved_cpsr.pan;
572  tc->setMiscReg(MISCREG_CPSR, cpsr);
573 
574  // Make sure mailbox sets to one always
576 
577  // Clear the exclusive monitor
579 
580  if (cpsr.mode == MODE_HYP) {
581  tc->setMiscReg(MISCREG_ELR_HYP, curPc +
582  (saved_cpsr.t ? thumbPcOffset(true) : armPcOffset(true)));
583  } else {
584  tc->setIntReg(INTREG_LR, curPc +
585  (saved_cpsr.t ? thumbPcOffset(false) : armPcOffset(false)));
586  }
587 
588  switch (cpsr.mode) {
589  case MODE_FIQ:
590  tc->setMiscReg(MISCREG_SPSR_FIQ, saved_cpsr);
591  break;
592  case MODE_IRQ:
593  tc->setMiscReg(MISCREG_SPSR_IRQ, saved_cpsr);
594  break;
595  case MODE_SVC:
596  tc->setMiscReg(MISCREG_SPSR_SVC, saved_cpsr);
597  break;
598  case MODE_MON:
599  assert(have_security);
600  tc->setMiscReg(MISCREG_SPSR_MON, saved_cpsr);
601  break;
602  case MODE_ABORT:
603  tc->setMiscReg(MISCREG_SPSR_ABT, saved_cpsr);
604  break;
605  case MODE_UNDEFINED:
606  tc->setMiscReg(MISCREG_SPSR_UND, saved_cpsr);
607  if (ec(tc) != EC_UNKNOWN)
609  break;
610  case MODE_HYP:
611  assert(ArmSystem::haveVirtualization(tc));
612  tc->setMiscReg(MISCREG_SPSR_HYP, saved_cpsr);
614  break;
615  default:
616  panic("unknown Mode\n");
617  }
618 
619  Addr newPc = getVector(tc);
620  DPRINTF(Faults, "Invoking Fault:%s cpsr:%#x PC:%#x lr:%#x newVec: %#x "
621  "%s\n", name(), cpsr, curPc, tc->readIntReg(INTREG_LR),
622  newPc, arm_inst ? csprintf("inst: %#x", arm_inst->encoding()) :
623  std::string());
624  PCState pc(newPc);
625  pc.thumb(cpsr.t);
626  pc.nextThumb(pc.thumb());
627  pc.jazelle(cpsr.j);
628  pc.nextJazelle(pc.jazelle());
629  pc.aarch64(!cpsr.width);
630  pc.nextAArch64(!cpsr.width);
631  pc.illegalExec(false);
632  tc->pcState(pc);
633 }
634 
635 void
637 {
638  // Determine actual misc. register indices for ELR_ELx and SPSR_ELx
639  MiscRegIndex elr_idx, spsr_idx;
640  switch (toEL) {
641  case EL1:
642  elr_idx = MISCREG_ELR_EL1;
643  spsr_idx = MISCREG_SPSR_EL1;
644  break;
645  case EL2:
646  assert(ArmSystem::haveVirtualization(tc));
647  elr_idx = MISCREG_ELR_EL2;
648  spsr_idx = MISCREG_SPSR_EL2;
649  break;
650  case EL3:
651  assert(ArmSystem::haveSecurity(tc));
652  elr_idx = MISCREG_ELR_EL3;
653  spsr_idx = MISCREG_SPSR_EL3;
654  break;
655  default:
656  panic("Invalid target exception level");
657  break;
658  }
659 
660  // Save process state into SPSR_ELx
661  CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
662  CPSR spsr = cpsr;
663  spsr.nz = tc->readCCReg(CCREG_NZ);
664  spsr.c = tc->readCCReg(CCREG_C);
665  spsr.v = tc->readCCReg(CCREG_V);
666  spsr.ss = isResetSPSR() ? 0: cpsr.ss;
667  if (from64) {
668  // Force some bitfields to 0
669  spsr.q = 0;
670  spsr.it1 = 0;
671  spsr.j = 0;
672  spsr.ge = 0;
673  spsr.it2 = 0;
674  spsr.t = 0;
675  } else {
676  spsr.ge = tc->readCCReg(CCREG_GE);
677  ITSTATE it = tc->pcState().itstate();
678  spsr.it2 = it.top6;
679  spsr.it1 = it.bottom2;
680  }
681  tc->setMiscReg(spsr_idx, spsr);
682 
683  // Save preferred return address into ELR_ELx
684  Addr curr_pc = tc->pcState().pc();
685  Addr ret_addr = curr_pc;
686  if (from64)
687  ret_addr += armPcElrOffset();
688  else
689  ret_addr += spsr.t ? thumbPcElrOffset() : armPcElrOffset();
690  tc->setMiscReg(elr_idx, ret_addr);
691 
692  Addr vec_address = getVector64(tc);
693 
694  // Update process state
695  OperatingMode64 mode = 0;
696  mode.spX = 1;
697  mode.el = toEL;
698  mode.width = 0;
699  cpsr.mode = mode;
700  cpsr.daif = 0xf;
701  cpsr.il = 0;
702  cpsr.ss = 0;
703  cpsr.pan = span ? 1 : spsr.pan;
704  tc->setMiscReg(MISCREG_CPSR, cpsr);
705 
706  // If we have a valid instruction then use it to annotate this fault with
707  // extra information. This is used to generate the correct fault syndrome
708  // information
709  GEM5_VAR_USED ArmStaticInst *arm_inst = instrAnnotate(inst);
710 
711  // Set PC to start of exception handler
712  Addr new_pc = purifyTaggedAddr(vec_address, tc, toEL, true);
713  DPRINTF(Faults, "Invoking Fault (AArch64 target EL):%s cpsr:%#x PC:%#x "
714  "elr:%#x newVec: %#x %s\n", name(), cpsr, curr_pc, ret_addr,
715  new_pc, arm_inst ? csprintf("inst: %#x", arm_inst->encoding()) :
716  std::string());
717  PCState pc(new_pc);
718  pc.aarch64(!cpsr.width);
719  pc.nextAArch64(!cpsr.width);
720  pc.illegalExec(false);
721  pc.stepped(false);
722  tc->pcState(pc);
723 
724  // Save exception syndrome
725  if ((nextMode() != MODE_IRQ) && (nextMode() != MODE_FIQ))
727 }
728 
729 bool
731 {
733  VectorCatch* vc = sd->getVectorCatch(tc);
734  if (!vc->isVCMatch()) {
735  Fault fault = sd->testVectorCatch(tc, 0x0, this);
736  if (fault != NoFault)
737  fault->invoke(tc, inst);
738  return true;
739  }
740  return false;
741 }
742 
745 {
746  if (inst) {
747  auto arm_inst = static_cast<ArmStaticInst *>(inst.get());
748  arm_inst->annotateFault(this);
749  return arm_inst;
750  } else {
751  return nullptr;
752  }
753 }
754 
755 Addr
757 {
758  Addr base;
759 
760  // Check for invalid modes
761  GEM5_VAR_USED CPSR cpsr = tc->readMiscRegNoEffect(MISCREG_CPSR);
762  assert(ArmSystem::haveSecurity(tc) || cpsr.mode != MODE_MON);
763  assert(ArmSystem::haveVirtualization(tc) || cpsr.mode != MODE_HYP);
764 
765  // RVBAR is aliased (implemented as) MVBAR in gem5, since the two
766  // are mutually exclusive; there is no need to check here for
767  // which register to use since they hold the same value
769 
770  return base + offset(tc);
771 }
772 
773 void
775 {
776  if (FullSystem) {
777  tc->getCpuPtr()->clearInterrupts(tc->threadId());
778  tc->clearArchRegs();
779  }
780  if (!ArmSystem::highestELIs64(tc)) {
781  ArmFault::invoke(tc, inst);
783  getMPIDR(dynamic_cast<ArmSystem*>(tc->getSystemPtr()), tc));
784 
785  // Unless we have SMC code to get us there, boot in HYP!
788  CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
789  cpsr.mode = MODE_HYP;
790  tc->setMiscReg(MISCREG_CPSR, cpsr);
791  }
792  } else {
793  // Advance the PC to the IMPLEMENTATION DEFINED reset value
795  pc.aarch64(true);
796  pc.nextAArch64(true);
797  tc->pcState(pc);
798  }
799 }
800 
801 void
803 {
804  if (FullSystem) {
805  ArmFault::invoke(tc, inst);
806  return;
807  }
808 
809  // If the mnemonic isn't defined this has to be an unknown instruction.
810  assert(unknown || mnemonic != NULL);
811  auto arm_inst = static_cast<ArmStaticInst *>(inst.get());
812  if (disabled) {
813  panic("Attempted to execute disabled instruction "
814  "'%s' (inst 0x%08x)", mnemonic, arm_inst->encoding());
815  } else if (unknown) {
816  panic("Attempted to execute unknown instruction (inst 0x%08x)",
817  arm_inst->encoding());
818  } else {
819  panic("Attempted to execute unimplemented instruction "
820  "'%s' (inst 0x%08x)", mnemonic, arm_inst->encoding());
821  }
822 }
823 
824 bool
826 {
827  HCR hcr = tc->readMiscRegNoEffect(MISCREG_HCR);
828  return fromEL == EL2 ||
829  (EL2Enabled(tc) && (fromEL == EL0) && hcr.tge);
830 }
831 
832 uint32_t
834 {
835 
836  // If UndefinedInstruction is routed to hypervisor, iss field is 0.
837  if (hypRouted) {
838  return 0;
839  }
840 
841  if (overrideEc == EC_INVALID)
842  return issRaw;
843 
844  uint32_t new_iss = 0;
845  uint32_t op0, op1, op2, CRn, CRm, Rt, dir;
846 
847  dir = bits(machInst, 21, 21);
848  op0 = bits(machInst, 20, 19);
849  op1 = bits(machInst, 18, 16);
850  CRn = bits(machInst, 15, 12);
851  CRm = bits(machInst, 11, 8);
852  op2 = bits(machInst, 7, 5);
853  Rt = bits(machInst, 4, 0);
854 
855  new_iss = op0 << 20 | op2 << 17 | op1 << 14 | CRn << 10 |
856  Rt << 5 | CRm << 1 | dir;
857 
858  return new_iss;
859 }
860 
861 void
863 {
864  if (FullSystem) {
865  ArmFault::invoke(tc, inst);
866  return;
867  }
868 
869  // As of now, there isn't a 32 bit thumb version of this instruction.
870  assert(!machInst.bigThumb);
871  tc->getSystemPtr()->workload->syscall(tc);
872 
873  // Advance the PC since that won't happen automatically.
874  PCState pc = tc->pcState();
875  assert(inst);
876  inst->advancePC(pc);
877  tc->pcState(pc);
878 }
879 
880 bool
882 {
883  HCR hcr = tc->readMiscRegNoEffect(MISCREG_HCR);
884  return fromEL == EL2 ||
885  (EL2Enabled(tc) && fromEL == EL0 && hcr.tge);
886 }
887 
890 {
891  return (overrideEc != EC_INVALID) ? overrideEc :
892  (from64 ? EC_SVC_64 : vals.ec);
893 }
894 
895 uint32_t
897 {
898  // Even if we have a 24 bit imm from an arm32 instruction then we only use
899  // the bottom 16 bits for the ISS value (it doesn't hurt for AArch64 SVC).
900  return issRaw & 0xFFFF;
901 }
902 
903 uint32_t
905 {
906  if (from64)
907  return bits(machInst, 20, 5);
908  return 0;
909 }
910 
913 {
914  // If UndefinedInstruction is routed to hypervisor,
915  // HSR.EC field is 0.
916  if (hypRouted)
917  return EC_UNKNOWN;
918  else
919  return (overrideEc != EC_INVALID) ? overrideEc : vals.ec;
920 }
921 
922 
923 HypervisorCall::HypervisorCall(ExtMachInst _machInst, uint32_t _imm) :
924  ArmFaultVals<HypervisorCall>(_machInst, _imm)
925 {
926  bStep = true;
927 }
928 
929 bool
931 {
932  return from64 && fromEL == EL3;
933 }
934 
935 bool
937 {
938  return !from64 || fromEL != EL3;
939 }
940 
943 {
944  return from64 ? EC_HVC_64 : vals.ec;
945 }
946 
949 {
950  return (overrideEc != EC_INVALID) ? overrideEc : vals.ec;
951 }
952 
953 template<class T>
956 {
957  bool isHypTrap = false;
958 
959  // Normally we just use the exception vector from the table at the top if
960  // this file, however if this exception has caused a transition to hype
961  // mode, and its an exception type that would only do this if it has been
962  // trapped then we use the hyp trap vector instead of the normal vector
963  if (vals.hypTrappable) {
964  CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
965  if (cpsr.mode == MODE_HYP) {
966  CPSR spsr = tc->readMiscReg(MISCREG_SPSR_HYP);
967  isHypTrap = spsr.mode != MODE_HYP;
968  }
969  }
970  return isHypTrap ? 0x14 : vals.offset;
971 }
972 
973 template<class T>
976 {
977  if (toEL == fromEL) {
978  if (opModeIsT(fromMode))
979  return vals.currELTOffset;
980  return vals.currELHOffset;
981  } else {
982  bool lower_32 = false;
983  if (toEL == EL3) {
984  if (EL2Enabled(tc))
985  lower_32 = ELIs32(tc, EL2);
986  else
987  lower_32 = ELIs32(tc, EL1);
988  } else if (ELIsInHost(tc, fromEL) && fromEL == EL0 && toEL == EL2) {
989  lower_32 = ELIs32(tc, EL0);
990  } else {
991  lower_32 = ELIs32(tc, static_cast<ExceptionLevel>(toEL - 1));
992  }
993 
994  if (lower_32)
995  return vals.lowerEL32Offset;
996  return vals.lowerEL64Offset;
997  }
998 }
999 
1000 // void
1001 // SupervisorCall::setSyndrome64(ThreadContext *tc, MiscRegIndex esr_idx)
1002 // {
1003 // ESR esr = 0;
1004 // esr.ec = machInst.aarch64 ? SvcAArch64 : SvcAArch32;
1005 // esr.il = !machInst.thumb;
1006 // if (machInst.aarch64)
1007 // esr.imm16 = bits(machInst.instBits, 20, 5);
1008 // else if (machInst.thumb)
1009 // esr.imm16 = bits(machInst.instBits, 7, 0);
1010 // else
1011 // esr.imm16 = bits(machInst.instBits, 15, 0);
1012 // tc->setMiscReg(esr_idx, esr);
1013 // }
1014 
1015 void
1017 {
1018  if (FullSystem) {
1019  ArmFault::invoke(tc, inst);
1020  return;
1021  }
1022 }
1023 
1026 {
1027  return (from64 ? EC_SMC_64 : vals.ec);
1028 }
1029 
1030 bool
1032 {
1033  HCR hcr = tc->readMiscRegNoEffect(MISCREG_HCR_EL2);
1034  return EL2Enabled(tc) && currEL(tc) <= EL1 && hcr.tge;
1035 }
1036 
1037 uint32_t
1039 {
1040  // If SupervisorTrap is routed to hypervisor, iss field is 0.
1041  if (hypRouted) {
1042  return 0;
1043  }
1044  return issRaw;
1045 }
1046 
1049 {
1050  if (hypRouted)
1051  return EC_UNKNOWN;
1052  else
1053  return (overrideEc != EC_INVALID) ? overrideEc : vals.ec;
1054 }
1055 
1058 {
1059  return (overrideEc != EC_INVALID) ? overrideEc :
1060  (from64 ? EC_SMC_64 : vals.ec);
1061 }
1062 
1063 template<class T>
1064 void
1066 {
1067  if (tranMethod == ArmFault::UnknownTran) {
1068  tranMethod = longDescFormatInUse(tc) ? ArmFault::LpaeTran
1070 
1071  if ((tranMethod == ArmFault::VmsaTran) && this->routeToMonitor(tc)) {
1072  // See ARM ARM B3-1416
1073  bool override_LPAE = false;
1074  TTBCR ttbcr_s = tc->readMiscReg(MISCREG_TTBCR_S);
1075  GEM5_VAR_USED TTBCR ttbcr_ns = tc->readMiscReg(MISCREG_TTBCR_NS);
1076  if (ttbcr_s.eae) {
1077  override_LPAE = true;
1078  } else {
1079  // Unimplemented code option, not seen in testing. May need
1080  // extension according to the manual exceprt above.
1081  DPRINTF(Faults, "Warning: Incomplete translation method "
1082  "override detected.\n");
1083  }
1084  if (override_LPAE)
1085  tranMethod = ArmFault::LpaeTran;
1086  }
1087  }
1088 
1089  if (source == ArmFault::AsynchronousExternalAbort) {
1090  tc->getCpuPtr()->clearInterrupt(tc->threadId(), INT_ABT, 0);
1091  }
1092  // Get effective fault source encoding
1093  CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
1094 
1095  // source must be determined BEFORE invoking generic routines which will
1096  // try to set hsr etc. and are based upon source!
1097  ArmFaultVals<T>::invoke(tc, inst);
1098 
1099  if (!this->to64) { // AArch32
1100  FSR fsr = getFsr(tc);
1101  if (cpsr.mode == MODE_HYP) {
1102  tc->setMiscReg(T::HFarIndex, faultAddr);
1103  } else if (stage2) {
1104  tc->setMiscReg(MISCREG_HPFAR, (faultAddr >> 8) & ~0xf);
1105  tc->setMiscReg(T::HFarIndex, OVAddr);
1106  } else if (debugType > ArmFault::NODEBUG) {
1107  DBGDS32 Rext = tc->readMiscReg(MISCREG_DBGDSCRext);
1108  tc->setMiscReg(T::FarIndex, faultAddr);
1109  if (debugType == ArmFault::BRKPOINT){
1110  Rext.moe = 0x1;
1111  } else if (debugType == ArmFault::VECTORCATCH){
1112  Rext.moe = 0x5;
1113  } else if (debugType > ArmFault::VECTORCATCH) {
1114  Rext.moe = 0xa;
1115  fsr.cm = (debugType == ArmFault::WPOINT_CM)? 1 : 0;
1116  }
1117 
1118  tc->setMiscReg(T::FsrIndex, fsr);
1119  tc->setMiscReg(MISCREG_DBGDSCRext, Rext);
1120 
1121  } else {
1122  tc->setMiscReg(T::FsrIndex, fsr);
1123  tc->setMiscReg(T::FarIndex, faultAddr);
1124  }
1125  DPRINTF(Faults, "Abort Fault source=%#x fsr=%#x faultAddr=%#x "\
1126  "tranMethod=%#x\n", source, fsr, faultAddr, tranMethod);
1127  } else { // AArch64
1128  // Set the FAR register. Nothing else to do if we are in AArch64 state
1129  // because the syndrome register has already been set inside invoke64()
1130  if (stage2) {
1131  // stage 2 fault, set HPFAR_EL2 to the faulting IPA
1132  // and FAR_EL2 to the Original VA
1134  tc->setMiscReg(MISCREG_HPFAR_EL2, bits(faultAddr, 47, 12) << 4);
1135 
1136  DPRINTF(Faults, "Abort Fault (Stage 2) VA: 0x%x IPA: 0x%x\n",
1137  OVAddr, faultAddr);
1138  } else {
1139  tc->setMiscReg(AbortFault<T>::getFaultAddrReg64(), faultAddr);
1140  }
1141  }
1142 }
1143 
1144 template<class T>
1145 void
1147 {
1148  srcEncoded = getFaultStatusCode(tc);
1149  if (srcEncoded == ArmFault::FaultSourceInvalid) {
1150  panic("Invalid fault source\n");
1151  }
1152  ArmFault::setSyndrome(tc, syndrome_reg);
1153 }
1154 
1155 template<class T>
1156 uint8_t
1158 {
1159 
1160  panic_if(!this->faultUpdated,
1161  "Trying to use un-updated ArmFault internal variables\n");
1162 
1163  uint8_t fsc = 0;
1164 
1165  if (!this->to64) {
1166  // AArch32
1167  assert(tranMethod != ArmFault::UnknownTran);
1168  if (tranMethod == ArmFault::LpaeTran) {
1169  fsc = ArmFault::longDescFaultSources[source];
1170  } else {
1171  fsc = ArmFault::shortDescFaultSources[source];
1172  }
1173  } else {
1174  // AArch64
1175  fsc = ArmFault::aarch64FaultSources[source];
1176  }
1177 
1178  return fsc;
1179 }
1180 
1181 template<class T>
1182 FSR
1184 {
1185  FSR fsr = 0;
1186 
1187  auto fsc = getFaultStatusCode(tc);
1188 
1189  // AArch32
1190  assert(tranMethod != ArmFault::UnknownTran);
1191  if (tranMethod == ArmFault::LpaeTran) {
1192  fsr.status = fsc;
1193  fsr.lpae = 1;
1194  } else {
1195  fsr.fsLow = bits(fsc, 3, 0);
1196  fsr.fsHigh = bits(fsc, 4);
1197  fsr.domain = static_cast<uint8_t>(domain);
1198  }
1199 
1200  fsr.wnr = (write ? 1 : 0);
1201  fsr.ext = 0;
1202 
1203  return fsr;
1204 }
1205 
1206 template<class T>
1207 bool
1209 {
1210  if (ArmSystem::haveSecurity(tc)) {
1211  SCR scr = tc->readMiscRegNoEffect(MISCREG_SCR);
1212  return (!scr.ns || scr.aw);
1213  }
1214  return true;
1215 }
1216 
1217 template<class T>
1218 void
1220 {
1221  switch (id)
1222  {
1223  case ArmFault::S1PTW:
1224  s1ptw = val;
1225  break;
1226  case ArmFault::OVA:
1227  OVAddr = val;
1228  break;
1229 
1230  // Just ignore unknown ID's
1231  default:
1232  break;
1233  }
1234 }
1235 
1236 template<class T>
1237 uint32_t
1239 {
1240  uint32_t val;
1241 
1242  val = srcEncoded & 0x3F;
1243  val |= write << 6;
1244  val |= s1ptw << 7;
1245  return (val);
1246 }
1247 
1248 template<class T>
1249 bool
1251 {
1252  // NOTE: Not relying on LL information being aligned to lowest bits here
1253  return
1254  (source == ArmFault::AlignmentFault) ||
1255  ((source >= ArmFault::TranslationLL) &&
1256  (source < ArmFault::TranslationLL + 4)) ||
1257  ((source >= ArmFault::AccessFlagLL) &&
1258  (source < ArmFault::AccessFlagLL + 4)) ||
1259  ((source >= ArmFault::DomainLL) &&
1260  (source < ArmFault::DomainLL + 4)) ||
1261  ((source >= ArmFault::PermissionLL) &&
1262  (source < ArmFault::PermissionLL + 4));
1263 }
1264 
1265 template<class T>
1266 bool
1268 {
1269  va = (stage2 ? OVAddr : faultAddr);
1270  return true;
1271 }
1272 
1275 {
1276  if (to64) {
1277  // AArch64
1278  if (toEL == fromEL)
1280  else
1282  } else {
1283  // AArch32
1284  // Abort faults have different EC codes depending on whether
1285  // the fault originated within HYP mode, or not. So override
1286  // the method and add the extra adjustment of the EC value.
1287 
1289 
1290  CPSR spsr = tc->readMiscReg(MISCREG_SPSR_HYP);
1291  if (spsr.mode == MODE_HYP) {
1292  ec = ((ExceptionClass) (((uint32_t) ec) + 1));
1293  }
1294  return ec;
1295  }
1296 }
1297 
1298 bool
1300 {
1301  SCR scr = 0;
1302  if (from64)
1304  else
1305  scr = tc->readMiscRegNoEffect(MISCREG_SCR);
1306 
1307  return scr.ea && !isMMUFault();
1308 }
1309 
1310 bool
1312 {
1313  bool toHyp;
1314 
1315  HCR hcr = tc->readMiscRegNoEffect(MISCREG_HCR);
1316  HDCR hdcr = tc->readMiscRegNoEffect(MISCREG_HDCR);
1317 
1318  toHyp = fromEL == EL2;
1319  toHyp |= ArmSystem::haveEL(tc, EL2) && !isSecure(tc) &&
1320  currEL(tc) <= EL1 && (hcr.tge || stage2 ||
1321  (source == DebugEvent && hdcr.tde));
1322  return toHyp;
1323 }
1324 
1327 {
1328  if (to64) {
1329  // AArch64
1331  panic("Asynchronous External Abort should be handled with "
1332  "SystemErrors (SErrors)!");
1333  }
1334  if (toEL == fromEL)
1335  return EC_DATA_ABORT_CURR_EL;
1336  else
1337  return EC_DATA_ABORT_LOWER_EL;
1338  } else {
1339  // AArch32
1340  // Abort faults have different EC codes depending on whether
1341  // the fault originated within HYP mode, or not. So override
1342  // the method and add the extra adjustment of the EC value.
1343 
1345 
1346  CPSR spsr = tc->readMiscReg(MISCREG_SPSR_HYP);
1347  if (spsr.mode == MODE_HYP) {
1348  ec = ((ExceptionClass) (((uint32_t) ec) + 1));
1349  }
1350  return ec;
1351  }
1352 }
1353 
1354 bool
1356 {
1357  SCR scr = 0;
1358  if (from64)
1360  else
1361  scr = tc->readMiscRegNoEffect(MISCREG_SCR);
1362 
1363  return scr.ea && !isMMUFault();
1364 }
1365 
1366 bool
1368 {
1369  bool toHyp;
1370 
1371  HCR hcr = tc->readMiscRegNoEffect(MISCREG_HCR);
1372  HDCR hdcr = tc->readMiscRegNoEffect(MISCREG_HDCR);
1373 
1374  bool amo = hcr.amo;
1375  if (hcr.tge == 1)
1376  amo = (!HaveVirtHostExt(tc) || hcr.e2h == 0);
1377 
1378  // if in Hyp mode then stay in Hyp mode
1379  toHyp = fromEL == EL2 ||
1380  (EL2Enabled(tc) && fromEL <= EL1
1381  && (hcr.tge || stage2 ||
1382  ((source == AsynchronousExternalAbort) && amo) ||
1383  ((fromEL == EL0) && hcr.tge &&
1384  ((source == AlignmentFault) ||
1386  ((source == DebugEvent) && (hdcr.tde || hcr.tge))));
1387  return toHyp;
1388 }
1389 
1390 uint32_t
1392 {
1393  uint32_t val;
1394 
1395  // Add on the data abort specific fields to the generic abort ISS value
1397 
1398  val |= cm << 8;
1399 
1400  // ISS is valid if not caused by a stage 1 page table walk, and when taken
1401  // to AArch64 only when directed to EL2
1402  if (!s1ptw && stage2 && (!to64 || toEL == EL2)) {
1403  val |= isv << 24;
1404  if (isv) {
1405  val |= sas << 22;
1406  val |= sse << 21;
1407  val |= srt << 16;
1408  // AArch64 only. These assignments are safe on AArch32 as well
1409  // because these vars are initialized to false
1410  val |= sf << 15;
1411  val |= ar << 14;
1412  }
1413  }
1414  return (val);
1415 }
1416 
1417 void
1419 {
1421  switch (id)
1422  {
1423  case SAS:
1424  isv = true;
1425  sas = val;
1426  break;
1427  case SSE:
1428  isv = true;
1429  sse = val;
1430  break;
1431  case SRT:
1432  isv = true;
1433  srt = val;
1434  break;
1435  case SF:
1436  isv = true;
1437  sf = val;
1438  break;
1439  case AR:
1440  isv = true;
1441  ar = val;
1442  break;
1443  case CM:
1444  cm = val;
1445  break;
1446  case OFA:
1447  faultAddr = val;
1448  break;
1449  // Just ignore unknown ID's
1450  default:
1451  break;
1452  }
1453 }
1454 
1455 void
1457 {
1459  HCR hcr = tc->readMiscRegNoEffect(MISCREG_HCR);
1460  hcr.va = 0;
1461  tc->setMiscRegNoEffect(MISCREG_HCR, hcr);
1462 }
1463 
1464 bool
1466 {
1467  assert(ArmSystem::haveSecurity(tc));
1468  SCR scr = 0;
1469  if (from64)
1471  else
1472  scr = tc->readMiscRegNoEffect(MISCREG_SCR);
1473  return scr.irq;
1474 }
1475 
1476 bool
1478 {
1479  HCR hcr = tc->readMiscRegNoEffect(MISCREG_HCR);
1480  return fromEL == EL2 ||
1481  (EL2Enabled(tc) && fromEL <= EL1 && (hcr.tge || hcr.imo));
1482 }
1483 
1484 bool
1486 {
1487  if (ArmSystem::haveSecurity(tc)) {
1488  SCR scr = tc->readMiscRegNoEffect(MISCREG_SCR);
1489  return (!scr.ns || scr.aw);
1490  }
1491  return true;
1492 }
1493 
1495 {}
1496 
1497 bool
1499 {
1500  assert(ArmSystem::haveSecurity(tc));
1501  SCR scr = 0;
1502  if (from64)
1504  else
1505  scr = tc->readMiscRegNoEffect(MISCREG_SCR);
1506  return scr.fiq;
1507 }
1508 
1509 bool
1511 {
1512  HCR hcr = tc->readMiscRegNoEffect(MISCREG_HCR);
1513  return fromEL == EL2 ||
1514  (EL2Enabled(tc) && fromEL <= EL1 && (hcr.tge || hcr.fmo));
1515 }
1516 
1517 bool
1519 {
1520  if (ArmSystem::haveSecurity(tc)) {
1521  SCR scr = tc->readMiscRegNoEffect(MISCREG_SCR);
1522  return (!scr.ns || scr.aw);
1523  }
1524  return true;
1525 }
1526 
1527 bool
1529 {
1531  return true;
1532  } else if (ArmSystem::haveSecurity(tc)) {
1533  SCR scr = tc->readMiscRegNoEffect(MISCREG_SCR);
1534  return (!scr.ns || scr.fw);
1535  }
1536  return true;
1537 }
1538 
1540 {}
1541 
1542 void
1544 {
1546  assert(from64);
1547  // Set the FAR
1549 }
1550 
1551 bool
1553 {
1554  HCR hcr = tc->readMiscRegNoEffect(MISCREG_HCR_EL2);
1555  return fromEL == EL2 || (EL2Enabled(tc) && fromEL <= EL1 && hcr.tge);
1556 }
1557 
1559 {}
1560 
1561 bool
1563 {
1564  assert(from64);
1565  HCR hcr = tc->readMiscRegNoEffect(MISCREG_HCR_EL2);
1566  return EL2Enabled(tc) && currEL(tc) <= EL1 && hcr.tge == 1;
1567 }
1568 
1570 {}
1571 
1572 void
1574 {
1575  tc->getCpuPtr()->clearInterrupt(tc->threadId(), INT_ABT, 0);
1576  ArmFault::invoke(tc, inst);
1577 }
1578 
1579 bool
1581 {
1582  assert(ArmSystem::haveSecurity(tc));
1583  assert(from64);
1584  SCR scr = tc->readMiscRegNoEffect(MISCREG_SCR_EL3);
1585  return scr.ea || fromEL == EL3;
1586 }
1587 
1588 bool
1590 {
1591  assert(from64);
1592 
1593  HCR hcr = tc->readMiscRegNoEffect(MISCREG_HCR_EL2);
1594 
1595  return fromEL == EL2 ||
1596  (EL2Enabled(tc) && fromEL <= EL1 && (hcr.tge || hcr.amo));
1597 }
1598 
1599 
1601  : ArmFaultVals<SoftwareBreakpoint>(_mach_inst, _iss)
1602 {}
1603 
1604 bool
1606 {
1607  const HCR hcr = tc->readMiscRegNoEffect(MISCREG_HCR_EL2);
1608  const HDCR mdcr = tc->readMiscRegNoEffect(MISCREG_MDCR_EL2);
1609 
1610  return fromEL == EL2 ||
1611  (EL2Enabled(tc) && fromEL <= EL1 && (hcr.tge || mdcr.tde));
1612 }
1613 
1616 {
1618 }
1619 
1621  : ArmFaultVals<HardwareBreakpoint>(0x0, _iss), vAddr(_vaddr)
1622 {}
1623 
1624 bool
1626 {
1627  const HCR hcr = tc->readMiscRegNoEffect(MISCREG_HCR_EL2);
1628  const HDCR mdcr = tc->readMiscRegNoEffect(MISCREG_MDCR_EL2);
1629 
1630  return EL2Enabled(tc) && fromEL <= EL1 && (hcr.tge || mdcr.tde);
1631 }
1632 
1635 {
1636  // AArch64
1637  if (toEL == fromEL)
1638  return EC_HW_BREAKPOINT_CURR_EL;
1639  else
1641 }
1642 
1643 void
1645 {
1646 
1648  MiscRegIndex elr_idx;
1649  switch (toEL) {
1650  case EL1:
1651  elr_idx = MISCREG_ELR_EL1;
1652  break;
1653  case EL2:
1654  assert(ArmSystem::haveVirtualization(tc));
1655  elr_idx = MISCREG_ELR_EL2;
1656  break;
1657  case EL3:
1658  assert(ArmSystem::haveSecurity(tc));
1659  elr_idx = MISCREG_ELR_EL3;
1660  break;
1661  default:
1662  panic("Invalid target exception level");
1663  break;
1664  }
1665 
1666  tc->setMiscReg(elr_idx, vAddr);
1667 
1668 }
1669 
1671  bool _write, bool _cm)
1672  : ArmFaultVals<Watchpoint>(_mach_inst), vAddr(_vaddr),
1673  write(_write), cm(_cm)
1674 {}
1675 
1676 uint32_t
1678 {
1679  uint32_t iss = 0x0022;
1680 // NV
1681 // if (toEL == EL2)
1682 // iss |= 0x02000;
1683  if (cm)
1684  iss |= 0x00100;
1685  if (write)
1686  iss |= 0x00040;
1687  return iss;
1688 }
1689 
1690 void
1692 {
1694  // Set the FAR
1696 
1697 }
1698 
1699 bool
1701 {
1702  const HCR hcr = tc->readMiscRegNoEffect(MISCREG_HCR_EL2);
1703  const HDCR mdcr = tc->readMiscRegNoEffect(MISCREG_MDCR_EL2);
1704 
1705  return fromEL == EL2 ||
1706  (EL2Enabled(tc) && fromEL <= EL1 && (hcr.tge || mdcr.tde));
1707 }
1708 
1709 void
1711 {
1713  switch (id)
1714  {
1715  case OFA:
1716  vAddr = val;
1717  break;
1718  // Just ignore unknown ID's
1719  default:
1720  break;
1721  }
1722 }
1723 
1726 {
1727  // AArch64
1728  if (toEL == fromEL)
1729  return EC_WATCHPOINT_CURR_EL;
1730  else
1731  return EC_WATCHPOINT_LOWER_EL;
1732 }
1733 
1735  bool _stepped)
1736  : ArmFaultVals<SoftwareStepFault>(_mach_inst), isldx(is_ldx),
1737  stepped(_stepped)
1738 {
1739  bStep = true;
1740 }
1741 
1742 bool
1744 {
1745  const HCR hcr = tc->readMiscRegNoEffect(MISCREG_HCR_EL2);
1746  const HDCR mdcr = tc->readMiscRegNoEffect(MISCREG_MDCR_EL2);
1747 
1748  return fromEL == EL2 ||
1749  (EL2Enabled(tc) && fromEL <= EL1 && (hcr.tge || mdcr.tde));
1750 }
1751 
1754 {
1755  // AArch64
1756  if (toEL == fromEL)
1757  return EC_SOFTWARE_STEP_CURR_EL;
1758  else
1760 }
1761 
1762 uint32_t
1764 {
1765  uint32_t iss= 0x0022;
1766  if (stepped) {
1767  iss |= 0x1000000;
1768  }
1769 
1770  if (isldx) {
1771  iss |= 0x40;
1772  }
1773 
1774  return iss;
1775 
1776 }
1777 
1778 void
1780  DPRINTF(Faults, "Invoking ArmSev Fault\n");
1781  if (!FullSystem)
1782  return;
1783 
1784  // Set sev_mailbox to 1, clear the pending interrupt from remote
1785  // SEV execution and let pipeline continue as pcState is still
1786  // valid.
1788  tc->getCpuPtr()->clearInterrupt(tc->threadId(), INT_SEV, 0);
1789 }
1790 
1791 // Instantiate all the templates to make the linker happy
1792 template class ArmFaultVals<Reset>;
1793 template class ArmFaultVals<UndefinedInstruction>;
1794 template class ArmFaultVals<SupervisorCall>;
1795 template class ArmFaultVals<SecureMonitorCall>;
1796 template class ArmFaultVals<HypervisorCall>;
1797 template class ArmFaultVals<PrefetchAbort>;
1798 template class ArmFaultVals<DataAbort>;
1799 template class ArmFaultVals<VirtualDataAbort>;
1800 template class ArmFaultVals<HypervisorTrap>;
1801 template class ArmFaultVals<Interrupt>;
1802 template class ArmFaultVals<VirtualInterrupt>;
1803 template class ArmFaultVals<FastInterrupt>;
1804 template class ArmFaultVals<VirtualFastInterrupt>;
1805 template class ArmFaultVals<SupervisorTrap>;
1806 template class ArmFaultVals<SecureMonitorTrap>;
1807 template class ArmFaultVals<PCAlignmentFault>;
1808 template class ArmFaultVals<SPAlignmentFault>;
1809 template class ArmFaultVals<SystemError>;
1810 template class ArmFaultVals<SoftwareBreakpoint>;
1811 template class ArmFaultVals<HardwareBreakpoint>;
1812 template class ArmFaultVals<Watchpoint>;
1813 template class ArmFaultVals<SoftwareStepFault>;
1814 template class ArmFaultVals<ArmSev>;
1815 template class AbortFault<PrefetchAbort>;
1816 template class AbortFault<DataAbort>;
1817 template class AbortFault<VirtualDataAbort>;
1818 
1819 
1821 {}
1822 
1823 bool
1825 {
1826  const HCR hcr = tc->readMiscRegNoEffect(MISCREG_HCR_EL2);
1827  return EL2Enabled(tc) && fromEL == EL0 && hcr.tge;
1828 }
1829 
1830 bool
1832 {
1833  auto arm_fault = dynamic_cast<ArmFault *>(fault.get());
1834 
1835  if (arm_fault) {
1836  return arm_fault->getFaultVAddr(va);
1837  } else {
1838  auto pgt_fault = dynamic_cast<GenericPageTableFault *>(fault.get());
1839  if (pgt_fault) {
1840  va = pgt_fault->getFaultVAddr();
1841  return true;
1842  }
1843 
1844  auto align_fault = dynamic_cast<GenericAlignmentFault *>(fault.get());
1845  if (align_fault) {
1846  va = align_fault->getFaultVAddr();
1847  return true;
1848  }
1849 
1850  // Return false since it's not an address triggered exception
1851  return false;
1852  }
1853 }
1854 
1855 } // namespace ArmISA
1856 } // namespace gem5
gem5::ThreadContext::setIntReg
virtual void setIntReg(RegIndex reg_idx, RegVal val)=0
gem5::ArmISA::MISCREG_FAR_EL1
@ MISCREG_FAR_EL1
Definition: misc.hh:649
gem5::ArmISA::MISCREG_CPSR
@ MISCREG_CPSR
Definition: misc.hh:61
gem5::ArmISA::ArmFault::NODEBUG
@ NODEBUG
Definition: faults.hh:159
gem5::ArmISA::ArmFault::fromEL
ExceptionLevel fromEL
Definition: faults.hh:74
gem5::ArmISA::AbortFault::annotate
void annotate(ArmFault::AnnotationIDs id, uint64_t val) override
Definition: faults.cc:1219
gem5::ArmISA::CCREG_C
@ CCREG_C
Definition: cc.hh:50
gem5::ArmISA::AbortFault::setSyndrome
void setSyndrome(ThreadContext *tc, MiscRegIndex syndrome_reg) override
Definition: faults.cc:1146
gem5::ArmISA::ArmFault::FaultVals::ec
const ExceptionClass ec
Definition: faults.hh:194
gem5::ArmISA::ArmFault::NumFaultSources
@ NumFaultSources
Definition: faults.hh:119
gem5::ArmISA::SupervisorTrap::ec
ExceptionClass ec(ThreadContext *tc) const override
Definition: faults.cc:1048
gem5::ArmISA::EC_SOFTWARE_STEP
@ EC_SOFTWARE_STEP
Definition: types.hh:335
gem5::ArmISA::EC_PREFETCH_ABORT_TO_HYP
@ EC_PREFETCH_ABORT_TO_HYP
Definition: types.hh:319
gem5::ArmISA::MISCREG_VBAR_EL3
@ MISCREG_VBAR_EL3
Definition: misc.hh:742
gem5::ThreadContext::readMiscReg
virtual RegVal readMiscReg(RegIndex misc_reg)=0
gem5::ArmISA::UndefinedInstruction::mnemonic
const char * mnemonic
Definition: faults.hh:311
gem5::ArmISA::SPAlignmentFault::SPAlignmentFault
SPAlignmentFault()
Definition: faults.cc:1558
gem5::ArmISA::MODE_SVC
@ MODE_SVC
Definition: types.hh:284
gem5::ArmISA::EC_HVC
@ EC_HVC
Definition: types.hh:311
gem5::ArmISA::DataAbort::routeToMonitor
bool routeToMonitor(ThreadContext *tc) const override
Definition: faults.cc:1355
gem5::NoFault
constexpr decltype(nullptr) NoFault
Definition: types.hh:260
gem5::ArmISA::MISCREG_TTBCR_S
@ MISCREG_TTBCR_S
Definition: misc.hh:262
gem5::ThreadContext::getSystemPtr
virtual System * getSystemPtr()=0
gem5::ArmISA::MODE_MON
@ MODE_MON
Definition: types.hh:285
gem5::ArmISA::UndefinedInstruction::ec
ExceptionClass ec(ThreadContext *tc) const override
Definition: faults.cc:912
gem5::ArmISA::ELIs64
bool ELIs64(ThreadContext *tc, ExceptionLevel el)
Definition: utility.cc:282
gem5::ArmISA::SoftwareBreakpoint::routeToHyp
bool routeToHyp(ThreadContext *tc) const override
Definition: faults.cc:1605
gem5::ArmISA::EC_ILLEGAL_INST
@ EC_ILLEGAL_INST
Definition: types.hh:308
gem5::ArmISA::DataAbort::sf
bool sf
Definition: faults.hh:521
gem5::ArmISA::MODE_FIQ
@ MODE_FIQ
Definition: types.hh:282
gem5::ArmISA::EC_WATCHPOINT
@ EC_WATCHPOINT
Definition: types.hh:338
gem5::ArmISA::ArmFault::bStep
bool bStep
Definition: faults.hh:71
gem5::ArmISA::Watchpoint::Watchpoint
Watchpoint(ExtMachInst _mach_inst, Addr _vaddr, bool _write, bool _cm)
Definition: faults.cc:1670
gem5::ArmSystem::highestELIs64
bool highestELIs64() const
Returns true if the register width of the highest implemented exception level is 64 bits (ARMv8)
Definition: system.hh:205
gem5::ArmISA::SelfDebug
Definition: self_debug.hh:277
gem5::ArmISA::ArmFault::FaultSourceInvalid
@ FaultSourceInvalid
Definition: faults.hh:120
gem5::ArmISA::PCAlignmentFault::faultPC
Addr faultPC
The unaligned value of the PC.
Definition: faults.hh:593
gem5::ArmISA::ArmFault::abortDisable
virtual bool abortDisable(ThreadContext *tc)=0
gem5::ArmISA::cm
Bitfield< 13 > cm
Definition: misc_types.hh:428
gem5::ArmISA::EC_HW_BREAKPOINT_LOWER_EL
@ EC_HW_BREAKPOINT_LOWER_EL
Definition: types.hh:333
gem5::ArmISA::ArmStaticInst
Definition: static_inst.hh:63
gem5::ArmISA::ArmFault::BRKPOINT
@ BRKPOINT
Definition: faults.hh:160
gem5::ArmISA::HypervisorCall
Definition: faults.hh:408
gem5::ArmISA::EC_SERROR
@ EC_SERROR
Definition: types.hh:331
gem5::ArmISA::ArmFault::issRaw
uint32_t issRaw
Definition: faults.hh:68
gem5::ArmISA::EC_SVC_TO_HYP
@ EC_SVC_TO_HYP
Definition: types.hh:309
gem5::ArmISA::ArmFault::AR
@ AR
Definition: faults.hh:147
gem5::ArmISA::MISCREG_SPSR_FIQ
@ MISCREG_SPSR_FIQ
Definition: misc.hh:63
gem5::ArmISA::SystemError::SystemError
SystemError()
Definition: faults.cc:1569
gem5::ArmISA::HypervisorTrap::overrideEc
ExceptionClass overrideEc
Definition: faults.hh:423
gem5::ArmISA::MISCREG_MDCR_EL2
@ MISCREG_MDCR_EL2
Definition: misc.hh:587
gem5::ArmISA::EC_DATA_ABORT_LOWER_EL
@ EC_DATA_ABORT_LOWER_EL
Definition: types.hh:325
gem5::ArmISA::ArmFaultVals::vals
static FaultVals vals
Definition: faults.hh:264
gem5::ArmISA::SecureMonitorCall::ec
ExceptionClass ec(ThreadContext *tc) const override
Definition: faults.cc:1025
gem5::ArmISA::condCode
Bitfield< 31, 28 > condCode
Definition: types.hh:111
gem5::ArmISA::ArmFault::from64
bool from64
Definition: faults.hh:72
gem5::ArmISA::MODE_UNDEFINED
@ MODE_UNDEFINED
Definition: types.hh:288
gem5::ArmISA::HardwareBreakpoint::routeToHyp
bool routeToHyp(ThreadContext *tc) const override
Definition: faults.cc:1625
gem5::ArmISA::MODE_IRQ
@ MODE_IRQ
Definition: types.hh:283
gem5::ArmISA::ArmFault::VECTORCATCH
@ VECTORCATCH
Definition: faults.hh:161
gem5::ArmISA::MISCREG_SCR_EL3
@ MISCREG_SCR_EL3
Definition: misc.hh:593
gem5::ArmISA::domain
Bitfield< 7, 4 > domain
Definition: misc_types.hh:423
gem5::ArmISA::HypervisorTrap::ec
ExceptionClass ec(ThreadContext *tc) const override
Definition: faults.cc:948
gem5::ArmISA::UndefinedInstruction::overrideEc
ExceptionClass overrideEc
Definition: faults.hh:310
gem5::ArmISA::CCREG_NZ
@ CCREG_NZ
Definition: cc.hh:49
gem5::ArmISA::UndefinedInstruction::disabled
bool disabled
Definition: faults.hh:309
gem5::ArmISA::ArmFault::SynchronousExternalAbort
@ SynchronousExternalAbort
Definition: faults.hh:106
gem5::ArmISA::EC_HVC_64
@ EC_HVC_64
Definition: types.hh:315
gem5::ArmISA::ArmFault::LpaeTran
@ LpaeTran
Definition: faults.hh:152
gem5::ArmISA::ArmFault::faultUpdated
bool faultUpdated
Definition: faults.hh:82
gem5::ArmISA::ArmFault::SSE
@ SSE
Definition: faults.hh:137
gem5::ArmISA::MISCREG_VBAR_EL2
@ MISCREG_VBAR_EL2
Definition: misc.hh:740
gem5::ArmISA::UndefinedInstruction::unknown
bool unknown
Definition: faults.hh:308
gem5::ArmISA::MISCREG_HSCTLR
@ MISCREG_HSCTLR
Definition: misc.hh:246
gem5::ArmISA::currEL
static ExceptionLevel currEL(const ThreadContext *tc)
Definition: utility.hh:119
gem5::ArmISA::MISCREG_ESR_EL2
@ MISCREG_ESR_EL2
Definition: misc.hh:644
gem5::ArmISA::DataAbort::iss
uint32_t iss() const override
Definition: faults.cc:1391
gem5::ArmISA::PCAlignmentFault::routeToHyp
bool routeToHyp(ThreadContext *tc) const override
Definition: faults.cc:1552
gem5::ArmISA::HypervisorCall::routeToHyp
bool routeToHyp(ThreadContext *tc) const override
Definition: faults.cc:936
gem5::X86ISA::val
Bitfield< 63 > val
Definition: misc.hh:775
gem5::ArmISA::ArmFault::armPcElrOffset
virtual uint8_t armPcElrOffset()=0
gem5::ArmISA::Watchpoint::vAddr
Addr vAddr
Definition: faults.hh:646
gem5::ArmISA::AbortFault::getFaultStatusCode
uint8_t getFaultStatusCode(ThreadContext *tc) const
Definition: faults.cc:1157
gem5::ArmISA::PrefetchAbort::routeToMonitor
bool routeToMonitor(ThreadContext *tc) const override
Definition: faults.cc:1299
gem5::ArmISA::opModeIsT
static bool opModeIsT(OperatingMode mode)
Definition: types.hh:376
gem5::ArmISA::ArmFault::DomainLL
@ DomainLL
Definition: faults.hh:103
gem5::ArmISA::MISCREG_LOCKFLAG
@ MISCREG_LOCKFLAG
Definition: misc.hh:83
gem5::ArmISA::Interrupt::routeToMonitor
bool routeToMonitor(ThreadContext *tc) const override
Definition: faults.cc:1465
gem5::ArmISA::EL1
@ EL1
Definition: types.hh:267
gem5::ArmISA::EC_SOFTWARE_BREAKPOINT
@ EC_SOFTWARE_BREAKPOINT
Definition: types.hh:341
gem5::ArmISA::ArmFault::offset64
virtual FaultOffset offset64(ThreadContext *tc)=0
gem5::ArmISA::ArmFault::DebugEvent
@ DebugEvent
Definition: faults.hh:105
gem5::System::workload
Workload * workload
OS kernel.
Definition: system.hh:335
gem5::ArmISA::Watchpoint::routeToHyp
bool routeToHyp(ThreadContext *tc) const override
Definition: faults.cc:1700
gem5::ArmISA::opModeToEL
static ExceptionLevel opModeToEL(OperatingMode mode)
Definition: types.hh:383
gem5::ArmISA::MISCREG_SPSR_MON
@ MISCREG_SPSR_MON
Definition: misc.hh:66
gem5::ArmISA::ELIsInHost
bool ELIsInHost(ThreadContext *tc, ExceptionLevel el)
Returns true if the current exception level el is executing a Host OS or an application of a Host OS ...
Definition: utility.cc:297
gem5::ArmISA::Watchpoint
Definition: faults.hh:643
gem5::csprintf
std::string csprintf(const char *format, const Args &...args)
Definition: cprintf.hh:161
gem5::ArmISA::SupervisorTrap::iss
uint32_t iss() const override
Definition: faults.cc:1038
gem5::RefCountingPtr::get
T * get() const
Directly access the pointer itself without taking a reference.
Definition: refcnt.hh:227
gem5::X86ISA::base
Bitfield< 51, 12 > base
Definition: pagetable.hh:141
gem5::ArmISA::HardwareBreakpoint::vAddr
Addr vAddr
Definition: faults.hh:634
gem5::ArmISA::VirtualDataAbort::invoke
void invoke(ThreadContext *tc, const StaticInstPtr &inst) override
Definition: faults.cc:1456
gem5::ArmISA::SoftwareStepFault::isldx
bool isldx
Definition: faults.hh:663
system.hh
gem5::ArmISA::ArmFault::setSyndrome
virtual void setSyndrome(ThreadContext *tc, MiscRegIndex syndrome_reg)
Definition: faults.cc:398
gem5::ArmISA::ArmFault::to64
bool to64
Definition: faults.hh:73
gem5::ArmISA::MISCREG_SCTLR
@ MISCREG_SCTLR
Definition: misc.hh:235
gem5::ArmISA::getFaultVAddr
bool getFaultVAddr(Fault fault, Addr &va)
Returns true if the fault passed as a first argument was triggered by a memory access,...
Definition: faults.cc:1831
gem5::PowerISA::PCState
Definition: pcstate.hh:42
gem5::ArmISA::SoftwareBreakpoint::ec
ExceptionClass ec(ThreadContext *tc) const override
Definition: faults.cc:1615
gem5::ArmISA::SystemError::routeToHyp
bool routeToHyp(ThreadContext *tc) const override
Definition: faults.cc:1589
gem5::ArmISA::ArmFault::getVector64
Addr getVector64(ThreadContext *tc)
Definition: faults.cc:343
gem5::ArmISA::SystemError::routeToMonitor
bool routeToMonitor(ThreadContext *tc) const override
Definition: faults.cc:1580
gem5::ArmISA::ArmFault::PermissionLL
@ PermissionLL
Definition: faults.hh:104
gem5::FaultBase::name
virtual FaultName name() const =0
gem5::ThreadContext::readCCReg
virtual RegVal readCCReg(RegIndex reg_idx) const =0
gem5::ArmISA::EC_WATCHPOINT_LOWER_EL
@ EC_WATCHPOINT_LOWER_EL
Definition: types.hh:339
gem5::ArmISA::ArmFault::AsynchronousExternalAbort
@ AsynchronousExternalAbort
Definition: faults.hh:109
gem5::ArmISA::PCAlignmentFault::invoke
void invoke(ThreadContext *tc, const StaticInstPtr &inst=nullStaticInstPtr) override
Definition: faults.cc:1543
gem5::RefCountingPtr< StaticInst >
gem5::ArmISA::ArmFault::VmsaTran
@ VmsaTran
Definition: faults.hh:153
gem5::ArmISA::AbortFault::getFsr
FSR getFsr(ThreadContext *tc) const override
Definition: faults.cc:1183
gem5::ArmISA::MISCREG_DBGDSCRext
@ MISCREG_DBGDSCRext
Definition: misc.hh:103
gem5::ArmISA::EC_SMC_64
@ EC_SMC_64
Definition: types.hh:316
gem5::ArmISA::purifyTaggedAddr
Addr purifyTaggedAddr(Addr addr, ThreadContext *tc, ExceptionLevel el, TCR tcr, bool isInstr)
Removes the tag from tagged addresses if that mode is enabled.
Definition: utility.cc:463
gem5::ArmISA::SupervisorCall::iss
uint32_t iss() const override
Definition: faults.cc:896
gem5::ArmISA::ArmFault::OFA
@ OFA
Definition: faults.hh:140
gem5::ArmISA::ArmFault::iss
virtual uint32_t iss() const =0
gem5::GenericPageTableFault
Definition: faults.hh:116
gem5::ArmISA::FastInterrupt::abortDisable
bool abortDisable(ThreadContext *tc) override
Definition: faults.cc:1518
gem5::ArmISA::INT_ABT
@ INT_ABT
Definition: interrupts.hh:61
gem5::ArmISA::Watchpoint::invoke
void invoke(ThreadContext *tc, const StaticInstPtr &inst=nullStaticInstPtr) override
Definition: faults.cc:1691
gem5::ArmISA::amo
Bitfield< 5 > amo
Definition: misc_types.hh:279
gem5::ArmISA::ArmFault::countStat
virtual FaultStat & countStat()=0
gem5::ArmISA::ArmFault::instrAnnotate
ArmStaticInst * instrAnnotate(const StaticInstPtr &inst)
Definition: faults.cc:744
gem5::ArmISA::MISCREG_ELR_EL1
@ MISCREG_ELR_EL1
Definition: misc.hh:614
gem5::ArmISA::ArmFault::thumbPcElrOffset
virtual uint8_t thumbPcElrOffset()=0
gem5::ArmISA::ArmFaultVals
Definition: faults.hh:261
interrupts.hh
gem5::ThreadContext
ThreadContext is the external interface to all thread state for anything outside of the CPU.
Definition: thread_context.hh:93
gem5::ArmISA::EC_UNKNOWN
@ EC_UNKNOWN
Definition: types.hh:296
gem5::ArmISA::MODE_HYP
@ MODE_HYP
Definition: types.hh:287
gem5::ArmISA::ArmFault::offset
virtual FaultOffset offset(ThreadContext *tc)=0
gem5::ArmISA::MISCREG_SCTLR_EL1
@ MISCREG_SCTLR_EL1
Definition: misc.hh:579
gem5::ArmISA::SoftwareStepFault
Definition: faults.hh:660
gem5::ArmISA::HardwareBreakpoint
Definition: faults.hh:631
gem5::ArmISA::ArmFault::thumbPcOffset
virtual uint8_t thumbPcOffset(bool isHyp)=0
gem5::Fault
std::shared_ptr< FaultBase > Fault
Definition: types.hh:255
gem5::ArmISA::MISCREG_HDCR
@ MISCREG_HDCR
Definition: misc.hh:250
gem5::ArmISA::HaveVirtHostExt
bool HaveVirtHostExt(ThreadContext *tc)
Definition: utility.cc:224
gem5::ArmISA::EC_SOFTWARE_BREAKPOINT_64
@ EC_SOFTWARE_BREAKPOINT_64
Definition: types.hh:343
gem5::ArmISA::ArmFault::getSyndromeReg64
MiscRegIndex getSyndromeReg64() const
Definition: faults.cc:366
gem5::ArmISA::SecureMonitorCall::invoke
void invoke(ThreadContext *tc, const StaticInstPtr &inst=nullStaticInstPtr) override
Definition: faults.cc:1016
DPRINTF
#define DPRINTF(x,...)
Definition: trace.hh:186
gem5::ArmISA::ArmFault::toEL
ExceptionLevel toEL
Definition: faults.hh:75
gem5::ArmISA::MISCREG_MVBAR
@ MISCREG_MVBAR
Definition: misc.hh:394
gem5::ArmISA::DataAbort::ec
ExceptionClass ec(ThreadContext *tc) const override
Definition: faults.cc:1326
gem5::ArmISA::SecureMonitorTrap::ec
ExceptionClass ec(ThreadContext *tc) const override
Definition: faults.cc:1057
gem5::ArmISA::FastInterrupt::routeToHyp
bool routeToHyp(ThreadContext *tc) const override
Definition: faults.cc:1510
gem5::ArmISA::ArmFault::hypRouted
bool hypRouted
Definition: faults.hh:84
gem5::ArmISA::EL2
@ EL2
Definition: types.hh:268
gem5::ArmISA::MISCREG_SPSR_IRQ
@ MISCREG_SPSR_IRQ
Definition: misc.hh:64
gem5::ArmISA::SupervisorCall::invoke
void invoke(ThreadContext *tc, const StaticInstPtr &inst=nullStaticInstPtr) override
Definition: faults.cc:862
gem5::ArmISA::MISCREG_SCTLR_EL2
@ MISCREG_SCTLR_EL2
Definition: misc.hh:584
gem5::ArmISA::COND_UC
@ COND_UC
Definition: cc.hh:84
gem5::ArmISA::ArmFault::shortDescFaultSources
static uint8_t shortDescFaultSources[NumFaultSources]
Encodings of the fault sources when the short-desc.
Definition: faults.hh:125
gem5::ArmISA::DataAbort::sas
uint8_t sas
Definition: faults.hh:515
isa.hh
gem5::ArmISA::ELIs32
bool ELIs32(ThreadContext *tc, ExceptionLevel el)
Definition: utility.cc:288
gem5::ArmISA::ArmFault::update
void update(ThreadContext *tc)
Definition: faults.cc:439
gem5::ArmISA::ArmFaultVals::offset64
FaultOffset offset64(ThreadContext *tc) override
Definition: faults.cc:975
gem5::BaseCPU::clearInterrupt
void clearInterrupt(ThreadID tid, int int_num, int index)
Definition: base.hh:244
gem5::ArmISA::ArmFault::getFaultVAddr
virtual bool getFaultVAddr(Addr &va) const
Definition: faults.hh:256
gem5::ArmISA::MISCREG_VMPIDR
@ MISCREG_VMPIDR
Definition: misc.hh:234
gem5::ArmISA::Watchpoint::cm
bool cm
Definition: faults.hh:648
gem5::ArmISA::SecureMonitorCall::iss
uint32_t iss() const override
Definition: faults.cc:904
gem5::ArmISA::UndefinedInstruction::routeToHyp
bool routeToHyp(ThreadContext *tc) const override
Definition: faults.cc:825
gem5::ArmISA::AbortFault::iss
uint32_t iss() const override
Definition: faults.cc:1238
gem5::ArmISA::AbortFault::abortDisable
bool abortDisable(ThreadContext *tc) override
Definition: faults.cc:1208
gem5::ArmISA::UndefinedInstruction::invoke
void invoke(ThreadContext *tc, const StaticInstPtr &inst=nullStaticInstPtr) override
Definition: faults.cc:802
gem5::ArmISA::EL2Enabled
bool EL2Enabled(ThreadContext *tc)
Definition: utility.cc:274
gem5::ArmISA::SupervisorTrap::overrideEc
ExceptionClass overrideEc
Definition: faults.hh:378
gem5::PowerISA::AlignmentFault
Definition: faults.hh:82
gem5::ArmISA::MISCREG_SPSR_EL2
@ MISCREG_SPSR_EL2
Definition: misc.hh:625
gem5::ArmISA::DataAbort::srt
uint8_t srt
Definition: faults.hh:517
gem5::ArmISA::VirtualInterrupt::VirtualInterrupt
VirtualInterrupt()
Definition: faults.cc:1494
gem5::ArmISA::DataAbort::annotate
void annotate(AnnotationIDs id, uint64_t val) override
Definition: faults.cc:1418
gem5::ArmISA::ArmFault::SF
@ SF
Definition: faults.hh:146
gem5::bits
constexpr T bits(T val, unsigned first, unsigned last)
Extract the bitfield from position 'first' to 'last' (inclusive) from 'val' and right justify it.
Definition: bitfield.hh:76
compiler.hh
gem5::GenericAlignmentFault
Definition: faults.hh:128
gem5::ArmISA::EL3
@ EL3
Definition: types.hh:269
gem5::ArmISA::ArmFault::nextMode
virtual OperatingMode nextMode()=0
gem5::ThreadContext::pcState
virtual TheISA::PCState pcState() const =0
gem5::ArmISA::FastInterrupt::fiqDisable
bool fiqDisable(ThreadContext *tc) override
Definition: faults.cc:1528
gem5::ThreadContext::readMiscRegNoEffect
virtual RegVal readMiscRegNoEffect(RegIndex misc_reg) const =0
faults.hh
gem5::ArmISA::DataAbort::cm
uint8_t cm
Definition: faults.hh:518
gem5::ArmISA::MISCREG_ID_AA64MMFR1_EL1
@ MISCREG_ID_AA64MMFR1_EL1
Definition: misc.hh:570
gem5::ArmISA::MISCREG_SPSR_EL1
@ MISCREG_SPSR_EL1
Definition: misc.hh:612
gem5::ArmISA::COND_AL
@ COND_AL
Definition: cc.hh:83
gem5::PowerISA::INTREG_LR
@ INTREG_LR
Definition: int.hh:64
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::ThreadContext::readIntReg
virtual RegVal readIntReg(RegIndex reg_idx) const =0
gem5::ArmISA::SoftwareBreakpoint::SoftwareBreakpoint
SoftwareBreakpoint(ExtMachInst _mach_inst, uint32_t _iss)
Definition: faults.cc:1600
gem5::ArmISA::SoftwareBreakpoint
System error (AArch64 only)
Definition: faults.hh:622
gem5::ArmISA::ArmFaultVals< Reset >::offset
FaultOffset offset(ThreadContext *tc) override
Definition: faults.cc:955
gem5::ArmISA::SoftwareStepFault::iss
uint32_t iss() const override
Definition: faults.cc:1763
gem5::ArmISA::HypervisorCall::ec
ExceptionClass ec(ThreadContext *tc) const override
Definition: faults.cc:942
gem5::ArmISA::MiscRegIndex
MiscRegIndex
Definition: misc.hh:59
gem5::ArmISA::HardwareBreakpoint::ec
ExceptionClass ec(ThreadContext *tc) const override
Definition: faults.cc:1634
gem5::ArmISA::isSecure
bool isSecure(ThreadContext *tc)
Definition: utility.cc:72
gem5::ArmISA::CCREG_GE
@ CCREG_GE
Definition: cc.hh:52
gem5::ArmISA::va
Bitfield< 8 > va
Definition: misc_types.hh:275
gem5::FaultBase::invoke
virtual void invoke(ThreadContext *tc, const StaticInstPtr &inst=nullStaticInstPtr)
Definition: faults.cc:59
gem5::ArmISA::AbortFault::getFaultVAddr
bool getFaultVAddr(Addr &va) const override
Definition: faults.cc:1267
utility.hh
gem5::ArmISA::ExceptionClass
ExceptionClass
Definition: types.hh:293
gem5::ArmISA::SoftwareStepFault::routeToHyp
bool routeToHyp(ThreadContext *tc) const override
Definition: faults.cc:1743
full_system.hh
gem5::ArmISA::ArmFault::getFaultAddrReg64
MiscRegIndex getFaultAddrReg64() const
Definition: faults.cc:382
gem5::ArmISA::HardwareBreakpoint::HardwareBreakpoint
HardwareBreakpoint(Addr _vaddr, uint32_t _iss)
Definition: faults.cc:1620
gem5::ArmISA::Reset::getVector
Addr getVector(ThreadContext *tc) override
Definition: faults.cc:756
gem5::ArmISA::ArmFault
Definition: faults.hh:64
gem5::ArmISA::AbortFault< DataAbort >::faultAddr
Addr faultAddr
The virtual address the fault occured at.
Definition: faults.hh:445
gem5::ArmISA::FaultOffset
Addr FaultOffset
Definition: faults.hh:60
gem5::X86ISA::ExtMachInst
Definition: types.hh:206
gem5::FullSystem
bool FullSystem
The FullSystem variable can be used to determine the current mode of simulation.
Definition: root.cc:223
gem5::MipsISA::FaultVals
MipsFaultBase::FaultVals FaultVals
Definition: faults.cc:46
gem5::ArmISA::ArmFault::aarch64FaultSources
static uint8_t aarch64FaultSources[NumFaultSources]
Encodings of the fault sources in AArch64 state.
Definition: faults.hh:130
gem5::ArmISA::MISCREG_SPSR_EL3
@ MISCREG_SPSR_EL3
Definition: misc.hh:632
gem5::ArmISA::SupervisorCall::overrideEc
ExceptionClass overrideEc
Definition: faults.hh:340
gem5::ArmISA::EC_SOFTWARE_STEP_LOWER_EL
@ EC_SOFTWARE_STEP_LOWER_EL
Definition: types.hh:336
gem5::ArmISA::PrefetchAbort::routeToHyp
bool routeToHyp(ThreadContext *tc) const override
Definition: faults.cc:1311
gem5::ArmISA::EC_PREFETCH_ABORT_CURR_EL
@ EC_PREFETCH_ABORT_CURR_EL
Definition: types.hh:322
gem5::ArmISA::EL0
@ EL0
Definition: types.hh:266
panic_if
#define panic_if(cond,...)
Conditional panic macro that checks the supplied condition and only panics if the condition is true a...
Definition: logging.hh:203
gem5::ArmSystem
Definition: system.hh:62
gem5::ArmISA::SupervisorCall::routeToHyp
bool routeToHyp(ThreadContext *tc) const override
Definition: faults.cc:881
gem5::ArmISA::ArmFault::invoke64
void invoke64(ThreadContext *tc, const StaticInstPtr &inst=nullStaticInstPtr)
Definition: faults.cc:636
gem5::ArmISA::ArmFault::invoke
void invoke(ThreadContext *tc, const StaticInstPtr &inst=nullStaticInstPtr) override
Definition: faults.cc:489
gem5::ArmISA::MISCREG_HCR
@ MISCREG_HCR
Definition: misc.hh:248
gem5::ArmISA::SupervisorTrap::routeToHyp
bool routeToHyp(ThreadContext *tc) const override
Definition: faults.cc:1031
gem5::ArmISA::DataAbort::isv
bool isv
Definition: faults.hh:514
gem5::ArmISA::MISCREG_TTBCR_NS
@ MISCREG_TTBCR_NS
Definition: misc.hh:261
gem5::ArmISA::Watchpoint::annotate
void annotate(AnnotationIDs id, uint64_t val) override
Definition: faults.cc:1710
gem5::ArmISA::VectorCatch::isVCMatch
bool isVCMatch() const
Definition: self_debug.hh:257
gem5::ArmISA::VectorCatch
Definition: self_debug.hh:242
gem5::ArmISA::ArmFault::AlignmentFault
@ AlignmentFault
Definition: faults.hh:97
gem5::ArmISA::AbortFault::isMMUFault
bool isMMUFault() const
Definition: faults.cc:1250
gem5::ArmISA::ArmFault::getVector
virtual Addr getVector(ThreadContext *tc)
Definition: faults.cc:311
gem5::ArmISA::ArmFault::isResetSPSR
bool isResetSPSR()
Definition: faults.hh:232
gem5::ArmISA::MISCREG_SPSR_SVC
@ MISCREG_SPSR_SVC
Definition: misc.hh:65
gem5::ArmISA::ArmFault::CM
@ CM
Definition: faults.hh:139
base.hh
gem5::ArmISA::EC_PREFETCH_ABORT_LOWER_EL
@ EC_PREFETCH_ABORT_LOWER_EL
Definition: types.hh:320
gem5::ArmISA::Watchpoint::iss
uint32_t iss() const override
Definition: faults.cc:1677
gem5::ArmISA::AbortFault::invoke
void invoke(ThreadContext *tc, const StaticInstPtr &inst=nullStaticInstPtr) override
Definition: faults.cc:1065
gem5::ArmISA::HighVecs
const uint32_t HighVecs
Definition: faults.cc:63
gem5::ArmISA::ArmFault::span
bool span
Definition: faults.hh:85
gem5::ArmISA::EC_HW_BREAKPOINT_CURR_EL
@ EC_HW_BREAKPOINT_CURR_EL
Definition: types.hh:334
gem5::ArmISA::ArmFault::TranslationLL
@ TranslationLL
Definition: faults.hh:101
gem5::ArmISA::AbortFault< PrefetchAbort >::stage2
bool stage2
Definition: faults.hh:456
gem5::ArmISA::SoftwareStepFault::SoftwareStepFault
SoftwareStepFault(ExtMachInst _mach_inst, bool is_ldx, bool stepped)
Definition: faults.cc:1734
gem5::ArmISA::ArmFault::WPOINT_CM
@ WPOINT_CM
Definition: faults.hh:162
gem5::ArmISA::ConditionCode
ConditionCode
Definition: cc.hh:67
gem5::ArmISA::ArmFaultVals::ec
ExceptionClass ec(ThreadContext *tc) const override
Definition: faults.hh:291
gem5::ThreadContext::setMiscReg
virtual void setMiscReg(RegIndex misc_reg, RegVal val)=0
static_inst.hh
gem5::ArmISA::ISA::getSelfDebug
SelfDebug * getSelfDebug() const
Definition: isa.hh:524
gem5::ArmSystem::haveSecurity
bool haveSecurity() const
Returns true if this system implements the Security Extensions.
Definition: system.hh:162
gem5::ArmISA::ArmFault::ec
virtual ExceptionClass ec(ThreadContext *tc) const =0
gem5::MipsISA::pc
Bitfield< 4 > pc
Definition: pra_constants.hh:243
gem5::ArmISA::ArmFault::AnnotationIDs
AnnotationIDs
Definition: faults.hh:132
gem5::ArmISA::MISCREG_SCR
@ MISCREG_SCR
Definition: misc.hh:243
gem5::ArmISA::MISCREG_ESR_EL3
@ MISCREG_ESR_EL3
Definition: misc.hh:648
gem5::ArmISA::MISCREG_ELR_EL2
@ MISCREG_ELR_EL2
Definition: misc.hh:626
gem5::ArmISA::longDescFormatInUse
bool longDescFormatInUse(ThreadContext *tc)
Definition: utility.cc:127
gem5::ArmISA::EC_DATA_ABORT_TO_HYP
@ EC_DATA_ABORT_TO_HYP
Definition: types.hh:324
gem5::ArmISA::ArmFault::annotate
virtual void annotate(AnnotationIDs id, uint64_t val)
Definition: faults.hh:237
gem5::ArmISA::EC_PC_ALIGNMENT
@ EC_PC_ALIGNMENT
Definition: types.hh:323
gem5::ArmSystem::resetAddr
Addr resetAddr() const
Returns the reset address if the highest implemented exception level is 64 bits (ARMv8)
Definition: system.hh:220
gem5::ArmISA::ArmFault::AccessFlagLL
@ AccessFlagLL
Definition: faults.hh:102
gem5::ArmISA::SoftwareStepFault::ec
ExceptionClass ec(ThreadContext *tc) const override
Definition: faults.cc:1753
gem5::ArmISA::UndefinedInstruction::iss
uint32_t iss() const override
Definition: faults.cc:833
gem5::ArmISA::MISCREG_SPSR_ABT
@ MISCREG_SPSR_ABT
Definition: misc.hh:67
gem5::ArmISA::EC_INVALID
@ EC_INVALID
Definition: types.hh:295
gem5::ArmISA::MISCREG_ELR_HYP
@ MISCREG_ELR_HYP
Definition: misc.hh:70
gem5::ArmISA::FastInterrupt::routeToMonitor
bool routeToMonitor(ThreadContext *tc) const override
Definition: faults.cc:1498
gem5::ArmISA::ArmFault::S1PTW
@ S1PTW
Definition: faults.hh:134
gem5::ArmISA::Reset::invoke
void invoke(ThreadContext *tc, const StaticInstPtr &inst=nullStaticInstPtr) override
Definition: faults.cc:774
gem5::ArmISA::sd
Bitfield< 4 > sd
Definition: misc_types.hh:774
gem5::ArmISA::MISCREG_HVBAR
@ MISCREG_HVBAR
Definition: misc.hh:397
gem5::ArmISA::HypervisorCall::HypervisorCall
HypervisorCall(ExtMachInst _machInst, uint32_t _imm)
Definition: faults.cc:923
gem5::ThreadContext::getCpuPtr
virtual BaseCPU * getCpuPtr()=0
gem5::ArmISA::ArmSev::invoke
void invoke(ThreadContext *tc, const StaticInstPtr &inst=nullStaticInstPtr) override
Definition: faults.cc:1779
gem5::ArmISA::MISCREG_VBAR
@ MISCREG_VBAR
Definition: misc.hh:391
gem5::ArmISA::ArmFault::toMode
OperatingMode toMode
Definition: faults.hh:77
gem5::ArmISA::ArmFault::routeToHyp
virtual bool routeToHyp(ThreadContext *tc) const
Definition: faults.hh:243
gem5::ThreadContext::clearArchRegs
virtual void clearArchRegs()=0
gem5::ArmISA::MISCREG_HSR
@ MISCREG_HSR
Definition: misc.hh:282
gem5::ArmISA::MISCREG_SEV_MAILBOX
@ MISCREG_SEV_MAILBOX
Definition: misc.hh:92
gem5::ArmISA::ArmFault::SRT
@ SRT
Definition: faults.hh:138
gem5::ArmISA::HardwareBreakpoint::invoke
void invoke(ThreadContext *tc, const StaticInstPtr &inst=nullStaticInstPtr) override
Definition: faults.cc:1644
gem5::ThreadContext::threadId
virtual int threadId() const =0
gem5::ArmISA::DataAbort::sse
uint8_t sse
Definition: faults.hh:516
trace.hh
gem5::ArmISA::MISCREG_ELR_EL3
@ MISCREG_ELR_EL3
Definition: misc.hh:633
gem5::ArmISA::ArmFault::vectorCatch
bool vectorCatch(ThreadContext *tc, const StaticInstPtr &inst)
Definition: faults.cc:730
gem5::ArmISA::Interrupt::routeToHyp
bool routeToHyp(ThreadContext *tc) const override
Definition: faults.cc:1477
gem5::ArmISA::PrefetchAbort::ec
ExceptionClass ec(ThreadContext *tc) const override
Definition: faults.cc:1274
gem5::ArmISA::DataAbort::routeToHyp
bool routeToHyp(ThreadContext *tc) const override
Definition: faults.cc:1367
gem5::ArmISA::HypervisorCall::routeToMonitor
bool routeToMonitor(ThreadContext *tc) const override
Definition: faults.cc:930
gem5::ArmISA::DataAbort::ar
bool ar
Definition: faults.hh:522
gem5::ArmISA::IllegalInstSetStateFault::routeToHyp
bool routeToHyp(ThreadContext *tc) const override
Definition: faults.cc:1824
gem5::ArmISA::SystemError::invoke
void invoke(ThreadContext *tc, const StaticInstPtr &inst=nullStaticInstPtr) override
Definition: faults.cc:1573
gem5::ArmISA::EC_SMC_TO_HYP
@ EC_SMC_TO_HYP
Definition: types.hh:312
self_debug.hh
gem5::ArmSystem::haveEL
static bool haveEL(ThreadContext *tc, ArmISA::ExceptionLevel el)
Return true if the system implements a specific exception level.
Definition: system.cc:138
gem5::ArmISA::ArmFault::machInst
ExtMachInst machInst
Definition: faults.hh:67
gem5::ArmISA::MODE_ABORT
@ MODE_ABORT
Definition: types.hh:286
gem5::ArmISA::MISCREG_HCR_EL2
@ MISCREG_HCR_EL2
Definition: misc.hh:586
gem5::ArmISA::ArmFault::armPcOffset
virtual uint8_t armPcOffset(bool isHyp)=0
gem5::ArmISA::SPAlignmentFault::routeToHyp
bool routeToHyp(ThreadContext *tc) const override
Definition: faults.cc:1562
gem5::ArmISA::EC_SOFTWARE_STEP_CURR_EL
@ EC_SOFTWARE_STEP_CURR_EL
Definition: types.hh:337
gem5::ArmISA::ArmFault::fromMode
OperatingMode fromMode
Definition: faults.hh:76
gem5::ArmISA::EC_SVC_64
@ EC_SVC_64
Definition: types.hh:314
gem5::ArmISA::MISCREG_FAR_EL2
@ MISCREG_FAR_EL2
Definition: misc.hh:651
gem5::ArmISA::MISCREG_FAR_EL3
@ MISCREG_FAR_EL3
Definition: misc.hh:653
gem5::ArmISA::SupervisorCall::ec
ExceptionClass ec(ThreadContext *tc) const override
Definition: faults.cc:889
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40
gem5::ArmISA::MISCREG_HPFAR_EL2
@ MISCREG_HPFAR_EL2
Definition: misc.hh:652
gem5::ArmISA::ArmFault::routeToMonitor
virtual bool routeToMonitor(ThreadContext *tc) const =0
gem5::ArmISA::IllegalInstSetStateFault::IllegalInstSetStateFault
IllegalInstSetStateFault()
Definition: faults.cc:1820
gem5::ArmISA::AbortFault< PrefetchAbort >::source
uint8_t source
Definition: faults.hh:454
gem5::ArmISA::EC_HW_BREAKPOINT
@ EC_HW_BREAKPOINT
Definition: types.hh:332
gem5::ArmISA::MISCREG_HPFAR
@ MISCREG_HPFAR
Definition: misc.hh:291
gem5::ArmISA::MISCREG_ESR_EL1
@ MISCREG_ESR_EL1
Definition: misc.hh:639
gem5::ArmISA::cond
cond
Definition: pcstate.hh:62
gem5::ArmISA::CCREG_V
@ CCREG_V
Definition: cc.hh:51
gem5::ArmISA::MISCREG_VBAR_EL1
@ MISCREG_VBAR_EL1
Definition: misc.hh:736
gem5::ArmISA::ArmFault::longDescFaultSources
static uint8_t longDescFaultSources[NumFaultSources]
Encodings of the fault sources when the long-desc.
Definition: faults.hh:128
gem5::ArmISA::AbortFault
Definition: faults.hh:436
gem5::ArmISA::ArmFault::SAS
@ SAS
Definition: faults.hh:136
gem5::BaseCPU::clearInterrupts
void clearInterrupts(ThreadID tid)
Definition: base.hh:250
gem5::ArmISA::MISCREG_SPSR_HYP
@ MISCREG_SPSR_HYP
Definition: misc.hh:68
gem5::ArmISA::ArmStaticInst::annotateFault
virtual void annotateFault(ArmFault *fault)
Definition: static_inst.hh:532
thread_context.hh
gem5::ArmISA::ArmFault::UnknownTran
@ UnknownTran
Definition: faults.hh:154
gem5::ArmISA::OperatingMode
OperatingMode
Definition: types.hh:272
gem5::ArmISA::ArmFault::OVA
@ OVA
Definition: faults.hh:135
gem5::ArmISA::EC_STACK_PTR_ALIGNMENT
@ EC_STACK_PTR_ALIGNMENT
Definition: types.hh:328
gem5::StaticInst::advancePC
virtual void advancePC(TheISA::PCState &pc_state) const =0
gem5::ArmISA::EC_WATCHPOINT_CURR_EL
@ EC_WATCHPOINT_CURR_EL
Definition: types.hh:340
gem5::ArmISA::SoftwareStepFault::stepped
bool stepped
Definition: faults.hh:664
gem5::Workload::syscall
virtual void syscall(ThreadContext *tc)
Definition: workload.hh:106
gem5::ArmSystem::haveVirtualization
bool haveVirtualization() const
Returns true if this system implements the virtualization Extensions.
Definition: system.hh:171
gem5::ArmISA::AbortFault< DataAbort >::s1ptw
bool s1ptw
Definition: faults.hh:457
gem5::ArmISA::VirtualFastInterrupt::VirtualFastInterrupt
VirtualFastInterrupt()
Definition: faults.cc:1539
gem5::ArmISA::SecureMonitorTrap::overrideEc
ExceptionClass overrideEc
Definition: faults.hh:396
gem5::ArmISA::EC_DATA_ABORT_CURR_EL
@ EC_DATA_ABORT_CURR_EL
Definition: types.hh:327
gem5::ArmISA::getMPIDR
RegVal getMPIDR(ArmSystem *arm_sys, ThreadContext *tc)
This helper function is returning the value of MPIDR_EL1.
Definition: utility.cc:162
gem5::ArmISA::Interrupt::abortDisable
bool abortDisable(ThreadContext *tc) override
Definition: faults.cc:1485
gem5::ArmISA::ExceptionLevel
ExceptionLevel
Definition: types.hh:264
panic
#define panic(...)
This implements a cprintf based panic() function.
Definition: logging.hh:177
gem5::ArmISA::Watchpoint::ec
ExceptionClass ec(ThreadContext *tc) const override
Definition: faults.cc:1725
gem5::ArmISA::mode
Bitfield< 4, 0 > mode
Definition: misc_types.hh:73
gem5::ArmISA::INT_SEV
@ INT_SEV
Definition: interrupts.hh:64
gem5::ThreadContext::setMiscRegNoEffect
virtual void setMiscRegNoEffect(RegIndex misc_reg, RegVal val)=0
gem5::ArmISA::ArmFault::fiqDisable
virtual bool fiqDisable(ThreadContext *tc)=0
gem5::ArmISA::Watchpoint::write
bool write
Definition: faults.hh:647
gem5::ArmISA::MISCREG_SPSR_UND
@ MISCREG_SPSR_UND
Definition: misc.hh:69

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