gem5  v21.1.0.2
isa.cc
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37 
38 #include "arch/arm/isa.hh"
39 
40 #include "arch/arm/faults.hh"
41 #include "arch/arm/htm.hh"
42 #include "arch/arm/interrupts.hh"
43 #include "arch/arm/mmu.hh"
44 #include "arch/arm/pmu.hh"
45 #include "arch/arm/self_debug.hh"
46 #include "arch/arm/system.hh"
47 #include "arch/arm/tlbi_op.hh"
48 #include "cpu/base.hh"
49 #include "cpu/checker/cpu.hh"
50 #include "cpu/reg_class.hh"
51 #include "debug/Arm.hh"
52 #include "debug/MiscRegs.hh"
53 #include "dev/arm/generic_timer.hh"
54 #include "dev/arm/gic_v3.hh"
56 #include "params/ArmISA.hh"
57 #include "sim/faults.hh"
58 #include "sim/stat_control.hh"
59 #include "sim/system.hh"
60 
61 namespace gem5
62 {
63 
64 namespace ArmISA
65 {
66 
67 ISA::ISA(const Params &p) : BaseISA(p), system(NULL),
68  _decoderFlavor(p.decoderFlavor), pmu(p.pmu), impdefAsNop(p.impdef_nop),
69  afterStartup(false)
70 {
71  _regClasses.emplace_back(NUM_INTREGS, INTREG_ZERO);
72  _regClasses.emplace_back(0);
73  _regClasses.emplace_back(NumVecRegs);
75  _regClasses.emplace_back(NumVecPredRegs);
76  _regClasses.emplace_back(NUM_CCREGS);
77  _regClasses.emplace_back(NUM_MISCREGS);
78 
80 
81  // Hook up a dummy device if we haven't been configured with a
82  // real PMU. By using a dummy device, we don't need to check that
83  // the PMU exist every time we try to access a PMU register.
84  if (!pmu)
85  pmu = &dummyDevice;
86 
87  // Give all ISA devices a pointer to this ISA
88  pmu->setISA(this);
89 
90  system = dynamic_cast<ArmSystem *>(p.system);
91 
92  // Cache system-level properties
93  if (FullSystem && system) {
101  haveSVE = system->haveSVE();
102  haveVHE = system->haveVHE();
103  havePAN = system->havePAN();
105  sveVL = system->sveVL();
106  haveLSE = system->haveLSE();
107  haveTME = system->haveTME();
108  } else {
109  highestELIs64 = true; // ArmSystem::highestELIs64 does the same
111  haveCrypto = true;
112  haveLargeAsid64 = false;
113  physAddrRange = 32; // dummy value
114  haveSVE = true;
115  haveVHE = false;
116  havePAN = false;
117  haveSecEL2 = true;
118  sveVL = p.sve_vl_se;
119  haveLSE = true;
120  haveTME = true;
121  }
122 
123  selfDebug = new SelfDebug();
126 
127  clear();
128 }
129 
131 
132 void
134 {
135  const Params &p(params());
136 
137  // Invalidate cached copies of miscregs in the TLBs
138  if (tc) {
140  }
141 
142  SCTLR sctlr_rst = miscRegs[MISCREG_SCTLR_RST];
143  memset(miscRegs, 0, sizeof(miscRegs));
144 
145  initID32(p);
146 
147  // We always initialize AArch64 ID registers even
148  // if we are in AArch32. This is done since if we
149  // are in SE mode we don't know if our ArmProcess is
150  // AArch32 or AArch64
151  initID64(p);
152 
153  // Start with an event in the mailbox
155 
156  // Separate Instruction and Data TLBs
157  miscRegs[MISCREG_TLBTR] = 1;
158 
159  MVFR0 mvfr0 = 0;
160  mvfr0.advSimdRegisters = 2;
161  mvfr0.singlePrecision = 2;
162  mvfr0.doublePrecision = 2;
163  mvfr0.vfpExceptionTrapping = 0;
164  mvfr0.divide = 1;
165  mvfr0.squareRoot = 1;
166  mvfr0.shortVectors = 1;
167  mvfr0.roundingModes = 1;
168  miscRegs[MISCREG_MVFR0] = mvfr0;
169 
170  MVFR1 mvfr1 = 0;
171  mvfr1.flushToZero = 1;
172  mvfr1.defaultNaN = 1;
173  mvfr1.advSimdLoadStore = 1;
174  mvfr1.advSimdInteger = 1;
175  mvfr1.advSimdSinglePrecision = 1;
176  mvfr1.advSimdHalfPrecision = 1;
177  mvfr1.vfpHalfPrecision = 1;
178  miscRegs[MISCREG_MVFR1] = mvfr1;
179 
180  // Reset values of PRRR and NMRR are implementation dependent
181 
182  // @todo: PRRR and NMRR in secure state?
184  (1 << 19) | // 19
185  (0 << 18) | // 18
186  (0 << 17) | // 17
187  (1 << 16) | // 16
188  (2 << 14) | // 15:14
189  (0 << 12) | // 13:12
190  (2 << 10) | // 11:10
191  (2 << 8) | // 9:8
192  (2 << 6) | // 7:6
193  (2 << 4) | // 5:4
194  (1 << 2) | // 3:2
195  0; // 1:0
196 
198  (1 << 30) | // 31:30
199  (0 << 26) | // 27:26
200  (0 << 24) | // 25:24
201  (3 << 22) | // 23:22
202  (2 << 20) | // 21:20
203  (0 << 18) | // 19:18
204  (0 << 16) | // 17:16
205  (1 << 14) | // 15:14
206  (0 << 12) | // 13:12
207  (2 << 10) | // 11:10
208  (0 << 8) | // 9:8
209  (3 << 6) | // 7:6
210  (2 << 4) | // 5:4
211  (0 << 2) | // 3:2
212  0; // 1:0
213 
214  if (FullSystem && system->highestELIs64()) {
215  // Initialize AArch64 state
216  clear64(p);
217  return;
218  }
219 
220  // Initialize AArch32 state...
221  clear32(p, sctlr_rst);
222 }
223 
224 void
225 ISA::clear32(const ArmISAParams &p, const SCTLR &sctlr_rst)
226 {
227  CPSR cpsr = 0;
228  cpsr.mode = MODE_USER;
229 
230  if (FullSystem) {
232  }
233 
234  miscRegs[MISCREG_CPSR] = cpsr;
235  updateRegMap(cpsr);
236 
237  SCTLR sctlr = 0;
238  sctlr.te = (bool) sctlr_rst.te;
239  sctlr.nmfi = (bool) sctlr_rst.nmfi;
240  sctlr.v = (bool) sctlr_rst.v;
241  sctlr.u = 1;
242  sctlr.xp = 1;
243  sctlr.rao2 = 1;
244  sctlr.rao3 = 1;
245  sctlr.rao4 = 0xf; // SCTLR[6:3]
246  sctlr.uci = 1;
247  sctlr.dze = 1;
248  miscRegs[MISCREG_SCTLR_NS] = sctlr;
249  miscRegs[MISCREG_SCTLR_RST] = sctlr_rst;
250  miscRegs[MISCREG_HCPTR] = 0;
251 
252  miscRegs[MISCREG_CPACR] = 0;
253 
254  miscRegs[MISCREG_FPSID] = p.fpsid;
255 
256  if (haveLPAE) {
257  TTBCR ttbcr = miscRegs[MISCREG_TTBCR_NS];
258  ttbcr.eae = 0;
259  miscRegs[MISCREG_TTBCR_NS] = ttbcr;
260  // Enforce consistency with system-level settings
262  }
263 
264  if (haveSecurity) {
265  miscRegs[MISCREG_SCTLR_S] = sctlr;
266  miscRegs[MISCREG_SCR] = 0;
268  } else {
269  // we're always non-secure
270  miscRegs[MISCREG_SCR] = 1;
271  }
272 
273  //XXX We need to initialize the rest of the state.
274 }
275 
276 void
277 ISA::clear64(const ArmISAParams &p)
278 {
279  CPSR cpsr = 0;
280  Addr rvbar = system->resetAddr();
281  switch (system->highestEL()) {
282  // Set initial EL to highest implemented EL using associated stack
283  // pointer (SP_ELx); set RVBAR_ELx to implementation defined reset
284  // value
285  case EL3:
286  cpsr.mode = MODE_EL3H;
287  miscRegs[MISCREG_RVBAR_EL3] = rvbar;
288  break;
289  case EL2:
290  cpsr.mode = MODE_EL2H;
291  miscRegs[MISCREG_RVBAR_EL2] = rvbar;
292  break;
293  case EL1:
294  cpsr.mode = MODE_EL1H;
295  miscRegs[MISCREG_RVBAR_EL1] = rvbar;
296  break;
297  default:
298  panic("Invalid highest implemented exception level");
299  break;
300  }
301 
302  // Initialize rest of CPSR
303  cpsr.daif = 0xf; // Mask all interrupts
304  cpsr.ss = 0;
305  cpsr.il = 0;
306  miscRegs[MISCREG_CPSR] = cpsr;
307  updateRegMap(cpsr);
308 
309  // Initialize other control registers
310  miscRegs[MISCREG_MPIDR_EL1] = 0x80000000;
311  if (haveSecurity) {
312  miscRegs[MISCREG_SCTLR_EL3] = 0x30c50830;
313  miscRegs[MISCREG_SCR_EL3] = 0x00000030; // RES1 fields
314  } else if (haveVirtualization) {
315  // also MISCREG_SCTLR_EL2 (by mapping)
316  miscRegs[MISCREG_HSCTLR] = 0x30c50830;
317  } else {
318  // also MISCREG_SCTLR_EL1 (by mapping)
319  miscRegs[MISCREG_SCTLR_NS] = 0x30d00800 | 0x00050030; // RES1 | init
320  // Always non-secure
322  }
323 }
324 
325 void
326 ISA::initID32(const ArmISAParams &p)
327 {
328  // Initialize configurable default values
329 
330  uint32_t midr;
331  if (p.midr != 0x0)
332  midr = p.midr;
333  else if (highestELIs64)
334  // Cortex-A57 TRM r0p0 MIDR
335  midr = 0x410fd070;
336  else
337  // Cortex-A15 TRM r0p0 MIDR
338  midr = 0x410fc0f0;
339 
340  miscRegs[MISCREG_MIDR] = midr;
341  miscRegs[MISCREG_MIDR_EL1] = midr;
342  miscRegs[MISCREG_VPIDR] = midr;
343 
344  miscRegs[MISCREG_ID_ISAR0] = p.id_isar0;
345  miscRegs[MISCREG_ID_ISAR1] = p.id_isar1;
346  miscRegs[MISCREG_ID_ISAR2] = p.id_isar2;
347  miscRegs[MISCREG_ID_ISAR3] = p.id_isar3;
348  miscRegs[MISCREG_ID_ISAR4] = p.id_isar4;
349  miscRegs[MISCREG_ID_ISAR5] = p.id_isar5;
350  miscRegs[MISCREG_ID_ISAR6] = p.id_isar6;
351 
352  miscRegs[MISCREG_ID_MMFR0] = p.id_mmfr0;
353  miscRegs[MISCREG_ID_MMFR1] = p.id_mmfr1;
354  miscRegs[MISCREG_ID_MMFR2] = p.id_mmfr2;
355  miscRegs[MISCREG_ID_MMFR3] = p.id_mmfr3;
356  miscRegs[MISCREG_ID_MMFR4] = p.id_mmfr4;
357 
359  miscRegs[MISCREG_ID_ISAR5], 19, 4,
360  haveCrypto ? 0x1112 : 0x0);
361 }
362 
363 void
364 ISA::initID64(const ArmISAParams &p)
365 {
366  // Initialize configurable id registers
367  miscRegs[MISCREG_ID_AA64AFR0_EL1] = p.id_aa64afr0_el1;
368  miscRegs[MISCREG_ID_AA64AFR1_EL1] = p.id_aa64afr1_el1;
370  (p.id_aa64dfr0_el1 & 0xfffffffffffff0ffULL) |
371  (p.pmu ? 0x0000000000000100ULL : 0); // Enable PMUv3
372 
373  miscRegs[MISCREG_ID_AA64DFR1_EL1] = p.id_aa64dfr1_el1;
374  miscRegs[MISCREG_ID_AA64ISAR0_EL1] = p.id_aa64isar0_el1;
375  miscRegs[MISCREG_ID_AA64ISAR1_EL1] = p.id_aa64isar1_el1;
376  miscRegs[MISCREG_ID_AA64MMFR0_EL1] = p.id_aa64mmfr0_el1;
377  miscRegs[MISCREG_ID_AA64MMFR1_EL1] = p.id_aa64mmfr1_el1;
378  miscRegs[MISCREG_ID_AA64MMFR2_EL1] = p.id_aa64mmfr2_el1;
379 
381  (p.pmu ? 0x03000000ULL : 0); // Enable PMUv3
382 
384 
385  // SVE
386  miscRegs[MISCREG_ID_AA64ZFR0_EL1] = 0; // SVEver 0
387  if (haveSecurity) {
389  } else if (haveVirtualization) {
391  } else {
393  }
394 
395  // Enforce consistency with system-level settings...
396 
397  // EL3
400  haveSecurity ? 0x2 : 0x0);
401  // EL2
404  haveVirtualization ? 0x2 : 0x0);
405  // SVE
408  haveSVE ? 0x1 : 0x0);
409  // SecEL2
412  haveSecEL2 ? 0x1 : 0x0);
415  haveSecEL2 ? 0x1 : 0x0);
416  // Large ASID support
419  haveLargeAsid64 ? 0x2 : 0x0);
420  // Physical address size
424  // Crypto
427  haveCrypto ? 0x1112 : 0x0);
428  // LSE
431  haveLSE ? 0x2 : 0x0);
432  // VHE
435  haveVHE ? 0x1 : 0x0);
436  // PAN
439  havePAN ? 0x1 : 0x0);
440  // TME
443  haveTME ? 0x1 : 0x0);
444 }
445 
446 void
448 {
450 
451  if (tc) {
453 
454  if (haveTME) {
455  std::unique_ptr<BaseHTMCheckpoint> cpt(new HTMCheckpoint());
456  tc->setHtmCheckpointPtr(std::move(cpt));
457  }
458  }
459 
460  afterStartup = true;
461 }
462 
463 void
465 {
467 
468  if (!system)
469  return;
470 
471  selfDebug->init(tc);
472 
473  Gicv3 *gicv3 = dynamic_cast<Gicv3 *>(system->getGIC());
474  if (!gicv3)
475  return;
476 
477  if (!gicv3CpuInterface)
478  gicv3CpuInterface.reset(gicv3->getCPUInterface(tc->contextId()));
479 
480  gicv3CpuInterface->setISA(this);
481  gicv3CpuInterface->setThreadContext(tc);
482 }
483 
484 void
486 {
487  tc = new_tc;
489 }
490 
491 static void
493 {
494  auto src_mode = src->getIsaPtr()->vecRegRenameMode(src);
495 
496  // The way vector registers are copied (VecReg vs VecElem) is relevant
497  // in the O3 model only.
498  if (src_mode == enums::Full) {
499  for (auto idx = 0; idx < NumVecRegs; idx++)
500  dest->setVecRegFlat(idx, src->readVecRegFlat(idx));
501  } else {
502  for (auto idx = 0; idx < NumVecRegs; idx++)
503  for (auto elem_idx = 0; elem_idx < NumVecElemPerVecReg; elem_idx++)
504  dest->setVecElemFlat(
505  idx, elem_idx, src->readVecElemFlat(idx, elem_idx));
506  }
507 }
508 
509 void
511 {
512  for (int i = 0; i < NUM_INTREGS; i++)
513  tc->setIntRegFlat(i, src->readIntRegFlat(i));
514 
515  for (int i = 0; i < NUM_CCREGS; i++)
516  tc->setCCReg(i, src->readCCReg(i));
517 
518  for (int i = 0; i < NUM_MISCREGS; i++)
520 
521  copyVecRegs(src, tc);
522 
523  // setMiscReg "with effect" will set the misc register mapping correctly.
524  // e.g. updateRegMap(val)
526 
527  // Copy over the PC State
528  tc->pcState(src->pcState());
529 
530  // Invalidate the tlb misc register cache
531  static_cast<MMU *>(tc->getMMUPtr())->invalidateMiscReg();
532 }
533 
534 RegVal
535 ISA::readMiscRegNoEffect(int misc_reg) const
536 {
537  assert(misc_reg < NUM_MISCREGS);
538 
539  const auto &reg = lookUpMiscReg[misc_reg]; // bit masks
540  const auto &map = getMiscIndices(misc_reg);
541  int lower = map.first, upper = map.second;
542  // NB!: apply architectural masks according to desired register,
543  // despite possibly getting value from different (mapped) register.
544  auto val = !upper ? miscRegs[lower] : ((miscRegs[lower] & mask(32))
545  |(miscRegs[upper] << 32));
546  if (val & reg.res0()) {
547  DPRINTF(MiscRegs, "Reading MiscReg %s with set res0 bits: %#x\n",
548  miscRegName[misc_reg], val & reg.res0());
549  }
550  if ((val & reg.res1()) != reg.res1()) {
551  DPRINTF(MiscRegs, "Reading MiscReg %s with clear res1 bits: %#x\n",
552  miscRegName[misc_reg], (val & reg.res1()) ^ reg.res1());
553  }
554  return (val & ~reg.raz()) | reg.rao(); // enforce raz/rao
555 }
556 
557 
558 RegVal
559 ISA::readMiscReg(int misc_reg)
560 {
561  CPSR cpsr = 0;
562  PCState pc = 0;
563  SCR scr = 0;
564 
565  if (misc_reg == MISCREG_CPSR) {
566  cpsr = miscRegs[misc_reg];
567  pc = tc->pcState();
568  cpsr.j = pc.jazelle() ? 1 : 0;
569  cpsr.t = pc.thumb() ? 1 : 0;
570  return cpsr;
571  }
572 
573 #ifndef NDEBUG
574  if (!miscRegInfo[misc_reg][MISCREG_IMPLEMENTED]) {
575  if (miscRegInfo[misc_reg][MISCREG_WARN_NOT_FAIL])
576  warn("Unimplemented system register %s read.\n",
577  miscRegName[misc_reg]);
578  else
579  panic("Unimplemented system register %s read.\n",
580  miscRegName[misc_reg]);
581  }
582 #endif
583  misc_reg = redirectRegVHE(tc, misc_reg);
584 
585  switch (unflattenMiscReg(misc_reg)) {
586  case MISCREG_HCR:
587  case MISCREG_HCR2:
588  if (!haveVirtualization)
589  return 0;
590  break;
591  case MISCREG_CPACR:
592  {
593  const uint32_t ones = (uint32_t)(-1);
594  CPACR cpacrMask = 0;
595  // Only cp10, cp11, and ase are implemented, nothing else should
596  // be readable? (straight copy from the write code)
597  cpacrMask.cp10 = ones;
598  cpacrMask.cp11 = ones;
599  cpacrMask.asedis = ones;
600 
601  // Security Extensions may limit the readability of CPACR
602  if (haveSecurity) {
605  if (scr.ns && (cpsr.mode != MODE_MON) && ELIs32(tc, EL3)) {
606  NSACR nsacr = readMiscRegNoEffect(MISCREG_NSACR);
607  // NB: Skipping the full loop, here
608  if (!nsacr.cp10) cpacrMask.cp10 = 0;
609  if (!nsacr.cp11) cpacrMask.cp11 = 0;
610  }
611  }
613  val &= cpacrMask;
614  DPRINTF(MiscRegs, "Reading misc reg %s: %#x\n",
615  miscRegName[misc_reg], val);
616  return val;
617  }
618  case MISCREG_MPIDR:
619  case MISCREG_MPIDR_EL1:
620  return readMPIDR(system, tc);
621  case MISCREG_VMPIDR:
622  case MISCREG_VMPIDR_EL2:
623  // top bit defined as RES1
624  return readMiscRegNoEffect(misc_reg) | 0x80000000;
625  case MISCREG_ID_AFR0: // not implemented, so alias MIDR
626  case MISCREG_REVIDR: // not implemented, so alias MIDR
627  case MISCREG_MIDR:
630  if ((cpsr.mode == MODE_HYP) || isSecure(tc)) {
631  return readMiscRegNoEffect(misc_reg);
632  } else {
634  }
635  break;
636  case MISCREG_JOSCR: // Jazelle trivial implementation, RAZ/WI
637  case MISCREG_JMCR: // Jazelle trivial implementation, RAZ/WI
638  case MISCREG_JIDR: // Jazelle trivial implementation, RAZ/WI
639  case MISCREG_AIDR: // AUX ID set to 0
640  case MISCREG_TCMTR: // No TCM's
641  return 0;
642 
643  case MISCREG_CLIDR:
644  warn_once("The clidr register always reports 0 caches.\n");
645  warn_once("clidr LoUIS field of 0b001 to match current "
646  "ARM implementations.\n");
647  return 0x00200000;
648  case MISCREG_CCSIDR:
649  warn_once("The ccsidr register isn't implemented and "
650  "always reads as 0.\n");
651  break;
652  case MISCREG_CTR: // AArch32, ARMv7, top bit set
653  case MISCREG_CTR_EL0: // AArch64
654  {
655  //all caches have the same line size in gem5
656  //4 byte words in ARM
657  unsigned lineSizeWords =
658  tc->getSystemPtr()->cacheLineSize() / 4;
659  unsigned log2LineSizeWords = 0;
660 
661  while (lineSizeWords >>= 1) {
662  ++log2LineSizeWords;
663  }
664 
665  CTR ctr = 0;
666  //log2 of minimun i-cache line size (words)
667  ctr.iCacheLineSize = log2LineSizeWords;
668  //b11 - gem5 uses pipt
669  ctr.l1IndexPolicy = 0x3;
670  //log2 of minimum d-cache line size (words)
671  ctr.dCacheLineSize = log2LineSizeWords;
672  //log2 of max reservation size (words)
673  ctr.erg = log2LineSizeWords;
674  //log2 of max writeback size (words)
675  ctr.cwg = log2LineSizeWords;
676  //b100 - gem5 format is ARMv7
677  ctr.format = 0x4;
678 
679  return ctr;
680  }
681  case MISCREG_ACTLR:
682  warn("Not doing anything for miscreg ACTLR\n");
683  break;
684 
689  return pmu->readMiscReg(misc_reg);
690 
691  case MISCREG_CPSR_Q:
692  panic("shouldn't be reading this register seperately\n");
693  case MISCREG_FPSCR_QC:
695  case MISCREG_FPSCR_EXC:
697  case MISCREG_FPSR:
698  {
699  const uint32_t ones = (uint32_t)(-1);
700  FPSCR fpscrMask = 0;
701  fpscrMask.ioc = ones;
702  fpscrMask.dzc = ones;
703  fpscrMask.ofc = ones;
704  fpscrMask.ufc = ones;
705  fpscrMask.ixc = ones;
706  fpscrMask.idc = ones;
707  fpscrMask.qc = ones;
708  fpscrMask.v = ones;
709  fpscrMask.c = ones;
710  fpscrMask.z = ones;
711  fpscrMask.n = ones;
712  return readMiscRegNoEffect(MISCREG_FPSCR) & (uint32_t)fpscrMask;
713  }
714  case MISCREG_FPCR:
715  {
716  const uint32_t ones = (uint32_t)(-1);
717  FPSCR fpscrMask = 0;
718  fpscrMask.len = ones;
719  fpscrMask.fz16 = ones;
720  fpscrMask.stride = ones;
721  fpscrMask.rMode = ones;
722  fpscrMask.fz = ones;
723  fpscrMask.dn = ones;
724  fpscrMask.ahp = ones;
725  return readMiscRegNoEffect(MISCREG_FPSCR) & (uint32_t)fpscrMask;
726  }
727  case MISCREG_NZCV:
728  {
729  CPSR cpsr = 0;
730  cpsr.nz = tc->readCCReg(CCREG_NZ);
731  cpsr.c = tc->readCCReg(CCREG_C);
732  cpsr.v = tc->readCCReg(CCREG_V);
733  return cpsr;
734  }
735  case MISCREG_DAIF:
736  {
737  CPSR cpsr = 0;
738  cpsr.daif = (uint8_t) ((CPSR) miscRegs[MISCREG_CPSR]).daif;
739  return cpsr;
740  }
741  case MISCREG_SP_EL0:
742  {
743  return tc->readIntReg(INTREG_SP0);
744  }
745  case MISCREG_SP_EL1:
746  {
747  return tc->readIntReg(INTREG_SP1);
748  }
749  case MISCREG_SP_EL2:
750  {
751  return tc->readIntReg(INTREG_SP2);
752  }
753  case MISCREG_SPSEL:
754  {
755  return miscRegs[MISCREG_CPSR] & 0x1;
756  }
757  case MISCREG_CURRENTEL:
758  {
759  return miscRegs[MISCREG_CPSR] & 0xc;
760  }
761  case MISCREG_PAN:
762  {
763  return miscRegs[MISCREG_CPSR] & 0x400000;
764  }
765  case MISCREG_L2CTLR:
766  {
767  // mostly unimplemented, just set NumCPUs field from sim and return
768  L2CTLR l2ctlr = 0;
769  // b00:1CPU to b11:4CPUs
770  l2ctlr.numCPUs = tc->getSystemPtr()->threads.size() - 1;
771  return l2ctlr;
772  }
773  case MISCREG_DBGDIDR:
774  /* For now just implement the version number.
775  * ARMv7, v7.1 Debug architecture (0b0101 --> 0x5)
776  */
777  return 0x5 << 16;
778  case MISCREG_DBGDSCRint:
780  case MISCREG_ISR:
781  {
782  auto ic = dynamic_cast<ArmISA::Interrupts *>(
784  return ic->getISR(
788  }
789  case MISCREG_ISR_EL1:
790  {
791  auto ic = dynamic_cast<ArmISA::Interrupts *>(
793  return ic->getISR(
797  }
798  case MISCREG_DCZID_EL0:
799  return 0x04; // DC ZVA clear 64-byte chunks
800  case MISCREG_HCPTR:
801  {
802  RegVal val = readMiscRegNoEffect(misc_reg);
803  // The trap bit associated with CP14 is defined as RAZ
804  val &= ~(1 << 14);
805  // If a CP bit in NSACR is 0 then the corresponding bit in
806  // HCPTR is RAO/WI
807  bool secure_lookup = haveSecurity && isSecure(tc);
808  if (!secure_lookup) {
810  val |= (mask ^ 0x7FFF) & 0xBFFF;
811  }
812  // Set the bits for unimplemented coprocessors to RAO/WI
813  val |= 0x33FF;
814  return (val);
815  }
816  case MISCREG_HDFAR: // alias for secure DFAR
818  case MISCREG_HIFAR: // alias for secure IFAR
820 
821  case MISCREG_ID_PFR0:
822  // !ThumbEE | !Jazelle | Thumb | ARM
823  return 0x00000031;
824  case MISCREG_ID_PFR1:
825  { // Timer | Virti | !M Profile | TrustZone | ARMv4
826  bool haveTimer = (system->getGenericTimer() != NULL);
827  return 0x00000001
828  | (haveSecurity ? 0x00000010 : 0x0)
829  | (haveVirtualization ? 0x00001000 : 0x0)
830  | (haveTimer ? 0x00010000 : 0x0);
831  }
833  return 0x0000000000000002 | // AArch{64,32} supported at EL0
834  0x0000000000000020 | // EL1
835  (haveVirtualization ? 0x0000000000000200 : 0) | // EL2
836  (haveSecurity ? 0x0000000000002000 : 0) | // EL3
837  (haveSVE ? 0x0000000100000000 : 0) | // SVE
838  (haveSecEL2 ? 0x0000001000000000 : 0) | // SecEL2
839  (gicv3CpuInterface ? 0x0000000001000000 : 0);
841  return 0; // bits [63:0] RES0 (reserved for future use)
842 
843  // Generic Timer registers
846  return getGenericTimer().readMiscReg(misc_reg);
847 
851  return getGICv3CPUInterface().readMiscReg(misc_reg);
852 
853  default:
854  break;
855 
856  }
857  return readMiscRegNoEffect(misc_reg);
858 }
859 
860 void
862 {
863  assert(misc_reg < NUM_MISCREGS);
864 
865  const auto &reg = lookUpMiscReg[misc_reg]; // bit masks
866  const auto &map = getMiscIndices(misc_reg);
867  int lower = map.first, upper = map.second;
868 
869  auto v = (val & ~reg.wi()) | reg.rao();
870  if (upper > 0) {
871  miscRegs[lower] = bits(v, 31, 0);
872  miscRegs[upper] = bits(v, 63, 32);
873  DPRINTF(MiscRegs, "Writing MiscReg %s (%d %d:%d) : %#x\n",
874  miscRegName[misc_reg], misc_reg, lower, upper, v);
875  } else {
876  miscRegs[lower] = v;
877  DPRINTF(MiscRegs, "Writing MiscReg %s (%d %d) : %#x\n",
878  miscRegName[misc_reg], misc_reg, lower, v);
879  }
880 }
881 
882 void
883 ISA::setMiscReg(int misc_reg, RegVal val)
884 {
885 
886  RegVal newVal = val;
887  bool secure_lookup;
888  SCR scr;
889 
890  if (misc_reg == MISCREG_CPSR) {
891  updateRegMap(val);
892 
893 
894  CPSR old_cpsr = miscRegs[MISCREG_CPSR];
895  int old_mode = old_cpsr.mode;
896  CPSR cpsr = val;
897  if (old_mode != cpsr.mode || cpsr.il != old_cpsr.il) {
899  }
900 
901  if (cpsr.pan != old_cpsr.pan) {
903  }
904 
905  DPRINTF(Arm, "Updating CPSR from %#x to %#x f:%d i:%d a:%d mode:%#x\n",
906  miscRegs[misc_reg], cpsr, cpsr.f, cpsr.i, cpsr.a, cpsr.mode);
907  PCState pc = tc->pcState();
908  pc.nextThumb(cpsr.t);
909  pc.nextJazelle(cpsr.j);
910  pc.illegalExec(cpsr.il == 1);
911  selfDebug->setDebugMask(cpsr.d == 1);
912 
913  tc->getDecoderPtr()->setSveLen((getCurSveVecLenInBits() >> 7) - 1);
914 
915  // Follow slightly different semantics if a CheckerCPU object
916  // is connected
917  CheckerCPU *checker = tc->getCheckerCpuPtr();
918  if (checker) {
920  } else {
921  tc->pcState(pc);
922  }
923  } else {
924 #ifndef NDEBUG
925  if (!miscRegInfo[misc_reg][MISCREG_IMPLEMENTED]) {
926  if (miscRegInfo[misc_reg][MISCREG_WARN_NOT_FAIL])
927  warn("Unimplemented system register %s write with %#x.\n",
928  miscRegName[misc_reg], val);
929  else
930  panic("Unimplemented system register %s write with %#x.\n",
931  miscRegName[misc_reg], val);
932  }
933 #endif
934  misc_reg = redirectRegVHE(tc, misc_reg);
935 
936  switch (unflattenMiscReg(misc_reg)) {
937  case MISCREG_CPACR:
938  {
939 
940  const uint32_t ones = (uint32_t)(-1);
941  CPACR cpacrMask = 0;
942  // Only cp10, cp11, and ase are implemented, nothing else should
943  // be writable
944  cpacrMask.cp10 = ones;
945  cpacrMask.cp11 = ones;
946  cpacrMask.asedis = ones;
947 
948  // Security Extensions may limit the writability of CPACR
949  if (haveSecurity) {
951  CPSR cpsr = readMiscRegNoEffect(MISCREG_CPSR);
952  if (scr.ns && (cpsr.mode != MODE_MON) && ELIs32(tc, EL3)) {
953  NSACR nsacr = readMiscRegNoEffect(MISCREG_NSACR);
954  // NB: Skipping the full loop, here
955  if (!nsacr.cp10) cpacrMask.cp10 = 0;
956  if (!nsacr.cp11) cpacrMask.cp11 = 0;
957  }
958  }
959 
961  newVal &= cpacrMask;
962  newVal |= old_val & ~cpacrMask;
963  DPRINTF(MiscRegs, "Writing misc reg %s: %#x\n",
964  miscRegName[misc_reg], newVal);
965  }
966  break;
967  case MISCREG_CPACR_EL1:
968  {
969  const uint32_t ones = (uint32_t)(-1);
970  CPACR cpacrMask = 0;
971  cpacrMask.tta = ones;
972  cpacrMask.fpen = ones;
973  if (haveSVE) {
974  cpacrMask.zen = ones;
975  }
976  newVal &= cpacrMask;
977  DPRINTF(MiscRegs, "Writing misc reg %s: %#x\n",
978  miscRegName[misc_reg], newVal);
979  }
980  break;
981  case MISCREG_CPTR_EL2:
982  {
983  const HCR hcr = readMiscRegNoEffect(MISCREG_HCR_EL2);
984  const uint32_t ones = (uint32_t)(-1);
985  CPTR cptrMask = 0;
986  cptrMask.tcpac = ones;
987  cptrMask.tta = ones;
988  cptrMask.tfp = ones;
989  if (haveSVE) {
990  cptrMask.tz = ones;
991  cptrMask.zen = hcr.e2h ? ones : 0;
992  }
993  cptrMask.fpen = hcr.e2h ? ones : 0;
994  newVal &= cptrMask;
995  cptrMask = 0;
996  cptrMask.res1_13_12_el2 = ones;
997  cptrMask.res1_7_0_el2 = ones;
998  if (!haveSVE) {
999  cptrMask.res1_8_el2 = ones;
1000  }
1001  cptrMask.res1_9_el2 = ones;
1002  newVal |= cptrMask;
1003  DPRINTF(MiscRegs, "Writing misc reg %s: %#x\n",
1004  miscRegName[misc_reg], newVal);
1005  }
1006  break;
1007  case MISCREG_CPTR_EL3:
1008  {
1009  const uint32_t ones = (uint32_t)(-1);
1010  CPTR cptrMask = 0;
1011  cptrMask.tcpac = ones;
1012  cptrMask.tta = ones;
1013  cptrMask.tfp = ones;
1014  if (haveSVE) {
1015  cptrMask.ez = ones;
1016  }
1017  newVal &= cptrMask;
1018  DPRINTF(MiscRegs, "Writing misc reg %s: %#x\n",
1019  miscRegName[misc_reg], newVal);
1020  }
1021  break;
1022  case MISCREG_CSSELR:
1023  warn_once("The csselr register isn't implemented.\n");
1024  return;
1025 
1026  case MISCREG_DC_ZVA_Xt:
1027  warn("Calling DC ZVA! Not Implemeted! Expect WEIRD results\n");
1028  return;
1029 
1030  case MISCREG_FPSCR:
1031  {
1032  const uint32_t ones = (uint32_t)(-1);
1033  FPSCR fpscrMask = 0;
1034  fpscrMask.ioc = ones;
1035  fpscrMask.dzc = ones;
1036  fpscrMask.ofc = ones;
1037  fpscrMask.ufc = ones;
1038  fpscrMask.ixc = ones;
1039  fpscrMask.idc = ones;
1040  fpscrMask.ioe = ones;
1041  fpscrMask.dze = ones;
1042  fpscrMask.ofe = ones;
1043  fpscrMask.ufe = ones;
1044  fpscrMask.ixe = ones;
1045  fpscrMask.ide = ones;
1046  fpscrMask.len = ones;
1047  fpscrMask.fz16 = ones;
1048  fpscrMask.stride = ones;
1049  fpscrMask.rMode = ones;
1050  fpscrMask.fz = ones;
1051  fpscrMask.dn = ones;
1052  fpscrMask.ahp = ones;
1053  fpscrMask.qc = ones;
1054  fpscrMask.v = ones;
1055  fpscrMask.c = ones;
1056  fpscrMask.z = ones;
1057  fpscrMask.n = ones;
1058  newVal = (newVal & (uint32_t)fpscrMask) |
1060  ~(uint32_t)fpscrMask);
1061  tc->getDecoderPtr()->setContext(newVal);
1062  }
1063  break;
1064  case MISCREG_FPSR:
1065  {
1066  const uint32_t ones = (uint32_t)(-1);
1067  FPSCR fpscrMask = 0;
1068  fpscrMask.ioc = ones;
1069  fpscrMask.dzc = ones;
1070  fpscrMask.ofc = ones;
1071  fpscrMask.ufc = ones;
1072  fpscrMask.ixc = ones;
1073  fpscrMask.idc = ones;
1074  fpscrMask.qc = ones;
1075  fpscrMask.v = ones;
1076  fpscrMask.c = ones;
1077  fpscrMask.z = ones;
1078  fpscrMask.n = ones;
1079  newVal = (newVal & (uint32_t)fpscrMask) |
1081  ~(uint32_t)fpscrMask);
1082  misc_reg = MISCREG_FPSCR;
1083  }
1084  break;
1085  case MISCREG_FPCR:
1086  {
1087  const uint32_t ones = (uint32_t)(-1);
1088  FPSCR fpscrMask = 0;
1089  fpscrMask.len = ones;
1090  fpscrMask.fz16 = ones;
1091  fpscrMask.stride = ones;
1092  fpscrMask.rMode = ones;
1093  fpscrMask.fz = ones;
1094  fpscrMask.dn = ones;
1095  fpscrMask.ahp = ones;
1096  newVal = (newVal & (uint32_t)fpscrMask) |
1098  ~(uint32_t)fpscrMask);
1099  misc_reg = MISCREG_FPSCR;
1100  }
1101  break;
1102  case MISCREG_CPSR_Q:
1103  {
1104  assert(!(newVal & ~CpsrMaskQ));
1105  newVal = readMiscRegNoEffect(MISCREG_CPSR) | newVal;
1106  misc_reg = MISCREG_CPSR;
1107  }
1108  break;
1109  case MISCREG_FPSCR_QC:
1110  {
1112  (newVal & FpscrQcMask);
1113  misc_reg = MISCREG_FPSCR;
1114  }
1115  break;
1116  case MISCREG_FPSCR_EXC:
1117  {
1119  (newVal & FpscrExcMask);
1120  misc_reg = MISCREG_FPSCR;
1121  }
1122  break;
1123  case MISCREG_FPEXC:
1124  {
1125  // vfpv3 architecture, section B.6.1 of DDI04068
1126  // bit 29 - valid only if fpexc[31] is 0
1127  const uint32_t fpexcMask = 0x60000000;
1128  newVal = (newVal & fpexcMask) |
1129  (readMiscRegNoEffect(MISCREG_FPEXC) & ~fpexcMask);
1130  }
1131  break;
1132  case MISCREG_HCR2:
1133  if (!haveVirtualization)
1134  return;
1135  break;
1136  case MISCREG_HCR:
1137  {
1138  const HDCR mdcr = tc->readMiscRegNoEffect(MISCREG_MDCR_EL2);
1139  selfDebug->setenableTDETGE((HCR)val, mdcr);
1140  if (!haveVirtualization)
1141  return;
1142  }
1143  break;
1144 
1145  case MISCREG_HDCR:
1146  {
1147  const HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
1148  selfDebug->setenableTDETGE(hcr, (HDCR)val);
1149  }
1150  break;
1151  case MISCREG_DBGOSLAR:
1152  {
1153  OSL r = tc->readMiscReg(MISCREG_DBGOSLSR);
1154  const uint32_t temp = (val == 0xC5ACCE55)? 0x1 : 0x0;
1155  selfDebug->updateOSLock((RegVal) temp);
1156  r.oslk = bits(temp,0);
1158  }
1159  break;
1160  case MISCREG_DBGBCR0:
1161  selfDebug->updateDBGBCR(0, val);
1162  break;
1163  case MISCREG_DBGBCR1:
1164  selfDebug->updateDBGBCR(1, val);
1165  break;
1166  case MISCREG_DBGBCR2:
1167  selfDebug->updateDBGBCR(2, val);
1168  break;
1169  case MISCREG_DBGBCR3:
1170  selfDebug->updateDBGBCR(3, val);
1171  break;
1172  case MISCREG_DBGBCR4:
1173  selfDebug->updateDBGBCR(4, val);
1174  break;
1175  case MISCREG_DBGBCR5:
1176  selfDebug->updateDBGBCR(5, val);
1177  break;
1178  case MISCREG_DBGBCR6:
1179  selfDebug->updateDBGBCR(6, val);
1180  break;
1181  case MISCREG_DBGBCR7:
1182  selfDebug->updateDBGBCR(7, val);
1183  break;
1184  case MISCREG_DBGBCR8:
1185  selfDebug->updateDBGBCR(8, val);
1186  break;
1187  case MISCREG_DBGBCR9:
1188  selfDebug->updateDBGBCR(9, val);
1189  break;
1190  case MISCREG_DBGBCR10:
1191  selfDebug->updateDBGBCR(10, val);
1192  break;
1193  case MISCREG_DBGBCR11:
1194  selfDebug->updateDBGBCR(11, val);
1195  break;
1196  case MISCREG_DBGBCR12:
1197  selfDebug->updateDBGBCR(12, val);
1198  break;
1199  case MISCREG_DBGBCR13:
1200  selfDebug->updateDBGBCR(13, val);
1201  break;
1202  case MISCREG_DBGBCR14:
1203  selfDebug->updateDBGBCR(14, val);
1204  break;
1205  case MISCREG_DBGBCR15:
1206  selfDebug->updateDBGBCR(15, val);
1207  break;
1208  case MISCREG_DBGWCR0:
1209  selfDebug->updateDBGWCR(0, val);
1210  break;
1211  case MISCREG_DBGWCR1:
1212  selfDebug->updateDBGWCR(1, val);
1213  break;
1214  case MISCREG_DBGWCR2:
1215  selfDebug->updateDBGWCR(2, val);
1216  break;
1217  case MISCREG_DBGWCR3:
1218  selfDebug->updateDBGWCR(3, val);
1219  break;
1220  case MISCREG_DBGWCR4:
1221  selfDebug->updateDBGWCR(4, val);
1222  break;
1223  case MISCREG_DBGWCR5:
1224  selfDebug->updateDBGWCR(5, val);
1225  break;
1226  case MISCREG_DBGWCR6:
1227  selfDebug->updateDBGWCR(6, val);
1228  break;
1229  case MISCREG_DBGWCR7:
1230  selfDebug->updateDBGWCR(7, val);
1231  break;
1232  case MISCREG_DBGWCR8:
1233  selfDebug->updateDBGWCR(8, val);
1234  break;
1235  case MISCREG_DBGWCR9:
1236  selfDebug->updateDBGWCR(9, val);
1237  break;
1238  case MISCREG_DBGWCR10:
1239  selfDebug->updateDBGWCR(10, val);
1240  break;
1241  case MISCREG_DBGWCR11:
1242  selfDebug->updateDBGWCR(11, val);
1243  break;
1244  case MISCREG_DBGWCR12:
1245  selfDebug->updateDBGWCR(12, val);
1246  break;
1247  case MISCREG_DBGWCR13:
1248  selfDebug->updateDBGWCR(13, val);
1249  break;
1250  case MISCREG_DBGWCR14:
1251  selfDebug->updateDBGWCR(14, val);
1252  break;
1253  case MISCREG_DBGWCR15:
1254  selfDebug->updateDBGWCR(15, val);
1255  break;
1256 
1257  case MISCREG_MDCR_EL2:
1258  {
1259  const HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
1260  selfDebug->setenableTDETGE(hcr, (HDCR)val);
1261  }
1262  break;
1263  case MISCREG_SDCR:
1264  case MISCREG_MDCR_EL3:
1265  {
1266  selfDebug->setbSDD(val);
1267  }
1268  break;
1269  case MISCREG_DBGDSCRext:
1270  {
1272  DBGDS32 r = tc->readMiscReg(MISCREG_DBGDSCRint);
1273  DBGDS32 v = val;
1274  r.moe = v.moe;
1275  r.udccdis = v.udccdis;
1276  r.mdbgen = v.mdbgen;
1279  }
1280 
1281  break;
1282  case MISCREG_MDSCR_EL1:
1283  {
1285  }
1286  break;
1287 
1288  case MISCREG_OSLAR_EL1:
1289  {
1292  r.oslk = bits(val, 0);
1293  r.oslm_3 = 1;
1295  }
1296  break;
1297 
1298  case MISCREG_DBGBCR0_EL1:
1299  selfDebug->updateDBGBCR(0, val);
1300  break;
1301  case MISCREG_DBGBCR1_EL1:
1302  selfDebug->updateDBGBCR(1, val);
1303  break;
1304  case MISCREG_DBGBCR2_EL1:
1305  selfDebug->updateDBGBCR(2, val);
1306  break;
1307  case MISCREG_DBGBCR3_EL1:
1308  selfDebug->updateDBGBCR(3, val);
1309  break;
1310  case MISCREG_DBGBCR4_EL1:
1311  selfDebug->updateDBGBCR(4, val);
1312  break;
1313  case MISCREG_DBGBCR5_EL1:
1314  selfDebug->updateDBGBCR(5, val);
1315  break;
1316  case MISCREG_DBGBCR6_EL1:
1317  selfDebug->updateDBGBCR(6, val);
1318  break;
1319  case MISCREG_DBGBCR7_EL1:
1320  selfDebug->updateDBGBCR(7, val);
1321  break;
1322  case MISCREG_DBGBCR8_EL1:
1323  selfDebug->updateDBGBCR(8, val);
1324  break;
1325  case MISCREG_DBGBCR9_EL1:
1326  selfDebug->updateDBGBCR(9, val);
1327  break;
1328  case MISCREG_DBGBCR10_EL1:
1329  selfDebug->updateDBGBCR(10, val);
1330  break;
1331  case MISCREG_DBGBCR11_EL1:
1332  selfDebug->updateDBGBCR(11, val);
1333  break;
1334  case MISCREG_DBGBCR12_EL1:
1335  selfDebug->updateDBGBCR(12, val);
1336  break;
1337  case MISCREG_DBGBCR13_EL1:
1338  selfDebug->updateDBGBCR(13, val);
1339  break;
1340  case MISCREG_DBGBCR14_EL1:
1341  selfDebug->updateDBGBCR(14, val);
1342  break;
1343  case MISCREG_DBGBCR15_EL1:
1344  selfDebug->updateDBGBCR(15, val);
1345  break;
1346  case MISCREG_DBGWCR0_EL1:
1347  selfDebug->updateDBGWCR(0, val);
1348  break;
1349  case MISCREG_DBGWCR1_EL1:
1350  selfDebug->updateDBGWCR(1, val);
1351  break;
1352  case MISCREG_DBGWCR2_EL1:
1353  selfDebug->updateDBGWCR(2, val);
1354  break;
1355  case MISCREG_DBGWCR3_EL1:
1356  selfDebug->updateDBGWCR(3, val);
1357  break;
1358  case MISCREG_DBGWCR4_EL1:
1359  selfDebug->updateDBGWCR(4, val);
1360  break;
1361  case MISCREG_DBGWCR5_EL1:
1362  selfDebug->updateDBGWCR(5, val);
1363  break;
1364  case MISCREG_DBGWCR6_EL1:
1365  selfDebug->updateDBGWCR(6, val);
1366  break;
1367  case MISCREG_DBGWCR7_EL1:
1368  selfDebug->updateDBGWCR(7, val);
1369  break;
1370  case MISCREG_DBGWCR8_EL1:
1371  selfDebug->updateDBGWCR(8, val);
1372  break;
1373  case MISCREG_DBGWCR9_EL1:
1374  selfDebug->updateDBGWCR(9, val);
1375  break;
1376  case MISCREG_DBGWCR10_EL1:
1377  selfDebug->updateDBGWCR(10, val);
1378  break;
1379  case MISCREG_DBGWCR11_EL1:
1380  selfDebug->updateDBGWCR(11, val);
1381  break;
1382  case MISCREG_DBGWCR12_EL1:
1383  selfDebug->updateDBGWCR(12, val);
1384  break;
1385  case MISCREG_DBGWCR13_EL1:
1386  selfDebug->updateDBGWCR(13, val);
1387  break;
1388  case MISCREG_DBGWCR14_EL1:
1389  selfDebug->updateDBGWCR(14, val);
1390  break;
1391  case MISCREG_DBGWCR15_EL1:
1392  selfDebug->updateDBGWCR(15, val);
1393  break;
1394  case MISCREG_IFSR:
1395  {
1396  // ARM ARM (ARM DDI 0406C.b) B4.1.96
1397  const uint32_t ifsrMask =
1398  mask(31, 13) | mask(11, 11) | mask(8, 6);
1399  newVal = newVal & ~ifsrMask;
1400  }
1401  break;
1402  case MISCREG_DFSR:
1403  {
1404  // ARM ARM (ARM DDI 0406C.b) B4.1.52
1405  const uint32_t dfsrMask = mask(31, 14) | mask(8, 8);
1406  newVal = newVal & ~dfsrMask;
1407  }
1408  break;
1409  case MISCREG_AMAIR0:
1410  case MISCREG_AMAIR1:
1411  {
1412  // ARM ARM (ARM DDI 0406C.b) B4.1.5
1413  // Valid only with LPAE
1414  if (!haveLPAE)
1415  return;
1416  DPRINTF(MiscRegs, "Writing AMAIR: %#x\n", newVal);
1417  }
1418  break;
1419  case MISCREG_SCR:
1421  break;
1422  case MISCREG_SCTLR:
1423  {
1424  DPRINTF(MiscRegs, "Writing SCTLR: %#x\n", newVal);
1426 
1427  MiscRegIndex sctlr_idx;
1428  if (haveSecurity && !highestELIs64 && !scr.ns) {
1429  sctlr_idx = MISCREG_SCTLR_S;
1430  } else {
1431  sctlr_idx = MISCREG_SCTLR_NS;
1432  }
1433 
1434  SCTLR sctlr = miscRegs[sctlr_idx];
1435  SCTLR new_sctlr = newVal;
1436  new_sctlr.nmfi = ((bool)sctlr.nmfi) && !haveVirtualization;
1437  miscRegs[sctlr_idx] = (RegVal)new_sctlr;
1439  }
1440  case MISCREG_MIDR:
1441  case MISCREG_ID_PFR0:
1442  case MISCREG_ID_PFR1:
1443  case MISCREG_ID_DFR0:
1444  case MISCREG_ID_MMFR0:
1445  case MISCREG_ID_MMFR1:
1446  case MISCREG_ID_MMFR2:
1447  case MISCREG_ID_MMFR3:
1448  case MISCREG_ID_MMFR4:
1449  case MISCREG_ID_ISAR0:
1450  case MISCREG_ID_ISAR1:
1451  case MISCREG_ID_ISAR2:
1452  case MISCREG_ID_ISAR3:
1453  case MISCREG_ID_ISAR4:
1454  case MISCREG_ID_ISAR5:
1455 
1456  case MISCREG_MPIDR:
1457  case MISCREG_FPSID:
1458  case MISCREG_TLBTR:
1459  case MISCREG_MVFR0:
1460  case MISCREG_MVFR1:
1461 
1473  // ID registers are constants.
1474  return;
1475 
1476  // TLB Invalidate All
1477  case MISCREG_TLBIALL: // TLBI all entries, EL0&1,
1478  {
1479  assert32();
1480  scr = readMiscReg(MISCREG_SCR);
1481 
1482  TLBIALL tlbiOp(EL1, haveSecurity && !scr.ns);
1483  tlbiOp(tc);
1484  return;
1485  }
1486  // TLB Invalidate All, Inner Shareable
1487  case MISCREG_TLBIALLIS:
1488  {
1489  assert32();
1490  scr = readMiscReg(MISCREG_SCR);
1491 
1492  TLBIALL tlbiOp(EL1, haveSecurity && !scr.ns);
1493  tlbiOp.broadcast(tc);
1494  return;
1495  }
1496  // Instruction TLB Invalidate All
1497  case MISCREG_ITLBIALL:
1498  {
1499  assert32();
1500  scr = readMiscReg(MISCREG_SCR);
1501 
1502  ITLBIALL tlbiOp(EL1, haveSecurity && !scr.ns);
1503  tlbiOp(tc);
1504  return;
1505  }
1506  // Data TLB Invalidate All
1507  case MISCREG_DTLBIALL:
1508  {
1509  assert32();
1510  scr = readMiscReg(MISCREG_SCR);
1511 
1512  DTLBIALL tlbiOp(EL1, haveSecurity && !scr.ns);
1513  tlbiOp(tc);
1514  return;
1515  }
1516  // TLB Invalidate by VA
1517  // mcr tlbimval(is) is invalidating all matching entries
1518  // regardless of the level of lookup, since in gem5 we cache
1519  // in the tlb the last level of lookup only.
1520  case MISCREG_TLBIMVA:
1521  case MISCREG_TLBIMVAL:
1522  {
1523  assert32();
1524  scr = readMiscReg(MISCREG_SCR);
1525 
1526  TLBIMVA tlbiOp(EL1,
1527  haveSecurity && !scr.ns,
1528  mbits(newVal, 31, 12),
1529  bits(newVal, 7,0));
1530 
1531  tlbiOp(tc);
1532  return;
1533  }
1534  // TLB Invalidate by VA, Inner Shareable
1535  case MISCREG_TLBIMVAIS:
1536  case MISCREG_TLBIMVALIS:
1537  {
1538  assert32();
1539  scr = readMiscReg(MISCREG_SCR);
1540 
1541  TLBIMVA tlbiOp(EL1,
1542  haveSecurity && !scr.ns,
1543  mbits(newVal, 31, 12),
1544  bits(newVal, 7,0));
1545 
1546  tlbiOp.broadcast(tc);
1547  return;
1548  }
1549  // TLB Invalidate by ASID match
1550  case MISCREG_TLBIASID:
1551  {
1552  assert32();
1553  scr = readMiscReg(MISCREG_SCR);
1554 
1555  TLBIASID tlbiOp(EL1,
1556  haveSecurity && !scr.ns,
1557  bits(newVal, 7,0));
1558 
1559  tlbiOp(tc);
1560  return;
1561  }
1562  // TLB Invalidate by ASID match, Inner Shareable
1563  case MISCREG_TLBIASIDIS:
1564  {
1565  assert32();
1566  scr = readMiscReg(MISCREG_SCR);
1567 
1568  TLBIASID tlbiOp(EL1,
1569  haveSecurity && !scr.ns,
1570  bits(newVal, 7,0));
1571 
1572  tlbiOp.broadcast(tc);
1573  return;
1574  }
1575  // mcr tlbimvaal(is) is invalidating all matching entries
1576  // regardless of the level of lookup, since in gem5 we cache
1577  // in the tlb the last level of lookup only.
1578  // TLB Invalidate by VA, All ASID
1579  case MISCREG_TLBIMVAA:
1580  case MISCREG_TLBIMVAAL:
1581  {
1582  assert32();
1583  scr = readMiscReg(MISCREG_SCR);
1584 
1585  TLBIMVAA tlbiOp(EL1, haveSecurity && !scr.ns,
1586  mbits(newVal, 31,12));
1587 
1588  tlbiOp(tc);
1589  return;
1590  }
1591  // TLB Invalidate by VA, All ASID, Inner Shareable
1592  case MISCREG_TLBIMVAAIS:
1593  case MISCREG_TLBIMVAALIS:
1594  {
1595  assert32();
1596  scr = readMiscReg(MISCREG_SCR);
1597 
1598  TLBIMVAA tlbiOp(EL1, haveSecurity && !scr.ns,
1599  mbits(newVal, 31,12));
1600 
1601  tlbiOp.broadcast(tc);
1602  return;
1603  }
1604  // mcr tlbimvalh(is) is invalidating all matching entries
1605  // regardless of the level of lookup, since in gem5 we cache
1606  // in the tlb the last level of lookup only.
1607  // TLB Invalidate by VA, Hyp mode
1608  case MISCREG_TLBIMVAH:
1609  case MISCREG_TLBIMVALH:
1610  {
1611  assert32();
1612  scr = readMiscReg(MISCREG_SCR);
1613 
1614  TLBIMVAA tlbiOp(EL2, haveSecurity && !scr.ns,
1615  mbits(newVal, 31,12));
1616 
1617  tlbiOp(tc);
1618  return;
1619  }
1620  // TLB Invalidate by VA, Hyp mode, Inner Shareable
1621  case MISCREG_TLBIMVAHIS:
1622  case MISCREG_TLBIMVALHIS:
1623  {
1624  assert32();
1625  scr = readMiscReg(MISCREG_SCR);
1626 
1627  TLBIMVAA tlbiOp(EL2, haveSecurity && !scr.ns,
1628  mbits(newVal, 31,12));
1629 
1630  tlbiOp.broadcast(tc);
1631  return;
1632  }
1633  // mcr tlbiipas2l(is) is invalidating all matching entries
1634  // regardless of the level of lookup, since in gem5 we cache
1635  // in the tlb the last level of lookup only.
1636  // TLB Invalidate by Intermediate Physical Address, Stage 2
1637  case MISCREG_TLBIIPAS2:
1638  case MISCREG_TLBIIPAS2L:
1639  {
1640  assert32();
1641  scr = readMiscReg(MISCREG_SCR);
1642 
1643  TLBIIPA tlbiOp(EL1,
1644  haveSecurity && !scr.ns,
1645  static_cast<Addr>(bits(newVal, 35, 0)) << 12);
1646 
1647  tlbiOp(tc);
1648  return;
1649  }
1650  // TLB Invalidate by Intermediate Physical Address, Stage 2,
1651  // Inner Shareable
1652  case MISCREG_TLBIIPAS2IS:
1653  case MISCREG_TLBIIPAS2LIS:
1654  {
1655  assert32();
1656  scr = readMiscReg(MISCREG_SCR);
1657 
1658  TLBIIPA tlbiOp(EL1,
1659  haveSecurity && !scr.ns,
1660  static_cast<Addr>(bits(newVal, 35, 0)) << 12);
1661 
1662  tlbiOp.broadcast(tc);
1663  return;
1664  }
1665  // Instruction TLB Invalidate by VA
1666  case MISCREG_ITLBIMVA:
1667  {
1668  assert32();
1669  scr = readMiscReg(MISCREG_SCR);
1670 
1671  ITLBIMVA tlbiOp(EL1,
1672  haveSecurity && !scr.ns,
1673  mbits(newVal, 31, 12),
1674  bits(newVal, 7,0));
1675 
1676  tlbiOp(tc);
1677  return;
1678  }
1679  // Data TLB Invalidate by VA
1680  case MISCREG_DTLBIMVA:
1681  {
1682  assert32();
1683  scr = readMiscReg(MISCREG_SCR);
1684 
1685  DTLBIMVA tlbiOp(EL1,
1686  haveSecurity && !scr.ns,
1687  mbits(newVal, 31, 12),
1688  bits(newVal, 7,0));
1689 
1690  tlbiOp(tc);
1691  return;
1692  }
1693  // Instruction TLB Invalidate by ASID match
1694  case MISCREG_ITLBIASID:
1695  {
1696  assert32();
1697  scr = readMiscReg(MISCREG_SCR);
1698 
1699  ITLBIASID tlbiOp(EL1,
1700  haveSecurity && !scr.ns,
1701  bits(newVal, 7,0));
1702 
1703  tlbiOp(tc);
1704  return;
1705  }
1706  // Data TLB Invalidate by ASID match
1707  case MISCREG_DTLBIASID:
1708  {
1709  assert32();
1710  scr = readMiscReg(MISCREG_SCR);
1711 
1712  DTLBIASID tlbiOp(EL1,
1713  haveSecurity && !scr.ns,
1714  bits(newVal, 7,0));
1715 
1716  tlbiOp(tc);
1717  return;
1718  }
1719  // TLB Invalidate All, Non-Secure Non-Hyp
1720  case MISCREG_TLBIALLNSNH:
1721  {
1722  assert32();
1723 
1724  TLBIALLN tlbiOp(EL1);
1725  tlbiOp(tc);
1726  return;
1727  }
1728  // TLB Invalidate All, Non-Secure Non-Hyp, Inner Shareable
1729  case MISCREG_TLBIALLNSNHIS:
1730  {
1731  assert32();
1732 
1733  TLBIALLN tlbiOp(EL1);
1734  tlbiOp.broadcast(tc);
1735  return;
1736  }
1737  // TLB Invalidate All, Hyp mode
1738  case MISCREG_TLBIALLH:
1739  {
1740  assert32();
1741 
1742  TLBIALLN tlbiOp(EL2);
1743  tlbiOp(tc);
1744  return;
1745  }
1746  // TLB Invalidate All, Hyp mode, Inner Shareable
1747  case MISCREG_TLBIALLHIS:
1748  {
1749  assert32();
1750 
1751  TLBIALLN tlbiOp(EL2);
1752  tlbiOp.broadcast(tc);
1753  return;
1754  }
1755  // AArch64 TLB Invalidate All, EL3
1756  case MISCREG_TLBI_ALLE3:
1757  {
1758  assert64();
1759 
1760  TLBIALLEL tlbiOp(EL3, true);
1761  tlbiOp(tc);
1762  return;
1763  }
1764  // AArch64 TLB Invalidate All, EL3, Inner Shareable
1765  case MISCREG_TLBI_ALLE3IS:
1766  {
1767  assert64();
1768 
1769  TLBIALLEL tlbiOp(EL3, true);
1770  tlbiOp.broadcast(tc);
1771  return;
1772  }
1773  // AArch64 TLB Invalidate All, EL2
1774  case MISCREG_TLBI_ALLE2:
1775  {
1776  assert64();
1777  scr = readMiscReg(MISCREG_SCR);
1778 
1779  TLBIALLEL tlbiOp(EL2, haveSecurity && !scr.ns);
1780  tlbiOp(tc);
1781  return;
1782  }
1783  // AArch64 TLB Invalidate All, EL2, Inner Shareable
1784  case MISCREG_TLBI_ALLE2IS:
1785  {
1786  assert64();
1787  scr = readMiscReg(MISCREG_SCR);
1788 
1789  TLBIALLEL tlbiOp(EL2, haveSecurity && !scr.ns);
1790  tlbiOp.broadcast(tc);
1791  return;
1792  }
1793  // AArch64 TLB Invalidate All, EL1
1794  case MISCREG_TLBI_ALLE1:
1795  {
1796  assert64();
1797  scr = readMiscReg(MISCREG_SCR);
1798 
1799  TLBIALLEL tlbiOp(EL1, haveSecurity && !scr.ns);
1800  tlbiOp(tc);
1801  return;
1802  }
1803  // AArch64 TLB Invalidate All, EL1, Inner Shareable
1804  case MISCREG_TLBI_ALLE1IS:
1805  {
1806  assert64();
1807  scr = readMiscReg(MISCREG_SCR);
1808 
1809  TLBIALLEL tlbiOp(EL1, haveSecurity && !scr.ns);
1810  tlbiOp.broadcast(tc);
1811  return;
1812  }
1814  {
1815  assert64();
1816  scr = readMiscReg(MISCREG_SCR);
1817 
1818  TLBIVMALL tlbiOp(EL1, haveSecurity && !scr.ns, true);
1819  tlbiOp(tc);
1820  return;
1821  }
1822  case MISCREG_TLBI_VMALLE1:
1823  {
1824  assert64();
1825  scr = readMiscReg(MISCREG_SCR);
1826 
1827  HCR hcr = readMiscReg(MISCREG_HCR_EL2);
1828  bool is_host = (hcr.tge && hcr.e2h);
1829  ExceptionLevel target_el = is_host ? EL2 : EL1;
1830  TLBIVMALL tlbiOp(target_el, haveSecurity && !scr.ns, false);
1831  tlbiOp(tc);
1832  return;
1833  }
1835  {
1836  assert64();
1837  scr = readMiscReg(MISCREG_SCR);
1838 
1839  TLBIVMALL tlbiOp(EL1, haveSecurity && !scr.ns, true);
1840  tlbiOp.broadcast(tc);
1841  return;
1842  }
1844  {
1845  assert64();
1846  scr = readMiscReg(MISCREG_SCR);
1847 
1848  HCR hcr = readMiscReg(MISCREG_HCR_EL2);
1849  bool is_host = (hcr.tge && hcr.e2h);
1850  ExceptionLevel target_el = is_host ? EL2 : EL1;
1851  TLBIVMALL tlbiOp(target_el, haveSecurity && !scr.ns, false);
1852  tlbiOp.broadcast(tc);
1853  return;
1854  }
1855  // VAEx(IS) and VALEx(IS) are the same because TLBs
1856  // only store entries
1857  // from the last level of translation table walks
1858  // AArch64 TLB Invalidate by VA, EL3
1859  case MISCREG_TLBI_VAE3_Xt:
1860  case MISCREG_TLBI_VALE3_Xt:
1861  {
1862  assert64();
1863 
1864  TLBIMVA tlbiOp(EL3, true,
1865  static_cast<Addr>(bits(newVal, 43, 0)) << 12,
1866  0xbeef);
1867  tlbiOp(tc);
1868  return;
1869  }
1870  // AArch64 TLB Invalidate by VA, EL3, Inner Shareable
1873  {
1874  assert64();
1875 
1876  TLBIMVA tlbiOp(EL3, true,
1877  static_cast<Addr>(bits(newVal, 43, 0)) << 12,
1878  0xbeef);
1879 
1880  tlbiOp.broadcast(tc);
1881  return;
1882  }
1883  // AArch64 TLB Invalidate by VA, EL2
1884  case MISCREG_TLBI_VAE2_Xt:
1885  case MISCREG_TLBI_VALE2_Xt:
1886  {
1887  assert64();
1888  scr = readMiscReg(MISCREG_SCR);
1889 
1890  TLBIMVA tlbiOp(EL2, haveSecurity && !scr.ns,
1891  static_cast<Addr>(bits(newVal, 43, 0)) << 12,
1892  0xbeef);
1893  tlbiOp(tc);
1894  return;
1895  }
1896  // AArch64 TLB Invalidate by VA, EL2, Inner Shareable
1899  {
1900  assert64();
1901  scr = readMiscReg(MISCREG_SCR);
1902 
1903  TLBIMVA tlbiOp(EL2, haveSecurity && !scr.ns,
1904  static_cast<Addr>(bits(newVal, 43, 0)) << 12,
1905  0xbeef);
1906 
1907  tlbiOp.broadcast(tc);
1908  return;
1909  }
1910  // AArch64 TLB Invalidate by VA, EL1
1911  case MISCREG_TLBI_VAE1_Xt:
1912  case MISCREG_TLBI_VALE1_Xt:
1913  {
1914  assert64();
1915  scr = readMiscReg(MISCREG_SCR);
1916  auto asid = haveLargeAsid64 ? bits(newVal, 63, 48) :
1917  bits(newVal, 55, 48);
1918 
1919  HCR hcr = readMiscReg(MISCREG_HCR_EL2);
1920  bool is_host = (hcr.tge && hcr.e2h);
1921  ExceptionLevel target_el = is_host ? EL2 : EL1;
1922  TLBIMVA tlbiOp(target_el, haveSecurity && !scr.ns,
1923  static_cast<Addr>(bits(newVal, 43, 0)) << 12,
1924  asid);
1925 
1926  tlbiOp(tc);
1927  return;
1928  }
1929  // AArch64 TLB Invalidate by VA, EL1, Inner Shareable
1932  {
1933  assert64();
1934  scr = readMiscReg(MISCREG_SCR);
1935  auto asid = haveLargeAsid64 ? bits(newVal, 63, 48) :
1936  bits(newVal, 55, 48);
1937 
1938  HCR hcr = readMiscReg(MISCREG_HCR_EL2);
1939  bool is_host = (hcr.tge && hcr.e2h);
1940  ExceptionLevel target_el = is_host ? EL2 : EL1;
1941  TLBIMVA tlbiOp(target_el, haveSecurity && !scr.ns,
1942  static_cast<Addr>(bits(newVal, 43, 0)) << 12,
1943  asid);
1944 
1945  tlbiOp.broadcast(tc);
1946  return;
1947  }
1948  // AArch64 TLB Invalidate by ASID, EL1
1950  {
1951  assert64();
1952  scr = readMiscReg(MISCREG_SCR);
1953  auto asid = haveLargeAsid64 ? bits(newVal, 63, 48) :
1954  bits(newVal, 55, 48);
1955 
1956  HCR hcr = readMiscReg(MISCREG_HCR_EL2);
1957  bool is_host = (hcr.tge && hcr.e2h);
1958  ExceptionLevel target_el = is_host ? EL2 : EL1;
1959  TLBIASID tlbiOp(target_el, haveSecurity && !scr.ns, asid);
1960  tlbiOp(tc);
1961  return;
1962  }
1963  // AArch64 TLB Invalidate by ASID, EL1, Inner Shareable
1965  {
1966  assert64();
1967  scr = readMiscReg(MISCREG_SCR);
1968  auto asid = haveLargeAsid64 ? bits(newVal, 63, 48) :
1969  bits(newVal, 55, 48);
1970 
1971  HCR hcr = readMiscReg(MISCREG_HCR_EL2);
1972  bool is_host = (hcr.tge && hcr.e2h);
1973  ExceptionLevel target_el = is_host ? EL2 : EL1;
1974  TLBIASID tlbiOp(target_el, haveSecurity && !scr.ns, asid);
1975  tlbiOp.broadcast(tc);
1976  return;
1977  }
1978  // VAAE1(IS) and VAALE1(IS) are the same because TLBs only store
1979  // entries from the last level of translation table walks
1980  // AArch64 TLB Invalidate by VA, All ASID, EL1
1981  case MISCREG_TLBI_VAAE1_Xt:
1983  {
1984  assert64();
1985  scr = readMiscReg(MISCREG_SCR);
1986 
1987  HCR hcr = readMiscReg(MISCREG_HCR_EL2);
1988  bool is_host = (hcr.tge && hcr.e2h);
1989  ExceptionLevel target_el = is_host ? EL2 : EL1;
1990  TLBIMVAA tlbiOp(target_el, haveSecurity && !scr.ns,
1991  static_cast<Addr>(bits(newVal, 43, 0)) << 12);
1992 
1993  tlbiOp(tc);
1994  return;
1995  }
1996  // AArch64 TLB Invalidate by VA, All ASID, EL1, Inner Shareable
1999  {
2000  assert64();
2001  scr = readMiscReg(MISCREG_SCR);
2002 
2003  HCR hcr = readMiscReg(MISCREG_HCR_EL2);
2004  bool is_host = (hcr.tge && hcr.e2h);
2005  ExceptionLevel target_el = is_host ? EL2 : EL1;
2006  TLBIMVAA tlbiOp(target_el, haveSecurity && !scr.ns,
2007  static_cast<Addr>(bits(newVal, 43, 0)) << 12);
2008 
2009  tlbiOp.broadcast(tc);
2010  return;
2011  }
2012  // AArch64 TLB Invalidate by Intermediate Physical Address,
2013  // Stage 2, EL1
2016  {
2017  assert64();
2018  scr = readMiscReg(MISCREG_SCR);
2019 
2020  TLBIIPA tlbiOp(EL1, haveSecurity && !scr.ns,
2021  static_cast<Addr>(bits(newVal, 35, 0)) << 12);
2022 
2023  tlbiOp(tc);
2024  return;
2025  }
2026  // AArch64 TLB Invalidate by Intermediate Physical Address,
2027  // Stage 2, EL1, Inner Shareable
2030  {
2031  assert64();
2032  scr = readMiscReg(MISCREG_SCR);
2033 
2034  TLBIIPA tlbiOp(EL1, haveSecurity && !scr.ns,
2035  static_cast<Addr>(bits(newVal, 35, 0)) << 12);
2036 
2037  tlbiOp.broadcast(tc);
2038  return;
2039  }
2040  case MISCREG_ACTLR:
2041  warn("Not doing anything for write of miscreg ACTLR\n");
2042  break;
2043 
2047  case MISCREG_PMCR ... MISCREG_PMOVSSET:
2048  pmu->setMiscReg(misc_reg, newVal);
2049  break;
2050 
2051 
2052  case MISCREG_HSTR: // TJDBX, now redifined to be RES0
2053  {
2054  HSTR hstrMask = 0;
2055  hstrMask.tjdbx = 1;
2056  newVal &= ~((uint32_t) hstrMask);
2057  break;
2058  }
2059  case MISCREG_HCPTR:
2060  {
2061  // If a CP bit in NSACR is 0 then the corresponding bit in
2062  // HCPTR is RAO/WI. Same applies to NSASEDIS
2063  secure_lookup = haveSecurity && isSecure(tc);
2064  if (!secure_lookup) {
2066  RegVal mask =
2067  (readMiscRegNoEffect(MISCREG_NSACR) ^ 0x7FFF) & 0xBFFF;
2068  newVal = (newVal & ~mask) | (oldValue & mask);
2069  }
2070  break;
2071  }
2072  case MISCREG_HDFAR: // alias for secure DFAR
2073  misc_reg = MISCREG_DFAR_S;
2074  break;
2075  case MISCREG_HIFAR: // alias for secure IFAR
2076  misc_reg = MISCREG_IFAR_S;
2077  break;
2078  case MISCREG_ATS1CPR:
2080  return;
2081  case MISCREG_ATS1CPW:
2083  return;
2084  case MISCREG_ATS1CUR:
2086  TLB::UserMode, val);
2087  return;
2088  case MISCREG_ATS1CUW:
2090  TLB::UserMode, val);
2091  return;
2092  case MISCREG_ATS12NSOPR:
2093  if (!haveSecurity)
2094  panic("Security Extensions required for ATS12NSOPR");
2096  return;
2097  case MISCREG_ATS12NSOPW:
2098  if (!haveSecurity)
2099  panic("Security Extensions required for ATS12NSOPW");
2101  return;
2102  case MISCREG_ATS12NSOUR:
2103  if (!haveSecurity)
2104  panic("Security Extensions required for ATS12NSOUR");
2106  TLB::UserMode, val);
2107  return;
2108  case MISCREG_ATS12NSOUW:
2109  if (!haveSecurity)
2110  panic("Security Extensions required for ATS12NSOUW");
2112  TLB::UserMode, val);
2113  return;
2114  case MISCREG_ATS1HR:
2116  return;
2117  case MISCREG_ATS1HW:
2119  return;
2120  case MISCREG_TTBCR:
2121  {
2122  TTBCR ttbcr = readMiscRegNoEffect(MISCREG_TTBCR);
2123  const uint32_t ones = (uint32_t)(-1);
2124  TTBCR ttbcrMask = 0;
2125  TTBCR ttbcrNew = newVal;
2126 
2127  // ARM DDI 0406C.b, ARMv7-32
2128  ttbcrMask.n = ones; // T0SZ
2129  if (haveSecurity) {
2130  ttbcrMask.pd0 = ones;
2131  ttbcrMask.pd1 = ones;
2132  }
2133  ttbcrMask.epd0 = ones;
2134  ttbcrMask.irgn0 = ones;
2135  ttbcrMask.orgn0 = ones;
2136  ttbcrMask.sh0 = ones;
2137  ttbcrMask.ps = ones; // T1SZ
2138  ttbcrMask.a1 = ones;
2139  ttbcrMask.epd1 = ones;
2140  ttbcrMask.irgn1 = ones;
2141  ttbcrMask.orgn1 = ones;
2142  ttbcrMask.sh1 = ones;
2143  if (haveLPAE)
2144  ttbcrMask.eae = ones;
2145 
2146  if (haveLPAE && ttbcrNew.eae) {
2147  newVal = newVal & ttbcrMask;
2148  } else {
2149  newVal = (newVal & ttbcrMask) | (ttbcr & (~ttbcrMask));
2150  }
2151  // Invalidate TLB MiscReg
2153  break;
2154  }
2155  case MISCREG_TTBR0:
2156  case MISCREG_TTBR1:
2157  {
2158  TTBCR ttbcr = readMiscRegNoEffect(MISCREG_TTBCR);
2159  if (haveLPAE) {
2160  if (ttbcr.eae) {
2161  // ARMv7 bit 63-56, 47-40 reserved, UNK/SBZP
2162  // ARMv8 AArch32 bit 63-56 only
2163  uint64_t ttbrMask = mask(63,56) | mask(47,40);
2164  newVal = (newVal & (~ttbrMask));
2165  }
2166  }
2167  // Invalidate TLB MiscReg
2169  break;
2170  }
2171  case MISCREG_SCTLR_EL1:
2172  case MISCREG_CONTEXTIDR:
2173  case MISCREG_PRRR:
2174  case MISCREG_NMRR:
2175  case MISCREG_MAIR0:
2176  case MISCREG_MAIR1:
2177  case MISCREG_DACR:
2178  case MISCREG_VTTBR:
2179  case MISCREG_SCR_EL3:
2180  case MISCREG_TCR_EL1:
2181  case MISCREG_TCR_EL2:
2182  case MISCREG_TCR_EL3:
2183  case MISCREG_VTCR_EL2:
2184  case MISCREG_SCTLR_EL2:
2185  case MISCREG_SCTLR_EL3:
2186  case MISCREG_HSCTLR:
2187  case MISCREG_TTBR0_EL1:
2188  case MISCREG_TTBR1_EL1:
2189  case MISCREG_TTBR0_EL2:
2190  case MISCREG_TTBR1_EL2:
2191  case MISCREG_TTBR0_EL3:
2193  break;
2194  case MISCREG_HCR_EL2:
2195  {
2196  const HDCR mdcr = tc->readMiscRegNoEffect(MISCREG_MDCR_EL2);
2197  selfDebug->setenableTDETGE((HCR)val, mdcr);
2199  }
2200  break;
2201  case MISCREG_NZCV:
2202  {
2203  CPSR cpsr = val;
2204 
2205  tc->setCCReg(CCREG_NZ, cpsr.nz);
2206  tc->setCCReg(CCREG_C, cpsr.c);
2207  tc->setCCReg(CCREG_V, cpsr.v);
2208  }
2209  break;
2210  case MISCREG_DAIF:
2211  {
2212  CPSR cpsr = miscRegs[MISCREG_CPSR];
2213  cpsr.daif = (uint8_t) ((CPSR) newVal).daif;
2214  newVal = cpsr;
2215  misc_reg = MISCREG_CPSR;
2216  }
2217  break;
2218  case MISCREG_SP_EL0:
2219  tc->setIntReg(INTREG_SP0, newVal);
2220  break;
2221  case MISCREG_SP_EL1:
2222  tc->setIntReg(INTREG_SP1, newVal);
2223  break;
2224  case MISCREG_SP_EL2:
2225  tc->setIntReg(INTREG_SP2, newVal);
2226  break;
2227  case MISCREG_SPSEL:
2228  {
2229  CPSR cpsr = miscRegs[MISCREG_CPSR];
2230  cpsr.sp = (uint8_t) ((CPSR) newVal).sp;
2231  newVal = cpsr;
2232  misc_reg = MISCREG_CPSR;
2233  }
2234  break;
2235  case MISCREG_CURRENTEL:
2236  {
2237  CPSR cpsr = miscRegs[MISCREG_CPSR];
2238  cpsr.el = (uint8_t) ((CPSR) newVal).el;
2239  newVal = cpsr;
2240  misc_reg = MISCREG_CPSR;
2241  }
2242  break;
2243  case MISCREG_PAN:
2244  {
2245  // PAN is affecting data accesses
2247 
2248  CPSR cpsr = miscRegs[MISCREG_CPSR];
2249  cpsr.pan = (uint8_t) ((CPSR) newVal).pan;
2250  newVal = cpsr;
2251  misc_reg = MISCREG_CPSR;
2252  }
2253  break;
2254  case MISCREG_AT_S1E1R_Xt:
2256  return;
2257  case MISCREG_AT_S1E1W_Xt:
2259  return;
2260  case MISCREG_AT_S1E0R_Xt:
2262  TLB::UserMode, val);
2263  return;
2264  case MISCREG_AT_S1E0W_Xt:
2266  TLB::UserMode, val);
2267  return;
2268  case MISCREG_AT_S1E2R_Xt:
2270  return;
2271  case MISCREG_AT_S1E2W_Xt:
2273  return;
2274  case MISCREG_AT_S12E1R_Xt:
2276  return;
2277  case MISCREG_AT_S12E1W_Xt:
2279  return;
2280  case MISCREG_AT_S12E0R_Xt:
2282  TLB::UserMode, val);
2283  return;
2284  case MISCREG_AT_S12E0W_Xt:
2286  TLB::UserMode, val);
2287  return;
2288  case MISCREG_AT_S1E3R_Xt:
2290  return;
2291  case MISCREG_AT_S1E3W_Xt:
2293  return;
2294  case MISCREG_SPSR_EL3:
2295  case MISCREG_SPSR_EL2:
2296  case MISCREG_SPSR_EL1:
2297  {
2298  RegVal spsr_mask = havePAN ?
2299  ~(0x2 << 22) : ~(0x3 << 22);
2300 
2301  newVal = val & spsr_mask;
2302  break;
2303  }
2304  case MISCREG_L2CTLR:
2305  warn("miscreg L2CTLR (%s) written with %#x. ignored...\n",
2306  miscRegName[misc_reg], uint32_t(val));
2307  break;
2308 
2309  // Generic Timer registers
2312  getGenericTimer().setMiscReg(misc_reg, newVal);
2313  break;
2317  getGICv3CPUInterface().setMiscReg(misc_reg, newVal);
2318  return;
2319  case MISCREG_ZCR_EL3:
2320  case MISCREG_ZCR_EL2:
2321  case MISCREG_ZCR_EL1:
2322  tc->getDecoderPtr()->setSveLen((getCurSveVecLenInBits() >> 7) - 1);
2323  break;
2324  }
2325  }
2326  setMiscRegNoEffect(misc_reg, newVal);
2327 }
2328 
2329 BaseISADevice &
2331 {
2332  // We only need to create an ISA interface the first time we try
2333  // to access the timer.
2334  if (timer)
2335  return *timer.get();
2336 
2337  assert(system);
2338  GenericTimer *generic_timer(system->getGenericTimer());
2339  if (!generic_timer) {
2340  panic("Trying to get a generic timer from a system that hasn't "
2341  "been configured to use a generic timer.\n");
2342  }
2343 
2344  timer.reset(new GenericTimerISA(*generic_timer, tc->contextId()));
2345  timer->setThreadContext(tc);
2346 
2347  return *timer.get();
2348 }
2349 
2350 BaseISADevice &
2352 {
2353  panic_if(!gicv3CpuInterface, "GICV3 cpu interface is not registered!");
2354  return *gicv3CpuInterface.get();
2355 }
2356 
2357 unsigned
2359 {
2360  if (!FullSystem) {
2361  return sveVL * 128;
2362  }
2363 
2364  panic_if(!tc,
2365  "A ThreadContext is needed to determine the SVE vector length "
2366  "in full-system mode");
2367 
2368  CPSR cpsr = miscRegs[MISCREG_CPSR];
2369  ExceptionLevel el = (ExceptionLevel) (uint8_t) cpsr.el;
2370 
2371  unsigned len = 0;
2372 
2373  if (el == EL1 || (el == EL0 && !ELIsInHost(tc, el))) {
2374  len = static_cast<ZCR>(miscRegs[MISCREG_ZCR_EL1]).len;
2375  }
2376 
2377  if (el == EL2 || (el == EL0 && ELIsInHost(tc, el))) {
2378  len = static_cast<ZCR>(miscRegs[MISCREG_ZCR_EL2]).len;
2379  } else if (haveVirtualization && !isSecure(tc) &&
2380  (el == EL0 || el == EL1)) {
2381  len = std::min(
2382  len,
2383  static_cast<unsigned>(
2384  static_cast<ZCR>(miscRegs[MISCREG_ZCR_EL2]).len));
2385  }
2386 
2387  if (el == EL3) {
2388  len = static_cast<ZCR>(miscRegs[MISCREG_ZCR_EL3]).len;
2389  } else if (haveSecurity) {
2390  len = std::min(
2391  len,
2392  static_cast<unsigned>(
2393  static_cast<ZCR>(miscRegs[MISCREG_ZCR_EL3]).len));
2394  }
2395 
2396  len = std::min(len, sveVL - 1);
2397 
2398  return (len + 1) * 128;
2399 }
2400 
2401 void
2403 {
2404  DPRINTF(Checkpoint, "Serializing Arm Misc Registers\n");
2406 }
2407 
2408 void
2410 {
2411  DPRINTF(Checkpoint, "Unserializing Arm Misc Registers\n");
2413  CPSR tmp_cpsr = miscRegs[MISCREG_CPSR];
2414  updateRegMap(tmp_cpsr);
2415 }
2416 
2417 void
2420 {
2421  // If we're in timing mode then doing the translation in
2422  // functional mode then we're slightly distorting performance
2423  // results obtained from simulations. The translation should be
2424  // done in the same mode the core is running in. NOTE: This
2425  // can't be an atomic translation because that causes problems
2426  // with unexpected atomic snoop requests.
2427  warn_once("Doing AT (address translation) in functional mode! Fix Me!\n");
2428 
2429  auto req = std::make_shared<Request>(
2430  val, 0, flags, Request::funcRequestorId,
2431  tc->pcState().pc(), tc->contextId());
2432 
2434  req, tc, mode, tran_type);
2435 
2436  PAR par = 0;
2437  if (fault == NoFault) {
2438  Addr paddr = req->getPaddr();
2439  uint64_t attr = getMMUPtr(tc)->getAttr();
2440  uint64_t attr1 = attr >> 56;
2441  if (!attr1 || attr1 ==0x44) {
2442  attr |= 0x100;
2443  attr &= ~ uint64_t(0x80);
2444  }
2445  par = (paddr & mask(47, 12)) | attr;
2446  DPRINTF(MiscRegs,
2447  "MISCREG: Translated addr %#x: PAR_EL1: %#xx\n",
2448  val, par);
2449  } else {
2450  ArmFault *arm_fault = static_cast<ArmFault *>(fault.get());
2451  arm_fault->update(tc);
2452  // Set fault bit and FSR
2453  FSR fsr = arm_fault->getFsr(tc);
2454 
2455  par.f = 1; // F bit
2456  par.fst = fsr.status; // FST
2457  par.ptw = (arm_fault->iss() >> 7) & 0x1; // S1PTW
2458  par.s = arm_fault->isStage2() ? 1 : 0; // S
2459 
2460  DPRINTF(MiscRegs,
2461  "MISCREG: Translated addr %#x fault fsr %#x: PAR: %#x\n",
2462  val, fsr, par);
2463  }
2465  return;
2466 }
2467 
2468 void
2471 {
2472  // If we're in timing mode then doing the translation in
2473  // functional mode then we're slightly distorting performance
2474  // results obtained from simulations. The translation should be
2475  // done in the same mode the core is running in. NOTE: This
2476  // can't be an atomic translation because that causes problems
2477  // with unexpected atomic snoop requests.
2478  warn_once("Doing AT (address translation) in functional mode! Fix Me!\n");
2479 
2480  auto req = std::make_shared<Request>(
2481  val, 0, flags, Request::funcRequestorId,
2482  tc->pcState().pc(), tc->contextId());
2483 
2485  req, tc, mode, tran_type);
2486 
2487  PAR par = 0;
2488  if (fault == NoFault) {
2489  Addr paddr = req->getPaddr();
2490  TTBCR ttbcr = readMiscRegNoEffect(MISCREG_TTBCR);
2491  HCR hcr = readMiscRegNoEffect(MISCREG_HCR);
2492 
2493  uint8_t max_paddr_bit = 0;
2494  if (haveLPAE && (ttbcr.eae || tran_type & TLB::HypMode ||
2495  ((tran_type & TLB::S1S2NsTran) && hcr.vm) )) {
2496 
2497  max_paddr_bit = 39;
2498  } else {
2499  max_paddr_bit = 31;
2500  }
2501 
2502  par = (paddr & mask(max_paddr_bit, 12)) |
2503  (getMMUPtr(tc)->getAttr());
2504 
2505  DPRINTF(MiscRegs,
2506  "MISCREG: Translated addr 0x%08x: PAR: 0x%08x\n",
2507  val, par);
2508  } else {
2509  ArmFault *arm_fault = static_cast<ArmFault *>(fault.get());
2510  arm_fault->update(tc);
2511  // Set fault bit and FSR
2512  FSR fsr = arm_fault->getFsr(tc);
2513 
2514  par.f = 0x1; // F bit
2515  par.lpae = fsr.lpae;
2516  par.ptw = (arm_fault->iss() >> 7) & 0x1;
2517  par.s = arm_fault->isStage2() ? 1 : 0;
2518 
2519  if (par.lpae) {
2520  // LPAE - rearange fault status
2521  par.fst = fsr.status;
2522  } else {
2523  // VMSA - rearange fault status
2524  par.fs4_0 = fsr.fsLow | (fsr.fsHigh << 5);
2525  par.fs5 = fsr.ext;
2526  }
2527  DPRINTF(MiscRegs,
2528  "MISCREG: Translated addr 0x%08x fault fsr %#x: PAR: 0x%08x\n",
2529  val, fsr, par);
2530  }
2532  return;
2533 }
2534 
2537 {
2538  switch (FullSystem ? sys->highestEL() : EL1) {
2539  case EL0:
2540  case EL1: priv(); break;
2541  case EL2: hyp(); break;
2542  case EL3: mon(); break;
2543  }
2544  return *this;
2545 }
2546 
2547 } // namespace ArmISA
2548 } // namespace gem5
gem5::ThreadContext::setIntReg
virtual void setIntReg(RegIndex reg_idx, RegVal val)=0
gem5::ArmISA::MISCREG_CTR_EL0
@ MISCREG_CTR_EL0
Definition: misc.hh:575
gem5::ArmISA::MISCREG_SP_EL0
@ MISCREG_SP_EL0
Definition: misc.hh:616
gem5::ArmISA::MODE_EL2H
@ MODE_EL2H
Definition: types.hh:278
gem5::ThreadContext::pcStateNoRecord
virtual void pcStateNoRecord(const TheISA::PCState &val)=0
gem5::ArmISA::MISCREG_DBGWCR11
@ MISCREG_DBGWCR11
Definition: misc.hh:165
gem5::ArmISA::MISCREG_NSACR
@ MISCREG_NSACR
Definition: misc.hh:245
gic_v3_cpu_interface.hh
gem5::ArmISA::NumVecElemPerVecReg
constexpr unsigned NumVecElemPerVecReg
Definition: vec.hh:58
gem5::ArmISA::MISCREG_CPSR
@ MISCREG_CPSR
Definition: misc.hh:61
gem5::ArmISA::BaseISADevice::setISA
virtual void setISA(ISA *isa)
Definition: isa_device.cc:55
gem5::ArmISA::MISCREG_ID_MMFR4
@ MISCREG_ID_MMFR4
Definition: misc.hh:219
gem5::ArmISA::MISCREG_CPTR_EL2
@ MISCREG_CPTR_EL2
Definition: misc.hh:588
gem5::ArmISA::MISCREG_DBGBCR9_EL1
@ MISCREG_DBGBCR9_EL1
Definition: misc.hh:483
gem5::ArmISA::ITLBIALL
Instruction TLB Invalidate All.
Definition: tlbi_op.hh:136
gem5::ArmSystem::physAddrRange
uint8_t physAddrRange() const
Returns the supported physical address range in bits.
Definition: system.hh:255
gem5::ArmISA::MISCREG_TLBIMVALIS
@ MISCREG_TLBIMVALIS
Definition: misc.hh:325
gem5::ArmISA::CCREG_C
@ CCREG_C
Definition: cc.hh:50
gem5::ArmISA::MISCREG_VTTBR
@ MISCREG_VTTBR
Definition: misc.hh:448
gem5::ArmISA::MISCREG_PMCR
@ MISCREG_PMCR
Definition: misc.hh:351
gem5::ArmISA::SelfDebug::setenableTDETGE
void setenableTDETGE(HCR hcr, HDCR mdcr)
Definition: self_debug.hh:397
gem5::BaseMMU::Read
@ Read
Definition: mmu.hh:53
gem5::ArmISA::MISCREG_CSSELR
@ MISCREG_CSSELR
Definition: misc.hh:230
gem5::ArmISA::SelfDebug::init
void init(ThreadContext *tc)
Definition: self_debug.cc:327
gem5::ArmISA::MISCREG_DBGDIDR
@ MISCREG_DBGDIDR
Definition: misc.hh:95
gem5::ArmISA::ISA::dummyDevice
DummyISADevice dummyDevice
Dummy device for to handle non-existing ISA devices.
Definition: isa.hh:78
gem5::ArmISA::MISCREG_TTBR0_EL2
@ MISCREG_TTBR0_EL2
Definition: misc.hh:603
gem5::ArmISA::MISCREG_AT_S12E0R_Xt
@ MISCREG_AT_S12E0R_Xt
Definition: misc.hh:674
gem5::ThreadContext::readMiscReg
virtual RegVal readMiscReg(RegIndex misc_reg)=0
gem5::ArmISA::MISCREG_DBGBCR9
@ MISCREG_DBGBCR9
Definition: misc.hh:131
gem5::NoFault
constexpr decltype(nullptr) NoFault
Definition: types.hh:260
gem5::ThreadContext::getSystemPtr
virtual System * getSystemPtr()=0
gem5::ArmISA::MODE_MON
@ MODE_MON
Definition: types.hh:285
gem5::ArmISA::TLBIALLEL
Implementaton of AArch64 TLBI ALLE(1,2,3)(IS) instructions.
Definition: tlbi_op.hh:162
gem5::ArmISA::len
Bitfield< 18, 16 > len
Definition: misc_types.hh:444
gem5::ArmISA::MISCREG_TLBIALL
@ MISCREG_TLBIALL
Definition: misc.hh:333
gem5::ArmISA::MISCREG_HSTR
@ MISCREG_HSTR
Definition: misc.hh:252
gem5::BaseISA::tc
ThreadContext * tc
Definition: isa.hh:62
gem5::ArmISA::MISCREG_MDCR_EL3
@ MISCREG_MDCR_EL3
Definition: misc.hh:596
gem5::ArmISA::MISCREG_L2CTLR
@ MISCREG_L2CTLR
Definition: misc.hh:367
gem5::ArmISA::MISCREG_TLBI_ALLE3IS
@ MISCREG_TLBI_ALLE3IS
Definition: misc.hh:704
gem5::ArmISA::MISCREG_TTBR0_EL3
@ MISCREG_TTBR0_EL3
Definition: misc.hh:609
warn
#define warn(...)
Definition: logging.hh:245
gem5::ArmISA::ISA::redirectRegVHE
int redirectRegVHE(ThreadContext *tc, int misc_reg)
Returns the enconcing equivalent when VHE is implemented and HCR_EL2.E2H is enabled and executing at ...
Definition: isa.hh:756
gem5::System::Threads::size
int size() const
Definition: system.hh:216
gem5::ArmISA::MISCREG_ID_ISAR5
@ MISCREG_ID_ISAR5
Definition: misc.hh:225
gem5::ArmISA::ISA::selfDebug
SelfDebug * selfDebug
Definition: isa.hh:115
gem5::ArmISA::MISCREG_AMAIR1
@ MISCREG_AMAIR1
Definition: misc.hh:384
gem5::ArmISA::BaseISADevice::readMiscReg
virtual RegVal readMiscReg(int misc_reg)=0
Read a system register belonging to this device.
gem5::RegVal
uint64_t RegVal
Definition: types.hh:173
gem5::ArmISA::MISCREG_TLBI_VAAE1IS_Xt
@ MISCREG_TLBI_VAAE1IS_Xt
Definition: misc.hh:681
gem5::ArmISA::MISCREG_SCTLR_EL3
@ MISCREG_SCTLR_EL3
Definition: misc.hh:591
gem5::ArmISA::MISCREG_DBGWCR14_EL1
@ MISCREG_DBGWCR14_EL1
Definition: misc.hh:520
gem5::ArmISA::MISCREG_TLBIIPAS2L
@ MISCREG_TLBIIPAS2L
Definition: misc.hh:346
gem5::ArmISA::MISCREG_AMAIR0
@ MISCREG_AMAIR0
Definition: misc.hh:381
gem5::ArmISA::MISCREG_AT_S1E3W_Xt
@ MISCREG_AT_S1E3W_Xt
Definition: misc.hh:677
gem5::ArmSystem::haveLSE
bool haveLSE() const
Returns true if LSE is implemented (ARMv8.1)
Definition: system.hh:238
gem5::ArmISA::MISCREG_PMEVTYPER5_EL0
@ MISCREG_PMEVTYPER5_EL0
Definition: misc.hh:801
system.hh
gem5::ArmISA::ISA::getCurSveVecLenInBits
unsigned getCurSveVecLenInBits() const
Definition: isa.cc:2358
gem5::ArmSystem::highestELIs64
bool highestELIs64() const
Returns true if the register width of the highest implemented exception level is 64 bits (ARMv8)
Definition: system.hh:205
gem5::ArmISA::MISCREG_DBGWCR3_EL1
@ MISCREG_DBGWCR3_EL1
Definition: misc.hh:509
gem5::ArmISA::SelfDebug
Definition: self_debug.hh:277
gem5::ArmISA::MISCREG_CURRENTEL
@ MISCREG_CURRENTEL
Definition: misc.hh:618
gem5::ArmISA::MISCREG_TTBR0
@ MISCREG_TTBR0
Definition: misc.hh:254
gem5::ArmISA::TLBIASID
TLB Invalidate by ASID match.
Definition: tlbi_op.hh:216
gem5::ArmISA::ISA::gicv3CpuInterface
std::unique_ptr< BaseISADevice > gicv3CpuInterface
Definition: isa.hh:87
gem5::ArmISA::TLBIALL
TLB Invalidate All.
Definition: tlbi_op.hh:106
gem5::ArmISA::MISCREG_TLBI_ALLE1
@ MISCREG_TLBI_ALLE1
Definition: misc.hh:701
gem5::igbreg::txd_op::ic
bool ic(TxDesc *d)
Definition: i8254xGBe_defs.hh:266
gem5::Gicv3::getCPUInterface
Gicv3CPUInterface * getCPUInterface(int cpu_id) const
Definition: gic_v3.hh:138
gem5::ArmISA::MISCREG_AT_S12E0W_Xt
@ MISCREG_AT_S12E0W_Xt
Definition: misc.hh:675
gem5::ArmISA::MISCREG_DBGWCR15
@ MISCREG_DBGWCR15
Definition: misc.hh:169
gem5::ArmISA::ISA::readMiscRegNoEffect
RegVal readMiscRegNoEffect(int misc_reg) const
Definition: isa.cc:535
gem5::ArmISA::NumVecRegs
const int NumVecRegs
Definition: vec.hh:80
gem5::ArmISA::MISCREG_DBGWCR10
@ MISCREG_DBGWCR10
Definition: misc.hh:164
gem5::ArmISA::ISA::clear
void clear()
Definition: isa.cc:133
gem5::ArmISA::MISCREG_MPIDR
@ MISCREG_MPIDR
Definition: misc.hh:209
gem5::ArmISA::el
Bitfield< 3, 2 > el
Definition: misc_types.hh:72
gem5::ArmISA::MISCREG_CNTFRQ
@ MISCREG_CNTFRQ
Definition: misc.hh:413
gem5::ArmISA::MISCREG_DBGBCR3_EL1
@ MISCREG_DBGBCR3_EL1
Definition: misc.hh:477
gem5::ArmISA::MISCREG_CONTEXTIDR
@ MISCREG_CONTEXTIDR
Definition: misc.hh:399
gem5::ArmISA::MISCREG_ATS1CUW
@ MISCREG_ATS1CUW
Definition: misc.hh:307
gem5::ArmISA::MISCREG_TCR_EL2
@ MISCREG_TCR_EL2
Definition: misc.hh:604
gem5::ArmISA::MISCREG_DBGBCR15_EL1
@ MISCREG_DBGBCR15_EL1
Definition: misc.hh:489
gem5::BaseCPU::getInterruptController
BaseInterrupts * getInterruptController(ThreadID tid)
Definition: base.hh:229
gem5::ArmISA::MISCREG_ITLBIMVA
@ MISCREG_ITLBIMVA
Definition: misc.hh:328
gem5::ArmISA::MISCREG_SDCR
@ MISCREG_SDCR
Definition: misc.hh:242
gem5::ArmISA::MISCREG_FPSID
@ MISCREG_FPSID
Definition: misc.hh:71
gem5::ArmISA::MMU::getAttr
uint64_t getAttr() const
Definition: mmu.hh:163
gem5::ArmISA::MISCREG_TLBI_IPAS2E1IS_Xt
@ MISCREG_TLBI_IPAS2E1IS_Xt
Definition: misc.hh:690
gem5::ArmISA::MISCREG_VPIDR
@ MISCREG_VPIDR
Definition: misc.hh:233
gem5::ArmISA::MISCREG_SCTLR_NS
@ MISCREG_SCTLR_NS
Definition: misc.hh:236
gem5::ArmSystem::haveLPAE
bool haveLPAE() const
Returns true if this system implements the Large Physical Address Extension.
Definition: system.hh:166
gem5::ArmISA::MISCREG_DBGWCR8
@ MISCREG_DBGWCR8
Definition: misc.hh:162
warn_once
#define warn_once(...)
Definition: logging.hh:249
gem5::ArmISA::MISCREG_DBGBCR5
@ MISCREG_DBGBCR5
Definition: misc.hh:127
gem5::ArmISA::MISCREG_MDCR_EL2
@ MISCREG_MDCR_EL2
Definition: misc.hh:587
gem5::ArmISA::MISCREG_DBGBCR1_EL1
@ MISCREG_DBGBCR1_EL1
Definition: misc.hh:475
gem5::ArmISA::MISCREG_TLBI_VAAE1_Xt
@ MISCREG_TLBI_VAAE1_Xt
Definition: misc.hh:687
gem5::ArmISA::MISCREG_DBGWCR9
@ MISCREG_DBGWCR9
Definition: misc.hh:163
gem5::ArmISA::MISCREG_TLBIMVAAL
@ MISCREG_TLBIMVAAL
Definition: misc.hh:338
gem5::ArmISA::ISA::haveLargeAsid64
bool haveLargeAsid64
Definition: isa.hh:95
gem5::ArmISA::MISCREG_MVFR1
@ MISCREG_MVFR1
Definition: misc.hh:73
gem5::ArmISA::ISA::MiscRegLUTEntryInitializer::priv
chain priv(bool v=true) const
Definition: isa.hh:250
gem5::ArmISA::MISCREG_ATS12NSOUR
@ MISCREG_ATS12NSOUR
Definition: misc.hh:310
gem5::ArmISA::ISA::takeOverFrom
void takeOverFrom(ThreadContext *new_tc, ThreadContext *old_tc) override
Definition: isa.cc:485
gem5::ArmISA::ISA::initID32
void initID32(const ArmISAParams &p)
Definition: isa.cc:326
gem5::ArmISA::MISCREG_TLBIMVALHIS
@ MISCREG_TLBIMVALHIS
Definition: misc.hh:344
gem5::ArmISA::MISCREG_TLBIALLH
@ MISCREG_TLBIALLH
Definition: misc.hh:347
gem5::BaseMMU::Mode
Mode
Definition: mmu.hh:53
gem5::ArmISA::attr
attr
Definition: misc_types.hh:655
gem5::ArmISA::MISCREG_NZCV
@ MISCREG_NZCV
Definition: misc.hh:619
gem5::ArmISA::MODE_EL1H
@ MODE_EL1H
Definition: types.hh:276
gem5::ArmISA::asid
asid
Definition: misc_types.hh:617
gem5::ArmISA::ISA::updateRegMap
void updateRegMap(CPSR cpsr)
Definition: isa.hh:464
gem5::BaseMMU::Write
@ Write
Definition: mmu.hh:53
gem5::ArmISA::MISCREG_SCR_EL3
@ MISCREG_SCR_EL3
Definition: misc.hh:593
gem5::ThreadContext::getMMUPtr
virtual BaseMMU * getMMUPtr()=0
gem5::CheckpointIn
Definition: serialize.hh:68
gem5::ArmISA::CCREG_NZ
@ CCREG_NZ
Definition: cc.hh:49
gem5::ArmISA::MISCREG_DBGWCR12_EL1
@ MISCREG_DBGWCR12_EL1
Definition: misc.hh:518
gem5::ArmISA::ISA::timer
std::unique_ptr< BaseISADevice > timer
Definition: isa.hh:84
gem5::ArmISA::MISCREG_DBGBCR0
@ MISCREG_DBGBCR0
Definition: misc.hh:122
gem5::ArmISA::MMU::D_TLBS
@ D_TLBS
Definition: mmu.hh:85
gem5::ArmISA::encodePhysAddrRange64
uint8_t encodePhysAddrRange64(int pa_size)
Returns the encoding corresponding to the specified n.
Definition: utility.cc:1311
gem5::ArmISA::MISCREG_TLBIIPAS2
@ MISCREG_TLBIIPAS2
Definition: misc.hh:345
gem5::ArmISA::MISCREG_TLBI_IPAS2LE1IS_Xt
@ MISCREG_TLBI_IPAS2LE1IS_Xt
Definition: misc.hh:691
gem5::ArmISA::MISCREG_DAIF
@ MISCREG_DAIF
Definition: misc.hh:620
gem5::ArmISA::MISCREG_TTBR1_EL1
@ MISCREG_TTBR1_EL1
Definition: misc.hh:599
gem5::ArmISA::MISCREG_TTBCR
@ MISCREG_TTBCR
Definition: misc.hh:260
gem5::ArmISA::MISCREG_TLBI_VMALLS12E1IS
@ MISCREG_TLBI_VMALLS12E1IS
Definition: misc.hh:696
gem5::ArmISA::MISCREG_TLBI_VALE2_Xt
@ MISCREG_TLBI_VALE2_Xt
Definition: misc.hh:702
gem5::ArmISA::MISCREG_TLBIMVAL
@ MISCREG_TLBIMVAL
Definition: misc.hh:337
gem5::ArmSystem::haveVHE
bool haveVHE() const
Returns true if Virtualization Host Extensions is implemented.
Definition: system.hh:241
gem5::ArmISA::MISCREG_JOSCR
@ MISCREG_JOSCR
Definition: misc.hh:201
gem5::ArmISA::MISCREG_HSCTLR
@ MISCREG_HSCTLR
Definition: misc.hh:246
gem5::ArmISA::SelfDebug::updateOSLock
void updateOSLock(RegVal val)
Definition: self_debug.hh:403
gem5::ArmSystem::haveLargeAsid64
bool haveLargeAsid64() const
Returns true if ASID is 16 bits in AArch64 (ARMv8)
Definition: system.hh:224
gem5::ArmISA::MISCREG_AT_S1E0W_Xt
@ MISCREG_AT_S1E0W_Xt
Definition: misc.hh:662
gem5::ArmISA::MISCREG_DBGWCR9_EL1
@ MISCREG_DBGWCR9_EL1
Definition: misc.hh:515
gem5::ArmISA::MISCREG_TLBI_VALE2IS_Xt
@ MISCREG_TLBI_VALE2IS_Xt
Definition: misc.hh:695
gem5::X86ISA::val
Bitfield< 63 > val
Definition: misc.hh:775
gem5::ArmISA::MISCREG_DBGWCR10_EL1
@ MISCREG_DBGWCR10_EL1
Definition: misc.hh:516
gem5::ArmISA::MISCREG_TLBIALLIS
@ MISCREG_TLBIALLIS
Definition: misc.hh:321
gem5::ArmISA::MISCREG_OSLSR_EL1
@ MISCREG_OSLSR_EL1
Definition: misc.hh:529
gem5::ArmISA::MISCREG_DBGBCR8_EL1
@ MISCREG_DBGBCR8_EL1
Definition: misc.hh:482
gem5::ArmISA::MISCREG_TLBIALLHIS
@ MISCREG_TLBIALLHIS
Definition: misc.hh:341
gem5::ArmISA::MISCREG_PMINTENSET_EL1
@ MISCREG_PMINTENSET_EL1
Definition: misc.hh:710
gem5::ArmISA::MISCREG_TLBI_VALE1IS_Xt
@ MISCREG_TLBI_VALE1IS_Xt
Definition: misc.hh:682
gem5::ArmISA::MISCREG_TLBTR
@ MISCREG_TLBTR
Definition: misc.hh:208
gem5::ArmISA::daif
Bitfield< 9, 6 > daif
Definition: misc_types.hh:69
gem5::ArmISA::MISCREG_ID_AA64AFR1_EL1
@ MISCREG_ID_AA64AFR1_EL1
Definition: misc.hh:566
gem5::ArmISA::MISCREG_ITLBIASID
@ MISCREG_ITLBIASID
Definition: misc.hh:329
gem5::ArmISA::miscRegName
const char *const miscRegName[]
Definition: misc.hh:1172
gem5::ArmISA::MISCREG_TCR_EL3
@ MISCREG_TCR_EL3
Definition: misc.hh:610
gem5::ArmISA::ISA::haveTME
bool haveTME
Definition: isa.hh:102
gem5::ArmISA::MISCREG_HIFAR
@ MISCREG_HIFAR
Definition: misc.hh:290
gem5::ArmSystem::haveCrypto
bool haveCrypto() const
Returns true if this system implements the Crypto Extension.
Definition: system.hh:176
gem5::ThreadContext::contextId
virtual ContextID contextId() const =0
gem5::ArmISA::EL1
@ EL1
Definition: types.hh:267
gem5::ArmISA::MISCREG_DBGWCR4
@ MISCREG_DBGWCR4
Definition: misc.hh:158
gem5::ArmISA::ISA::copyRegsFrom
void copyRegsFrom(ThreadContext *src) override
Definition: isa.cc:510
gem5::ArmISA::MISCREG_ID_ISAR3
@ MISCREG_ID_ISAR3
Definition: misc.hh:223
gem5::ArmISA::MISCREG_DBGBCR13_EL1
@ MISCREG_DBGBCR13_EL1
Definition: misc.hh:487
gem5::ArmISA::MISCREG_ID_AA64MMFR0_EL1
@ MISCREG_ID_AA64MMFR0_EL1
Definition: misc.hh:569
gem5::ArmISA::MISCREG_TLBIMVALH
@ MISCREG_TLBIMVALH
Definition: misc.hh:350
gem5::X86ISA::system
Bitfield< 15 > system
Definition: misc.hh:1003
gem5::ArmISA::MISCREG_DBGBCR12_EL1
@ MISCREG_DBGBCR12_EL1
Definition: misc.hh:486
gem5::ArmISA::MISCREG_ID_MMFR3
@ MISCREG_ID_MMFR3
Definition: misc.hh:218
gem5::ArmISA::MISCREG_DBGWCR13
@ MISCREG_DBGWCR13
Definition: misc.hh:167
std::vector
STL vector class.
Definition: stl.hh:37
gem5::ArmISA::ELIsInHost
bool ELIsInHost(ThreadContext *tc, ExceptionLevel el)
Returns true if the current exception level el is executing a Host OS or an application of a Host OS ...
Definition: utility.cc:297
gem5::ArmISA::MISCREG_DBGOSLAR
@ MISCREG_DBGOSLAR
Definition: misc.hh:187
gem5::ArmISA::CpsrMaskQ
static const uint32_t CpsrMaskQ
Definition: misc.hh:2192
gem5::ArmISA::MISCREG_PMOVSSET
@ MISCREG_PMOVSSET
Definition: misc.hh:366
gem5::ArmISA::ISA::serialize
void serialize(CheckpointOut &cp) const override
Serialize an object.
Definition: isa.cc:2402
gem5::ThreadContext::readIntRegFlat
virtual RegVal readIntRegFlat(RegIndex idx) const =0
Flat register interfaces.
gem5::ArmISA::MISCREG_PRRR_NS
@ MISCREG_PRRR_NS
Definition: misc.hh:370
gem5::ArmISA::MISCREG_TLBI_VALE1_Xt
@ MISCREG_TLBI_VALE1_Xt
Definition: misc.hh:688
gem5::ArmISA::ISA::haveSecEL2
bool haveSecEL2
Definition: isa.hh:101
gem5::ArmISA::MISCREG_ID_ISAR1
@ MISCREG_ID_ISAR1
Definition: misc.hh:221
gem5::ArmISA::MISCREG_ATS12NSOPW
@ MISCREG_ATS12NSOPW
Definition: misc.hh:309
gem5::ArmISA::TLB::S1CTran
@ S1CTran
Definition: tlb.hh:131
SERIALIZE_MAPPING
#define SERIALIZE_MAPPING(member, names, size)
Definition: serialize.hh:660
gem5::ArmISA::TLB::HypMode
@ HypMode
Definition: tlb.hh:132
gem5::mbits
constexpr T mbits(T val, unsigned first, unsigned last)
Mask off the given bits in place like bits() but without shifting.
Definition: bitfield.hh:103
gem5::ArmISA::FpscrQcMask
static const uint32_t FpscrQcMask
Definition: misc.hh:2209
gem5::ArmISA::MISCREG_ICH_LR15_EL2
@ MISCREG_ICH_LR15_EL2
Definition: misc.hh:914
gem5::ArmISA::ISA::sveVL
unsigned sveVL
SVE vector length in quadwords.
Definition: isa.hh:105
gem5::ArmISA::ISA::havePAN
bool havePAN
Definition: isa.hh:100
gem5::ArmISA::MISCREG_TLBI_VAE1IS_Xt
@ MISCREG_TLBI_VAE1IS_Xt
Definition: misc.hh:679
gem5::ArmISA::ISA::MiscRegLUTEntryInitializer::chain
const typedef MiscRegLUTEntryInitializer & chain
Definition: isa.hh:147
system.hh
gem5::ArmISA::MISCREG_IMPLEMENTED
@ MISCREG_IMPLEMENTED
Definition: misc.hh:1101
gem5::ArmISA::ISA::haveLSE
bool haveLSE
Definition: isa.hh:98
gem5::ArmISA::MISCREG_ID_AA64DFR1_EL1
@ MISCREG_ID_AA64DFR1_EL1
Definition: misc.hh:564
gem5::ArmISA::MISCREG_SCTLR
@ MISCREG_SCTLR
Definition: misc.hh:235
gem5::ArmISA::i
Bitfield< 7 > i
Definition: misc_types.hh:66
gem5::ArmISA::MISCREG_PAR_EL1
@ MISCREG_PAR_EL1
Definition: misc.hh:655
gem5::ArmISA::DTLBIASID
Data TLB Invalidate by ASID match.
Definition: tlbi_op.hh:245
gem5::ArmISA::MISCREG_TLBI_VALE3IS_Xt
@ MISCREG_TLBI_VALE3IS_Xt
Definition: misc.hh:706
faults.hh
gem5::ArmISA::MISCREG_ICC_AP0R0
@ MISCREG_ICC_AP0R0
Definition: misc.hh:959
gem5::ArmISA::MODE_EL3H
@ MODE_EL3H
Definition: types.hh:280
gem5::ArmISA::ITLBIASID
Instruction TLB Invalidate by ASID match.
Definition: tlbi_op.hh:232
gem5::ArmISA::FpscrExcMask
static const uint32_t FpscrExcMask
Definition: misc.hh:2213
gem5::ArmISA::MISCREG_DBGWCR5_EL1
@ MISCREG_DBGWCR5_EL1
Definition: misc.hh:511
gem5::ArmISA::MISCREG_DBGWCR7
@ MISCREG_DBGWCR7
Definition: misc.hh:161
gem5::ArmISA::MISCREG_TLBI_VMALLS12E1
@ MISCREG_TLBI_VMALLS12E1
Definition: misc.hh:703
gem5::PowerISA::PCState
Definition: pcstate.hh:42
gem5::ArmISA::MISCREG_JIDR
@ MISCREG_JIDR
Definition: misc.hh:199
gem5::ArmISA::SelfDebug::updateDBGBCR
void updateDBGBCR(int index, DBGBCR val)
Definition: self_debug.hh:409
gem5::ArmISA::MISCREG_ID_MMFR1
@ MISCREG_ID_MMFR1
Definition: misc.hh:216
gem5::ArmSystem::getGIC
BaseGic * getGIC() const
Get a pointer to the system's GIC.
Definition: system.hh:198
gem5::ArmISA::MISCREG_DBGBCR15
@ MISCREG_DBGBCR15
Definition: misc.hh:137
gem5::ArmISA::ITLBIMVA
Instruction TLB Invalidate by VA.
Definition: tlbi_op.hh:313
gem5::ThreadContext::getDecoderPtr
virtual TheISA::Decoder * getDecoderPtr()=0
gem5::ThreadContext::readCCReg
virtual RegVal readCCReg(RegIndex reg_idx) const =0
gem5::ArmISA::ISA::addressTranslation
void addressTranslation(TLB::ArmTranslationType tran_type, BaseMMU::Mode mode, Request::Flags flags, RegVal val)
Definition: isa.cc:2469
gem5::ArmISA::getMMUPtr
MMU * getMMUPtr(T *tc)
Definition: mmu.hh:171
gem5::ArmISA::MISCREG_ID_DFR0_EL1
@ MISCREG_ID_DFR0_EL1
Definition: misc.hh:544
gem5::ArmISA::MISCREG_JMCR
@ MISCREG_JMCR
Definition: misc.hh:202
gem5::ArmISA::MISCREG_VTCR_EL2
@ MISCREG_VTCR_EL2
Definition: misc.hh:606
gem5::ArmISA::MISCREG_DBGBCR6
@ MISCREG_DBGBCR6
Definition: misc.hh:128
gem5::ArmISA::MISCREG_TLBI_VAE2_Xt
@ MISCREG_TLBI_VAE2_Xt
Definition: misc.hh:700
gem5::ArmISA::miscRegInfo
std::bitset< NUM_MISCREG_INFOS > miscRegInfo[NUM_MISCREGS]
Definition: misc.cc:3397
gem5::ArmISA::TLB::S1E3Tran
@ S1E3Tran
Definition: tlb.hh:143
gem5::System::cacheLineSize
unsigned int cacheLineSize() const
Get the cache line size of the system.
Definition: system.hh:314
gem5::ArmISA::MISCREG_DBGWCR6_EL1
@ MISCREG_DBGWCR6_EL1
Definition: misc.hh:512
gem5::ArmISA::MISCREG_DACR
@ MISCREG_DACR
Definition: misc.hh:265
gem5::ArmISA::MISCREG_HCPTR
@ MISCREG_HCPTR
Definition: misc.hh:251
gem5::ArmISA::MISCREG_DBGWCR3
@ MISCREG_DBGWCR3
Definition: misc.hh:157
gem5::ArmISA::MISCREG_ID_ISAR0
@ MISCREG_ID_ISAR0
Definition: misc.hh:220
gem5::ArmISA::ISA::setMiscRegNoEffect
void setMiscRegNoEffect(int misc_reg, RegVal val)
Definition: isa.cc:861
gem5::ArmISA::ISA::initID64
void initID64(const ArmISAParams &p)
Definition: isa.cc:364
gem5::ArmISA::MISCREG_DBGDSCRext
@ MISCREG_DBGDSCRext
Definition: misc.hh:103
gem5::ArmISA::MISCREG_ID_MMFR2
@ MISCREG_ID_MMFR2
Definition: misc.hh:217
gem5::ArmISA::MISCREG_IFSR
@ MISCREG_IFSR
Definition: misc.hh:271
gem5::ArmISA::SelfDebug::setbSDD
void setbSDD(RegVal val)
Definition: self_debug.hh:377
gem5::ArmISA::TLBIALLN
TLB Invalidate All, Non-Secure.
Definition: tlbi_op.hh:258
gem5::ArmISA::MISCREG_DTLBIASID
@ MISCREG_DTLBIASID
Definition: misc.hh:332
gem5::SimObject::Params
SimObjectParams Params
Definition: sim_object.hh:170
mmu.hh
gem5::ArmISA::MISCREG_SCTLR_S
@ MISCREG_SCTLR_S
Definition: misc.hh:237
gem5::ArmISA::ArmFault::iss
virtual uint32_t iss() const =0
gem5::ArmISA::MISCREG_DBGWCR15_EL1
@ MISCREG_DBGWCR15_EL1
Definition: misc.hh:521
gem5::ArmISA::MISCREG_HCR2
@ MISCREG_HCR2
Definition: misc.hh:249
htm.hh
gem5::ArmISA::Interrupts
Definition: interrupts.hh:70
gem5::Flags< FlagsType >
gem5::ArmISA::MISCREG_CNTVOFF
@ MISCREG_CNTVOFF
Definition: misc.hh:433
gem5::ArmISA::SelfDebug::setMDBGen
void setMDBGen(RegVal val)
Definition: self_debug.hh:391
gem5::ArmISA::ISA::pmu
BaseISADevice * pmu
Definition: isa.hh:81
gem5::ArmISA::MISCREG_DTLBIMVA
@ MISCREG_DTLBIMVA
Definition: misc.hh:331
gem5::ArmISA::MISCREG_TLBIIPAS2IS
@ MISCREG_TLBIIPAS2IS
Definition: misc.hh:339
gem5::ArmISA::MISCREG_DBGBCR1
@ MISCREG_DBGBCR1
Definition: misc.hh:123
gem5::ArmISA::MISCREG_PRRR
@ MISCREG_PRRR
Definition: misc.hh:369
gem5::BaseISA::_regClasses
RegClasses _regClasses
Definition: isa.hh:64
gem5::ArmISA::NumVecPredRegs
const int NumVecPredRegs
Definition: vec.hh:81
gem5::ThreadContext::setHtmCheckpointPtr
virtual void setHtmCheckpointPtr(BaseHTMCheckpointPtr cpt)=0
gem5::ArmSystem::highestEL
ArmISA::ExceptionLevel highestEL() const
Returns the highest implemented exception level.
Definition: system.hh:209
gem5::ArmISA::MISCREG_DBGWCR0
@ MISCREG_DBGWCR0
Definition: misc.hh:154
gem5::ArmISA::MISCREG_RVBAR_EL1
@ MISCREG_RVBAR_EL1
Definition: misc.hh:738
gem5::ArmISA::MISCREG_DBGBCR8
@ MISCREG_DBGBCR8
Definition: misc.hh:130
interrupts.hh
gem5::ArmISA::MISCREG_DBGBCR10
@ MISCREG_DBGBCR10
Definition: misc.hh:132
gem5::ThreadContext::getIsaPtr
virtual BaseISA * getIsaPtr()=0
gem5::ArmISA::MISCREG_DBGWCR14
@ MISCREG_DBGWCR14
Definition: misc.hh:168
gem5::ArmISA::MISCREG_ATS1CUR
@ MISCREG_ATS1CUR
Definition: misc.hh:306
gem5::ArmISA::MISCREG_ID_AA64PFR1_EL1
@ MISCREG_ID_AA64PFR1_EL1
Definition: misc.hh:562
gem5::ArmISA::SelfDebug::setMDSCRvals
void setMDSCRvals(RegVal val)
Definition: self_debug.hh:383
gem5::ThreadContext
ThreadContext is the external interface to all thread state for anything outside of the CPU.
Definition: thread_context.hh:93
gem5::ArmISA::MISCREG_DBGWCR2_EL1
@ MISCREG_DBGWCR2_EL1
Definition: misc.hh:508
gem5::ArmISA::MODE_HYP
@ MODE_HYP
Definition: types.hh:287
gem5::ArmISA::MISCREG_DBGBCR3
@ MISCREG_DBGBCR3
Definition: misc.hh:125
gem5::ArmISA::MISCREG_SCTLR_EL1
@ MISCREG_SCTLR_EL1
Definition: misc.hh:579
gem5::ArmISA::MISCREG_ID_AA64MMFR2_EL1
@ MISCREG_ID_AA64MMFR2_EL1
Definition: misc.hh:822
gem5::ArmISA::ISA::clear64
void clear64(const ArmISAParams &p)
Definition: isa.cc:277
gem5::ArmISA::MISCREG_ID_ISAR2
@ MISCREG_ID_ISAR2
Definition: misc.hh:222
gem5::Fault
std::shared_ptr< FaultBase > Fault
Definition: types.hh:255
gem5::ArmISA::MISCREG_ICH_LRC15
@ MISCREG_ICH_LRC15
Definition: misc.hh:1051
gem5::ArmISA::MISCREG_HDCR
@ MISCREG_HDCR
Definition: misc.hh:250
gem5::ArmISA::MISCREG_CPTR_EL3
@ MISCREG_CPTR_EL3
Definition: misc.hh:595
gem5::ArmISA::MISCREG_ID_ISAR4
@ MISCREG_ID_ISAR4
Definition: misc.hh:224
gem5::SimObject::params
const Params & params() const
Definition: sim_object.hh:176
gem5::ArmISA::MISCREG_DBGBCR14
@ MISCREG_DBGBCR14
Definition: misc.hh:136
DPRINTF
#define DPRINTF(x,...)
Definition: trace.hh:186
gem5::ArmISA::MISCREG_MVBAR
@ MISCREG_MVBAR
Definition: misc.hh:394
gem5::ArmISA::MISCREG_PMOVSSET_EL0
@ MISCREG_PMOVSSET_EL0
Definition: misc.hh:725
gem5::ArmISA::MISCREG_DBGWCR5
@ MISCREG_DBGWCR5
Definition: misc.hh:159
gem5::ArmISA::MISCREG_MAIR1
@ MISCREG_MAIR1
Definition: misc.hh:378
gem5::ArmISA::EL2
@ EL2
Definition: types.hh:268
gem5::ArmISA::copyVecRegs
static void copyVecRegs(ThreadContext *src, ThreadContext *dest)
Definition: isa.cc:492
gem5::ArmISA::MISCREG_FPEXC
@ MISCREG_FPEXC
Definition: misc.hh:75
gem5::ArmISA::MISCREG_MIDR_EL1
@ MISCREG_MIDR_EL1
Definition: misc.hh:539
gem5::ArmISA::TLBIMVAA
TLB Invalidate by VA, All ASID.
Definition: tlbi_op.hh:281
gem5::ArmISA::MISCREG_AT_S1E1W_Xt
@ MISCREG_AT_S1E1W_Xt
Definition: misc.hh:660
gem5::ArmISA::MISCREG_SCTLR_EL2
@ MISCREG_SCTLR_EL2
Definition: misc.hh:584
gem5::MipsISA::p
Bitfield< 0 > p
Definition: pra_constants.hh:326
gem5::ArmISA::MISCREG_ID_AA64AFR0_EL1
@ MISCREG_ID_AA64AFR0_EL1
Definition: misc.hh:565
gem5::ArmISA::ISA::getMiscIndices
std::pair< int, int > getMiscIndices(int misc_reg) const
Definition: isa.hh:833
gem5::ArmISA::NUM_MISCREGS
@ NUM_MISCREGS
Definition: misc.hh:1096
isa.hh
gem5::ArmISA::ISA::unserialize
void unserialize(CheckpointIn &cp) override
Unserialize an object.
Definition: isa.cc:2409
gem5::ArmISA::ELIs32
bool ELIs32(ThreadContext *tc, ExceptionLevel el)
Definition: utility.cc:288
gem5::CheckerCPU
CheckerCPU class.
Definition: cpu.hh:84
gem5::ArmISA::ArmFault::update
void update(ThreadContext *tc)
Definition: faults.cc:439
gem5::ArmISA::MISCREG_CCSIDR
@ MISCREG_CCSIDR
Definition: misc.hh:227
gem5::ThreadContext::setIntRegFlat
virtual void setIntRegFlat(RegIndex idx, RegVal val)=0
gem5::ArmISA::MISCREG_DBGWCR4_EL1
@ MISCREG_DBGWCR4_EL1
Definition: misc.hh:510
gem5::ArmISA::v
Bitfield< 28 > v
Definition: misc_types.hh:54
gem5::ArmISA::ISA::ISA
ISA(const Params &p)
Definition: isa.cc:67
gem5::ArmISA::MISCREG_MVFR0
@ MISCREG_MVFR0
Definition: misc.hh:74
cpu.hh
gem5::ArmISA::ISA::MiscRegLUTEntryInitializer::mon
chain mon(bool v=true) const
Definition: isa.hh:364
gem5::ThreadContext::readVecElemFlat
virtual const TheISA::VecElem & readVecElemFlat(RegIndex idx, const ElemIndex &elem_idx) const =0
gem5::ArmISA::MISCREG_VMPIDR
@ MISCREG_VMPIDR
Definition: misc.hh:234
gem5::ArmISA::MISCREG_PMXEVTYPER_PMCCFILTR
@ MISCREG_PMXEVTYPER_PMCCFILTR
Definition: misc.hh:90
gem5::ArmISA::MISCREG_TLBIALLNSNHIS
@ MISCREG_TLBIALLNSNHIS
Definition: misc.hh:343
gem5::ArmISA::TLB::S1S2NsTran
@ S1S2NsTran
Definition: tlb.hh:135
gem5::ArmISA::ISA::haveLPAE
bool haveLPAE
Definition: isa.hh:92
gem5::ArmISA::MISCREG_DBGWCR1_EL1
@ MISCREG_DBGWCR1_EL1
Definition: misc.hh:507
gem5::GenericTimer
Definition: generic_timer.hh:288
gem5::ArmISA::TLB::UserMode
@ UserMode
Definition: tlb.hh:125
gem5::ArmISA::MISCREG_ICC_IGRPEN1_EL3
@ MISCREG_ICC_IGRPEN1_EL3
Definition: misc.hh:882
gem5::ArmISA::MISCREG_CPACR_EL1
@ MISCREG_CPACR_EL1
Definition: misc.hh:582
gem5::ArmISA::MISCREG_ATS1HR
@ MISCREG_ATS1HR
Definition: misc.hh:319
gem5::ArmISA::MISCREG_DBGBCR11
@ MISCREG_DBGBCR11
Definition: misc.hh:133
gem5::ArmISA::MISCREG_SPSEL
@ MISCREG_SPSEL
Definition: misc.hh:617
tlbi_op.hh
gem5::ArmISA::pan
Bitfield< 22 > pan
Definition: misc_types.hh:58
gem5::ArmISA::MISCREG_MPIDR_EL1
@ MISCREG_MPIDR_EL1
Definition: misc.hh:540
gem5::ArmISA::MISCREG_ACTLR
@ MISCREG_ACTLR
Definition: misc.hh:238
gem5::ArmISA::MISCREG_TLBI_ASIDE1IS_Xt
@ MISCREG_TLBI_ASIDE1IS_Xt
Definition: misc.hh:680
gem5::ArmISA::MISCREG_SPSR_EL2
@ MISCREG_SPSR_EL2
Definition: misc.hh:625
gem5::ArmISA::TLB::S1E2Tran
@ S1E2Tran
Definition: tlb.hh:142
gem5::ArmISA::ISA::assert32
void assert32()
Definition: isa.hh:505
gem5::ArmISA::MISCREG_DC_ZVA_Xt
@ MISCREG_DC_ZVA_Xt
Definition: misc.hh:665
gem5::ArmISA::MISCREG_SP_EL1
@ MISCREG_SP_EL1
Definition: misc.hh:627
gem5::ArmISA::MISCREG_AT_S1E0R_Xt
@ MISCREG_AT_S1E0R_Xt
Definition: misc.hh:661
gem5::ArmISA::mask
Bitfield< 3, 0 > mask
Definition: pcstate.hh:63
gem5::ArmISA::MISCREG_ISR
@ MISCREG_ISR
Definition: misc.hh:396
gem5::ArmISA::MISCREG_RVBAR_EL2
@ MISCREG_RVBAR_EL2
Definition: misc.hh:741
gem5::ArmISA::MISCREG_ID_AFR0
@ MISCREG_ID_AFR0
Definition: misc.hh:214
gem5::ArmISA::MMU::translateFunctional
bool translateFunctional(ThreadContext *tc, Addr vaddr, Addr &paddr)
Definition: mmu.cc:96
gem5::ArmISA::MISCREG_MIDR
@ MISCREG_MIDR
Definition: misc.hh:205
gem5::insertBits
constexpr T insertBits(T val, unsigned first, unsigned last, B bit_val)
Returns val with bits first to last set to the LSBs of bit_val.
Definition: bitfield.hh:166
gem5::bits
constexpr T bits(T val, unsigned first, unsigned last)
Extract the bitfield from position 'first' to 'last' (inclusive) from 'val' and right justify it.
Definition: bitfield.hh:76
gem5::ArmISA::MISCREG_DBGBCR4_EL1
@ MISCREG_DBGBCR4_EL1
Definition: misc.hh:478
gem5::ArmISA::EL3
@ EL3
Definition: types.hh:269
gem5::ArmSystem::havePAN
bool havePAN() const
Returns true if Priviledge Access Never is implemented.
Definition: system.hh:244
gem5::ArmISA::ISA::getGICv3CPUInterface
BaseISADevice & getGICv3CPUInterface()
Definition: isa.cc:2351
gem5::ArmISA::ISA::readMiscReg
RegVal readMiscReg(int misc_reg)
Definition: isa.cc:559
gem5::ArmISA::MISCREG_PAR
@ MISCREG_PAR
Definition: misc.hh:294
gem5::ThreadContext::pcState
virtual TheISA::PCState pcState() const =0
gem5::ThreadContext::readMiscRegNoEffect
virtual RegVal readMiscRegNoEffect(RegIndex misc_reg) const =0
gem5::ArmISA::MODE_USER
@ MODE_USER
Definition: types.hh:281
gem5::ArmISA::ISA::startup
void startup() override
startup() is the final initialization call before simulation.
Definition: isa.cc:447
gem5::ArmISA::ISA::haveSVE
bool haveSVE
Definition: isa.hh:97
gem5::ArmISA::MISCREG_ID_PFR1
@ MISCREG_ID_PFR1
Definition: misc.hh:212
gem5::ArmISA::MISCREG_ID_AA64DFR0_EL1
@ MISCREG_ID_AA64DFR0_EL1
Definition: misc.hh:563
faults.hh
generic_timer.hh
gem5::ArmISA::ISA::getGenericTimer
BaseISADevice & getGenericTimer()
Definition: isa.cc:2330
gem5::ArmISA::MISCREG_HDFAR
@ MISCREG_HDFAR
Definition: misc.hh:289
gem5::ArmISA::MISCREG_ID_AA64MMFR1_EL1
@ MISCREG_ID_AA64MMFR1_EL1
Definition: misc.hh:570
gem5::ArmISA::MISCREG_SPSR_EL1
@ MISCREG_SPSR_EL1
Definition: misc.hh:612
gem5::ArmISA::MISCREG_RVBAR_EL3
@ MISCREG_RVBAR_EL3
Definition: misc.hh:743
gem5::ArmISA::MISCREG_VBAR_S
@ MISCREG_VBAR_S
Definition: misc.hh:393
gem5::ArmISA::MISCREG_TCMTR
@ MISCREG_TCMTR
Definition: misc.hh:207
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::ArmISA::MISCREG_DBGBCR12
@ MISCREG_DBGBCR12
Definition: misc.hh:134
gem5::ArmISA::MISCREG_TLBIMVA
@ MISCREG_TLBIMVA
Definition: misc.hh:334
gem5::ArmSystem::haveSVE
bool haveSVE() const
Returns true if SVE is implemented (ARMv8)
Definition: system.hh:232
gem5::ThreadContext::readIntReg
virtual RegVal readIntReg(RegIndex reg_idx) const =0
gem5::ArmISA::MISCREG_NMRR_NS
@ MISCREG_NMRR_NS
Definition: misc.hh:376
gem5::ArmISA::MISCREG_DFSR
@ MISCREG_DFSR
Definition: misc.hh:268
gem5::ArmISA::MISCREG_NMRR
@ MISCREG_NMRR
Definition: misc.hh:375
gem5::BaseISA::vecRegRenameMode
virtual enums::VecRegRenameMode vecRegRenameMode(ThreadContext *_tc) const
Definition: isa.hh:81
gem5::ArmISA::MISCREG_DBGBCR0_EL1
@ MISCREG_DBGBCR0_EL1
Definition: misc.hh:474
gem5::ThreadContext::setVecElemFlat
virtual void setVecElemFlat(RegIndex idx, const ElemIndex &elem_idx, const TheISA::VecElem &val)=0
gem5::ArmISA::MiscRegIndex
MiscRegIndex
Definition: misc.hh:59
gem5::ArmISA::MISCREG_AT_S12E1R_Xt
@ MISCREG_AT_S12E1R_Xt
Definition: misc.hh:672
gem5::ArmISA::MISCREG_TTBR1
@ MISCREG_TTBR1
Definition: misc.hh:257
gem5::ArmISA::isSecure
bool isSecure(ThreadContext *tc)
Definition: utility.cc:72
gem5::ArmISA::ISA::initializeMiscRegMetadata
void initializeMiscRegMetadata()
Definition: misc.cc:3400
gem5::ArmISA::TLBIIPA
TLB Invalidate by Intermediate Physical Address.
Definition: tlbi_op.hh:341
gem5::ArmISA::MISCREG_IFAR_S
@ MISCREG_IFAR_S
Definition: misc.hh:288
gem5::ArmISA::MISCREG_SP_EL2
@ MISCREG_SP_EL2
Definition: misc.hh:634
gem5::ArmISA::MISCREG_ID_AA64ISAR1_EL1
@ MISCREG_ID_AA64ISAR1_EL1
Definition: misc.hh:568
gem5::ArmISA::MISCREG_AT_S1E2W_Xt
@ MISCREG_AT_S1E2W_Xt
Definition: misc.hh:671
gem5::ArmISA::MISCREG_ID_AA64ZFR0_EL1
@ MISCREG_ID_AA64ZFR0_EL1
Definition: misc.hh:1054
gem5::ArmISA::ArmFault::getFsr
virtual FSR getFsr(ThreadContext *tc) const
Definition: faults.hh:254
gem5::ArmISA::ISA::haveVirtualization
bool haveVirtualization
Definition: isa.hh:93
gem5::ArmISA::MISCREG_DBGWCR1
@ MISCREG_DBGWCR1
Definition: misc.hh:155
gem5::ArmISA::MISCREG_TLBI_IPAS2LE1_Xt
@ MISCREG_TLBI_IPAS2LE1_Xt
Definition: misc.hh:698
gem5::ArmISA::MISCREG_DBGBCR7_EL1
@ MISCREG_DBGBCR7_EL1
Definition: misc.hh:481
gem5::ArmISA::ISA::highestELIs64
bool highestELIs64
Definition: isa.hh:90
gem5::ArmISA::MISCREG_DBGBCR5_EL1
@ MISCREG_DBGBCR5_EL1
Definition: misc.hh:479
gem5::ArmISA::MISCREG_MAIR0
@ MISCREG_MAIR0
Definition: misc.hh:372
gem5::ArmISA::MISCREG_TLBI_VAALE1IS_Xt
@ MISCREG_TLBI_VAALE1IS_Xt
Definition: misc.hh:683
gem5::ArmISA::ISA::haveSecurity
bool haveSecurity
Definition: isa.hh:91
gem5::ArmISA::HTMCheckpoint
Definition: htm.hh:58
gem5::ArmISA::MISCREG_DBGBCR10_EL1
@ MISCREG_DBGBCR10_EL1
Definition: misc.hh:484
gem5::ArmISA::ArmFault
Definition: faults.hh:64
gem5::X86ISA::reg
Bitfield< 5, 3 > reg
Definition: types.hh:92
gem5::ArmISA::MISCREG_DBGBCR4
@ MISCREG_DBGBCR4
Definition: misc.hh:126
gem5::ArmISA::ISA::setupThreadContext
void setupThreadContext()
Definition: isa.cc:464
gem5::ArmISA::MISCREG_TLBIASIDIS
@ MISCREG_TLBIASIDIS
Definition: misc.hh:323
gem5::ArmISA::ISA::lookUpMiscReg
static std::vector< struct MiscRegLUTEntry > lookUpMiscReg
Metadata table accessible via the value of the register.
Definition: isa.hh:141
gem5::FullSystem
bool FullSystem
The FullSystem variable can be used to determine the current mode of simulation.
Definition: root.cc:223
gem5::ArmISA::MISCREG_CNTVOFF_EL2
@ MISCREG_CNTVOFF_EL2
Definition: misc.hh:788
gem5::ArmISA::MISCREG_DBGWCR0_EL1
@ MISCREG_DBGWCR0_EL1
Definition: misc.hh:506
gem5::ArmISA::MISCREG_ATS12NSOPR
@ MISCREG_ATS12NSOPR
Definition: misc.hh:308
gem5::ArmISA::MISCREG_AIDR
@ MISCREG_AIDR
Definition: misc.hh:229
gem5::ArmISA::MISCREG_SPSR_EL3
@ MISCREG_SPSR_EL3
Definition: misc.hh:632
gem5::ArmISA::MISCREG_DBGWCR6
@ MISCREG_DBGWCR6
Definition: misc.hh:160
stat_control.hh
gem5::ArmISA::MISCREG_DBGWCR11_EL1
@ MISCREG_DBGWCR11_EL1
Definition: misc.hh:517
gem5::ArmISA::TLB::S1E0Tran
@ S1E0Tran
Definition: tlb.hh:140
gem5::ArmISA::MISCREG_FPSCR_QC
@ MISCREG_FPSCR_QC
Definition: misc.hh:81
gem5::Gicv3
Definition: gic_v3.hh:56
gem5::ArmISA::MISCREG_ATS1CPW
@ MISCREG_ATS1CPW
Definition: misc.hh:305
gem5::ArmISA::EL0
@ EL0
Definition: types.hh:266
panic_if
#define panic_if(cond,...)
Conditional panic macro that checks the supplied condition and only panics if the condition is true a...
Definition: logging.hh:203
gem5::ArmISA::MISCREG_CTR
@ MISCREG_CTR
Definition: misc.hh:206
gem5::ArmISA::MISCREG_PAN
@ MISCREG_PAN
Definition: misc.hh:1093
gem5::ArmSystem
Definition: system.hh:62
gem5::ArmISA::BaseISADevice::setThreadContext
virtual void setThreadContext(ThreadContext *tc)
Definition: isa_device.hh:68
gem5::ArmISA::MISCREG_DTLBIALL
@ MISCREG_DTLBIALL
Definition: misc.hh:330
gem5::ArmISA::MISCREG_HCR
@ MISCREG_HCR
Definition: misc.hh:248
gem5::ArmISA::MISCREG_DFAR_S
@ MISCREG_DFAR_S
Definition: misc.hh:285
gem5::ArmISA::MISCREG_TLBIMVAHIS
@ MISCREG_TLBIMVAHIS
Definition: misc.hh:342
gem5::ArmISA::MISCREG_ATS1HW
@ MISCREG_ATS1HW
Definition: misc.hh:320
gem5::ArmISA::ISA::haveVHE
bool haveVHE
Definition: isa.hh:99
gem5::ArmISA::ISA::MiscRegLUTEntryInitializer::highest
chain highest(ArmSystem *const sys) const
Definition: isa.cc:2536
gem5::ArmISA::MISCREG_TTBCR_NS
@ MISCREG_TTBCR_NS
Definition: misc.hh:261
gem5::ArmISA::MISCREG_ATS12NSOUW
@ MISCREG_ATS12NSOUW
Definition: misc.hh:311
gem5::Request::funcRequestorId
@ funcRequestorId
This requestor id is used for functional requests that don't come from a particular device.
Definition: request.hh:260
gem5::ArmSystem::sveVL
unsigned sveVL() const
Returns the SVE vector length at reset, in quadwords.
Definition: system.hh:235
base.hh
gem5::ArmISA::MISCREG_FPSCR_EXC
@ MISCREG_FPSCR_EXC
Definition: misc.hh:80
gem5::ArmISA::MISCREG_AT_S1E3R_Xt
@ MISCREG_AT_S1E3R_Xt
Definition: misc.hh:676
gem5::System::threads
Threads threads
Definition: system.hh:316
gem5::ArmISA::MISCREG_FPSCR
@ MISCREG_FPSCR
Definition: misc.hh:72
gem5::ArmISA::MISCREG_ZCR_EL1
@ MISCREG_ZCR_EL1
Definition: misc.hh:1058
gem5::ArmISA::MISCREG_TLBI_ASIDE1_Xt
@ MISCREG_TLBI_ASIDE1_Xt
Definition: misc.hh:686
gem5::SimObject::startup
virtual void startup()
startup() is the final initialization call before simulation.
Definition: sim_object.cc:99
gem5::ArmISA::MISCREG_CLIDR
@ MISCREG_CLIDR
Definition: misc.hh:228
gem5::ArmISA::MISCREG_ICH_AP0R0_EL2
@ MISCREG_ICH_AP0R0_EL2
Definition: misc.hh:885
gem5::ArmISA::DTLBIALL
Data TLB Invalidate All.
Definition: tlbi_op.hh:149
gem5::ArmISA::TLBIOp::broadcast
void broadcast(ThreadContext *tc)
Broadcast the TLB Invalidate operation to all TLBs in the Arm system.
Definition: tlbi_op.hh:73
gem5::ArmISA::ISA::miscRegs
RegVal miscRegs[NUM_MISCREGS]
Definition: isa.hh:460
gem5::ArmISA::TLB::S1E1Tran
@ S1E1Tran
Definition: tlb.hh:141
gem5::ArmISA::MISCREG_TLBIMVAALIS
@ MISCREG_TLBIMVAALIS
Definition: misc.hh:326
gem5::ArmISA::MISCREG_TLBIMVAH
@ MISCREG_TLBIMVAH
Definition: misc.hh:348
gem5::ArmISA::MISCREG_TLBI_VAALE1_Xt
@ MISCREG_TLBI_VAALE1_Xt
Definition: misc.hh:689
gem5::ArmISA::MISCREG_DBGBCR2
@ MISCREG_DBGBCR2
Definition: misc.hh:124
gem5::ArmISA::MISCREG_DBGBCR2_EL1
@ MISCREG_DBGBCR2_EL1
Definition: misc.hh:476
gem5::ArmISA::MISCREG_DBGWCR7_EL1
@ MISCREG_DBGWCR7_EL1
Definition: misc.hh:513
gem5::ArmISA::TLBIMVA
TLB Invalidate by VA.
Definition: tlbi_op.hh:296
gem5::ThreadContext::setMiscReg
virtual void setMiscReg(RegIndex misc_reg, RegVal val)=0
gem5::ArmISA::ISA::system
ArmSystem * system
Definition: isa.hh:72
gem5::ArmSystem::haveSecurity
bool haveSecurity() const
Returns true if this system implements the Security Extensions.
Definition: system.hh:162
gem5::ArmISA::MISCREG_DBGOSLSR
@ MISCREG_DBGOSLSR
Definition: misc.hh:188
gem5::ArmISA::NUM_CCREGS
@ NUM_CCREGS
Definition: cc.hh:55
gem5::ArmISA::TLB::S12E1Tran
@ S12E1Tran
Definition: tlb.hh:145
gem5::MipsISA::pc
Bitfield< 4 > pc
Definition: pra_constants.hh:243
gem5::ArmISA::TLBIVMALL
Implementaton of AArch64 TLBI VMALLE1(IS)/VMALLS112E1(IS) instructions.
Definition: tlbi_op.hh:188
gem5::ArmISA::MISCREG_ICC_PMR_EL1
@ MISCREG_ICC_PMR_EL1
Definition: misc.hh:837
gem5::ArmISA::MISCREG_SCR
@ MISCREG_SCR
Definition: misc.hh:243
reg_class.hh
gem5::ArmISA::MISCREG_ID_PFR0
@ MISCREG_ID_PFR0
Definition: misc.hh:211
gem5::ArmSystem::resetAddr
Addr resetAddr() const
Returns the reset address if the highest implemented exception level is 64 bits (ARMv8)
Definition: system.hh:220
gem5::ArmISA::MISCREG_VMPIDR_EL2
@ MISCREG_VMPIDR_EL2
Definition: misc.hh:578
gem5::ArmISA::MISCREG_PMEVCNTR0_EL0
@ MISCREG_PMEVCNTR0_EL0
Definition: misc.hh:790
gem5::ArmSystem::getGenericTimer
GenericTimer * getGenericTimer() const
Get a pointer to the system's generic timer model.
Definition: system.hh:195
gem5::ArmISA::MISCREG_TLBI_ALLE3
@ MISCREG_TLBI_ALLE3
Definition: misc.hh:707
gem5::ArmISA::MISCREG_REVIDR
@ MISCREG_REVIDR
Definition: misc.hh:210
gem5::ThreadContext::setCCReg
virtual void setCCReg(RegIndex reg_idx, RegVal val)=0
pmu.hh
gem5::ArmISA::TLB::ArmTranslationType
ArmTranslationType
Definition: tlb.hh:128
gem5::ArmISA::MISCREG_DBGBCR6_EL1
@ MISCREG_DBGBCR6_EL1
Definition: misc.hh:480
gem5::ArmISA::ISA::setMiscReg
void setMiscReg(int misc_reg, RegVal val)
Definition: isa.cc:883
gem5::ArmISA::BaseISADevice::setMiscReg
virtual void setMiscReg(int misc_reg, RegVal val)=0
Write to a system register belonging to this device.
gem5::ArmISA::MISCREG_FPSR
@ MISCREG_FPSR
Definition: misc.hh:622
gem5::ArmISA::MISCREG_ZCR_EL3
@ MISCREG_ZCR_EL3
Definition: misc.hh:1055
gem5::MipsISA::r
r
Definition: pra_constants.hh:98
gem5::CheckpointOut
std::ostream CheckpointOut
Definition: serialize.hh:66
gem5::ArmISA::NUM_PHYS_MISCREGS
@ NUM_PHYS_MISCREGS
Definition: misc.hh:1065
gem5::ThreadContext::getCpuPtr
virtual BaseCPU * getCpuPtr()=0
gem5::ArmISA::TLB::S12E0Tran
@ S12E0Tran
Definition: tlb.hh:144
gem5::ArmISA::MISCREG_SEV_MAILBOX
@ MISCREG_SEV_MAILBOX
Definition: misc.hh:92
gem5::ThreadContext::threadId
virtual int threadId() const =0
gem5::ArmISA::MISCREG_ID_ISAR6
@ MISCREG_ID_ISAR6
Definition: misc.hh:226
gem5::ArmISA::ISA::physAddrRange
uint8_t physAddrRange
Definition: isa.hh:96
gem5::ArmISA::MISCREG_DCZID_EL0
@ MISCREG_DCZID_EL0
Definition: misc.hh:576
gem5::ArmISA::MISCREG_FPCR
@ MISCREG_FPCR
Definition: misc.hh:621
gem5::ArmISA::DTLBIMVA
Data TLB Invalidate by VA.
Definition: tlbi_op.hh:327
gem5::ThreadContext::setVecRegFlat
virtual void setVecRegFlat(RegIndex idx, const TheISA::VecRegContainer &val)=0
gem5::ArmISA::MISCREG_CNTFRQ_EL0
@ MISCREG_CNTFRQ_EL0
Definition: misc.hh:753
gem5::ArmISA::SelfDebug::updateDBGWCR
void updateDBGWCR(int index, DBGWCR val)
Definition: self_debug.hh:415
self_debug.hh
gem5::BaseISA
Definition: isa.hh:54
gem5::ArmISA::ISA::MiscRegLUTEntryInitializer::hyp
chain hyp(bool v=true) const
Definition: isa.hh:326
gem5::ArmISA::sp
Bitfield< 0 > sp
Definition: misc_types.hh:74
gem5::ArmISA::MISCREG_DBGWCR2
@ MISCREG_DBGWCR2
Definition: misc.hh:156
gem5::ArmISA::ISA::afterStartup
bool afterStartup
Definition: isa.hh:113
gem5::ArmISA::MISCREG_TLBIMVAIS
@ MISCREG_TLBIMVAIS
Definition: misc.hh:322
gem5::ArmISA::MISCREG_AT_S12E1W_Xt
@ MISCREG_AT_S12E1W_Xt
Definition: misc.hh:673
gem5::ArmISA::MISCREG_HCR_EL2
@ MISCREG_HCR_EL2
Definition: misc.hh:586
gem5::ArmISA::MISCREG_TLBI_ALLE1IS
@ MISCREG_TLBI_ALLE1IS
Definition: misc.hh:694
gem5::ArmISA::MISCREG_TLBIASID
@ MISCREG_TLBIASID
Definition: misc.hh:335
gem5::ArmISA::MISCREG_ATS1CPR
@ MISCREG_ATS1CPR
Definition: misc.hh:304
gem5::ArmISA::MISCREG_TTBR0_EL1
@ MISCREG_TTBR0_EL1
Definition: misc.hh:597
gem5::ArmISA::MISCREG_DBGBCR11_EL1
@ MISCREG_DBGBCR11_EL1
Definition: misc.hh:485
gem5::ArmISA::MISCREG_TLBI_VALE3_Xt
@ MISCREG_TLBI_VALE3_Xt
Definition: misc.hh:709
gem5::ArmISA::MISCREG_TLBI_ALLE2
@ MISCREG_TLBI_ALLE2
Definition: misc.hh:699
gem5::ArmISA::MISCREG_TLBIMVAA
@ MISCREG_TLBIMVAA
Definition: misc.hh:336
gem5::ArmISA::MISCREG_ZCR_EL2
@ MISCREG_ZCR_EL2
Definition: misc.hh:1056
gem5::ArmISA::ISA::addressTranslation64
void addressTranslation64(TLB::ArmTranslationType tran_type, BaseMMU::Mode mode, Request::Flags flags, RegVal val)
Definition: isa.cc:2418
gem5::ArmISA::MISCREG_SCTLR_RST
@ MISCREG_SCTLR_RST
Definition: misc.hh:91
gem5::ArmISA::MISCREG_TLBI_VMALLE1
@ MISCREG_TLBI_VMALLE1
Definition: misc.hh:684
gem5::ArmISA::MISCREG_DBGWCR8_EL1
@ MISCREG_DBGWCR8_EL1
Definition: misc.hh:514
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40
gem5::ArmISA::MISCREG_ID_AA64PFR0_EL1
@ MISCREG_ID_AA64PFR0_EL1
Definition: misc.hh:561
gem5::ArmISA::MISCREG_DBGDSCRint
@ MISCREG_DBGDSCRint
Definition: misc.hh:96
gem5::ArmISA::MISCREG_DBGWCR12
@ MISCREG_DBGWCR12
Definition: misc.hh:166
gem5::ArmISA::MISCREG_TLBIMVAAIS
@ MISCREG_TLBIMVAAIS
Definition: misc.hh:324
gem5::ArmISA::MISCREG_TLBI_VAE1_Xt
@ MISCREG_TLBI_VAE1_Xt
Definition: misc.hh:685
gem5::ArmISA::SelfDebug::setDebugMask
void setDebugMask(bool mask)
Definition: self_debug.hh:421
gem5::ArmSystem::haveSecEL2
bool haveSecEL2() const
Returns true if Priviledge Access Never is implemented.
Definition: system.hh:247
gem5::ArmISA::MISCREG_TLBIALLNSNH
@ MISCREG_TLBIALLNSNH
Definition: misc.hh:349
gem5::ArmISA::ArmFault::isStage2
virtual bool isStage2() const
Definition: faults.hh:253
gem5::ArmSystem::haveTME
bool haveTME() const
Returns true if this system implements the transactional memory extension (ARMv9)
Definition: system.hh:229
gem5::GenericTimerISA
Definition: generic_timer.hh:390
gem5::ArmISA::CCREG_V
@ CCREG_V
Definition: cc.hh:51
gem5::ArmISA::MISCREG_ID_MMFR0
@ MISCREG_ID_MMFR0
Definition: misc.hh:215
gem5::ArmISA::MMU
Definition: mmu.hh:52
gem5::ArmISA::MISCREG_TLBI_VMALLE1IS
@ MISCREG_TLBI_VMALLE1IS
Definition: misc.hh:678
UNSERIALIZE_MAPPING
#define UNSERIALIZE_MAPPING(member, names, size)
Definition: serialize.hh:666
gem5::ArmISA::MISCREG_TLBI_VAE3IS_Xt
@ MISCREG_TLBI_VAE3IS_Xt
Definition: misc.hh:705
gem5::ThreadContext::readVecRegFlat
virtual const TheISA::VecRegContainer & readVecRegFlat(RegIndex idx) const =0
gem5::ArmISA::MISCREG_TLBI_IPAS2E1_Xt
@ MISCREG_TLBI_IPAS2E1_Xt
Definition: misc.hh:697
gem5::loader::Arm
@ Arm
Definition: object_file.hh:59
gem5::ArmISA::MISCREG_CPACR
@ MISCREG_CPACR
Definition: misc.hh:241
gem5::ArmISA::MISCREG_MDSCR_EL1
@ MISCREG_MDSCR_EL1
Definition: misc.hh:455
gem5::ArmISA::MISCREG_DBGBCR14_EL1
@ MISCREG_DBGBCR14_EL1
Definition: misc.hh:488
gem5::ThreadContext::getCheckerCpuPtr
virtual CheckerCPU * getCheckerCpuPtr()=0
gic_v3.hh
gem5::ArmISA::preUnflattenMiscReg
void preUnflattenMiscReg()
Definition: misc.cc:1349
gem5::ArmISA::MISCREG_DBGBCR7
@ MISCREG_DBGBCR7
Definition: misc.hh:129
gem5::ArmISA::ISA::clear32
void clear32(const ArmISAParams &p, const SCTLR &sctlr_rst)
Definition: isa.cc:225
gem5::ArmISA::MISCREG_ISR_EL1
@ MISCREG_ISR_EL1
Definition: misc.hh:739
gem5::ArmISA::MISCREG_ID_AA64ISAR0_EL1
@ MISCREG_ID_AA64ISAR0_EL1
Definition: misc.hh:567
gem5::ArmISA::ISA::haveCrypto
bool haveCrypto
Definition: isa.hh:94
gem5::ArmISA::MISCREG_OSLAR_EL1
@ MISCREG_OSLAR_EL1
Definition: misc.hh:528
gem5::ArmISA::MISCREG_AT_S1E1R_Xt
@ MISCREG_AT_S1E1R_Xt
Definition: misc.hh:659
gem5::ArmISA::readMPIDR
RegVal readMPIDR(ArmSystem *arm_sys, ThreadContext *tc)
This helper function is either returing the value of MPIDR_EL1 (by calling getMPIDR),...
Definition: utility.cc:134
gem5::ArmISA::MISCREG_TTBR1_EL2
@ MISCREG_TTBR1_EL2
Definition: misc.hh:820
gem5::ArmISA::MISCREG_DBGBCR13
@ MISCREG_DBGBCR13
Definition: misc.hh:135
gem5::ArmISA::MISCREG_ID_DFR0
@ MISCREG_ID_DFR0
Definition: misc.hh:213
gem5::ArmISA::MMU::invalidateMiscReg
void invalidateMiscReg(TLBType type=ALL_TLBS)
Definition: mmu.cc:132
gem5::ArmSystem::haveVirtualization
bool haveVirtualization() const
Returns true if this system implements the virtualization Extensions.
Definition: system.hh:171
gem5::ArmISA::MISCREG_TLBIIPAS2LIS
@ MISCREG_TLBIIPAS2LIS
Definition: misc.hh:340
gem5::ArmISA::MISCREG_ITLBIALL
@ MISCREG_ITLBIALL
Definition: misc.hh:327
gem5::ArmISA::MISCREG_TLBI_VAE2IS_Xt
@ MISCREG_TLBI_VAE2IS_Xt
Definition: misc.hh:693
gem5::ArmISA::unflattenMiscReg
int unflattenMiscReg(int reg)
Definition: misc.cc:1365
gem5::ArmISA::ISA::assert64
void assert64()
Definition: isa.hh:506
gem5::ArmISA::MISCREG_TCR_EL1
@ MISCREG_TCR_EL1
Definition: misc.hh:601
gem5::ArmISA::ExceptionLevel
ExceptionLevel
Definition: types.hh:264
panic
#define panic(...)
This implements a cprintf based panic() function.
Definition: logging.hh:177
gem5::ArmISA::MISCREG_TLBI_ALLE2IS
@ MISCREG_TLBI_ALLE2IS
Definition: misc.hh:692
gem5::ArmISA::BaseISADevice
Base class for devices that use the MiscReg interfaces.
Definition: isa_device.hh:61
gem5::ArmISA::MISCREG_TLBI_VAE3_Xt
@ MISCREG_TLBI_VAE3_Xt
Definition: misc.hh:708
gem5::ArmISA::mode
Bitfield< 4, 0 > mode
Definition: misc_types.hh:73
gem5::ThreadContext::setMiscRegNoEffect
virtual void setMiscRegNoEffect(RegIndex misc_reg, RegVal val)=0
gem5::ArmISA::MISCREG_WARN_NOT_FAIL
@ MISCREG_WARN_NOT_FAIL
Definition: misc.hh:1104
gem5::ArmISA::MISCREG_AT_S1E2R_Xt
@ MISCREG_AT_S1E2R_Xt
Definition: misc.hh:670
gem5::ArmISA::MISCREG_DBGWCR13_EL1
@ MISCREG_DBGWCR13_EL1
Definition: misc.hh:519
gem5::ArmISA::MISCREG_CPSR_Q
@ MISCREG_CPSR_Q
Definition: misc.hh:79

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