55 #include "debug/Arm.hh"
56 #include "debug/LLSC.hh"
57 #include "debug/VecPredRegs.hh"
58 #include "debug/VecRegs.hh"
62 #include "params/ArmISA.hh"
82 _decoderFlavor(
p.decoderFlavor), pmu(
p.pmu), impdefAsNop(
p.impdef_nop)
157 mvfr0.advSimdRegisters = 2;
158 mvfr0.singlePrecision = 2;
159 mvfr0.doublePrecision = 2;
160 mvfr0.vfpExceptionTrapping = 0;
162 mvfr0.squareRoot = 1;
163 mvfr0.shortVectors = 1;
164 mvfr0.roundingModes = 1;
168 mvfr1.flushToZero = 1;
169 mvfr1.defaultNaN = 1;
170 mvfr1.advSimdLoadStore = 1;
171 mvfr1.advSimdInteger = 1;
172 mvfr1.advSimdSinglePrecision = 1;
173 mvfr1.advSimdHalfPrecision = 1;
174 mvfr1.vfpHalfPrecision = 1;
235 sctlr.te = (bool) sctlr_rst.te;
236 sctlr.nmfi = (
bool) sctlr_rst.nmfi;
237 sctlr.v = (bool) sctlr_rst.v;
295 panic(
"Invalid highest implemented exception level");
311 }
else if (
release->
has(ArmExtension::VIRTUALIZATION)) {
359 release->
has(ArmExtension::CRYPTO) ? 0x1112 : 0x0);
363 release->
has(ArmExtension::FEAT_RDM) ? 0x1 : 0x0);
367 release->
has(ArmExtension::FEAT_FCMA) ? 0x1 : 0x0);
372 release->
has(ArmExtension::FEAT_JSCVT) ? 0x1 : 0x0);
382 (
p.id_aa64dfr0_el1 & 0xfffffffffffff0ffULL) |
383 (
p.pmu ? 0x0000000000000100ULL : 0);
393 (
p.pmu ? 0x03000000ULL : 0);
401 }
else if (
release->
has(ArmExtension::VIRTUALIZATION)) {
412 release->
has(ArmExtension::SECURITY) ? 0x2 : 0x0);
416 release->
has(ArmExtension::VIRTUALIZATION) ? 0x2 : 0x0);
420 release->
has(ArmExtension::FEAT_SVE) ? 0x1 : 0x0);
424 release->
has(ArmExtension::FEAT_SEL2) ? 0x1 : 0x0);
439 release->
has(ArmExtension::CRYPTO) ? 0x1112 : 0x0);
443 release->
has(ArmExtension::FEAT_LSE) ? 0x2 : 0x0);
447 release->
has(ArmExtension::FEAT_RDM) ? 0x1 : 0x0);
453 release->
has(ArmExtension::FEAT_PAuth) ? 0x1 : 0x0);
457 release->
has(ArmExtension::FEAT_JSCVT) ? 0x1 : 0x0);
461 release->
has(ArmExtension::FEAT_FCMA) ? 0x1 : 0x0);
465 release->
has(ArmExtension::FEAT_PAuth) ? 0x1 : 0x0);
471 release->
has(ArmExtension::FEAT_VMID16) ? 0x2 : 0x0);
475 release->
has(ArmExtension::FEAT_VHE) ? 0x1 : 0x0);
479 release->
has(ArmExtension::FEAT_HPDS) ? 0x1 : 0x0);
483 release->
has(ArmExtension::FEAT_PAN) ? 0x1 : 0x0);
489 release->
has(ArmExtension::FEAT_UAO) ? 0x1 : 0x0);
493 release->
has(ArmExtension::FEAT_LVA) ? 0x1 : 0x0);
528 gicv3_ifc->setISA(
this);
529 gicv3_ifc->setThreadContext(
tc);
583 bool sec_el2 = scr.eel2 &&
release->
has(ArmExtension::FEAT_SEL2);
729 int lower = map.first, upper = map.second;
735 DPRINTF(MiscRegs,
"Reading MiscReg %s with set res0 bits: %#x\n",
739 DPRINTF(MiscRegs,
"Reading MiscReg %s with clear res1 bits: %#x\n",
755 cpsr.j =
pc.jazelle() ? 1 : 0;
756 cpsr.t =
pc.thumb() ? 1 : 0;
764 warn(
"Unimplemented system register %s read.\n",
767 panic(
"Unimplemented system register %s read.\n",
776 if (!
release->
has(ArmExtension::VIRTUALIZATION))
781 const uint32_t ones = (uint32_t)(-1);
785 cpacrMask.cp10 = ones;
786 cpacrMask.cp11 = ones;
787 cpacrMask.asedis = ones;
796 if (!nsacr.cp10) cpacrMask.cp10 = 0;
797 if (!nsacr.cp11) cpacrMask.cp11 = 0;
802 DPRINTF(MiscRegs,
"Reading misc reg %s: %#x\n",
832 warn_once(
"The clidr register always reports 0 caches.\n");
833 warn_once(
"clidr LoUIS field of 0b001 to match current "
834 "ARM implementations.\n");
837 warn_once(
"The ccsidr register isn't implemented and "
838 "always reads as 0.\n");
845 unsigned lineSizeWords =
847 unsigned log2LineSizeWords = 0;
849 while (lineSizeWords >>= 1) {
855 ctr.iCacheLineSize = log2LineSizeWords;
857 ctr.l1IndexPolicy = 0x3;
859 ctr.dCacheLineSize = log2LineSizeWords;
861 ctr.erg = log2LineSizeWords;
863 ctr.cwg = log2LineSizeWords;
870 warn(
"Not doing anything for miscreg ACTLR\n");
880 panic(
"shouldn't be reading this register seperately\n");
887 const uint32_t ones = (uint32_t)(-1);
889 fpscrMask.ioc = ones;
890 fpscrMask.dzc = ones;
891 fpscrMask.ofc = ones;
892 fpscrMask.ufc = ones;
893 fpscrMask.ixc = ones;
894 fpscrMask.idc = ones;
904 const uint32_t ones = (uint32_t)(-1);
906 fpscrMask.len = ones;
907 fpscrMask.fz16 = ones;
908 fpscrMask.stride = ones;
909 fpscrMask.rMode = ones;
912 fpscrMask.ahp = ones;
991 bool secure_lookup =
release->
has(ArmExtension::SECURITY) &&
993 if (!secure_lookup) {
995 val |= (
mask ^ 0x7FFF) & 0xBFFF;
1015 (
release->
has(ArmExtension::VIRTUALIZATION) ?
1017 (have_timer ? 0x00010000 : 0x0);
1020 return 0x0000000000000002 |
1021 0x0000000000000020 |
1022 (
release->
has(ArmExtension::VIRTUALIZATION) ?
1023 0x0000000000000200 : 0) |
1025 0x0000000000002000 : 0) |
1027 0x0000000100000000 : 0) |
1029 0x0000001000000000 : 0) |
1058 int lower = map.first, upper = map.second;
1064 DPRINTF(MiscRegs,
"Writing MiscReg %s (%d %d:%d) : %#x\n",
1068 DPRINTF(MiscRegs,
"Writing MiscReg %s (%d %d) : %#x\n",
1086 int old_mode = old_cpsr.mode;
1088 if (cpsr.pan != old_cpsr.pan || cpsr.il != old_cpsr.il) {
1092 DPRINTF(
Arm,
"Updating CPSR from %#x to %#x f:%d i:%d a:%d mode:%#x\n",
1093 miscRegs[idx], cpsr, cpsr.f, cpsr.i, cpsr.a, cpsr.mode);
1095 pc.nextThumb(cpsr.t);
1096 pc.nextJazelle(cpsr.j);
1097 pc.illegalExec(cpsr.il == 1);
1114 if (old_mode != cpsr.mode) {
1134 warn(
"Unimplemented system register %s write with %#x.\n",
1137 panic(
"Unimplemented system register %s write with %#x.\n",
1147 const uint32_t ones = (uint32_t)(-1);
1148 CPACR cpacrMask = 0;
1151 cpacrMask.cp10 = ones;
1152 cpacrMask.cp11 = ones;
1153 cpacrMask.asedis = ones;
1162 if (!nsacr.cp10) cpacrMask.cp10 = 0;
1163 if (!nsacr.cp11) cpacrMask.cp11 = 0;
1168 newVal &= cpacrMask;
1169 newVal |= old_val & ~cpacrMask;
1170 DPRINTF(MiscRegs,
"Writing misc reg %s: %#x\n",
1176 const uint32_t ones = (uint32_t)(-1);
1177 CPACR cpacrMask = 0;
1178 cpacrMask.tta = ones;
1179 cpacrMask.fpen = ones;
1181 cpacrMask.zen = ones;
1183 newVal &= cpacrMask;
1184 DPRINTF(MiscRegs,
"Writing misc reg %s: %#x\n",
1191 const uint32_t ones = (uint32_t)(-1);
1193 cptrMask.tcpac = ones;
1194 cptrMask.tta = ones;
1195 cptrMask.tfp = ones;
1198 cptrMask.zen = hcr.e2h ? ones : 0;
1200 cptrMask.fpen = hcr.e2h ? ones : 0;
1203 cptrMask.res1_13_12_el2 = ones;
1204 cptrMask.res1_7_0_el2 = ones;
1206 cptrMask.res1_8_el2 = ones;
1208 cptrMask.res1_9_el2 = ones;
1210 DPRINTF(MiscRegs,
"Writing misc reg %s: %#x\n",
1216 const uint32_t ones = (uint32_t)(-1);
1218 cptrMask.tcpac = ones;
1219 cptrMask.tta = ones;
1220 cptrMask.tfp = ones;
1225 DPRINTF(MiscRegs,
"Writing misc reg %s: %#x\n",
1230 warn_once(
"The csselr register isn't implemented.\n");
1234 warn(
"Calling DC ZVA! Not Implemeted! Expect WEIRD results\n");
1239 const uint32_t ones = (uint32_t)(-1);
1240 FPSCR fpscrMask = 0;
1241 fpscrMask.ioc = ones;
1242 fpscrMask.dzc = ones;
1243 fpscrMask.ofc = ones;
1244 fpscrMask.ufc = ones;
1245 fpscrMask.ixc = ones;
1246 fpscrMask.idc = ones;
1247 fpscrMask.ioe = ones;
1248 fpscrMask.dze = ones;
1249 fpscrMask.ofe = ones;
1250 fpscrMask.ufe = ones;
1251 fpscrMask.ixe = ones;
1252 fpscrMask.ide = ones;
1253 fpscrMask.len = ones;
1254 fpscrMask.fz16 = ones;
1255 fpscrMask.stride = ones;
1256 fpscrMask.rMode = ones;
1257 fpscrMask.fz = ones;
1258 fpscrMask.dn = ones;
1259 fpscrMask.ahp = ones;
1260 fpscrMask.qc = ones;
1265 newVal = (newVal & (uint32_t)fpscrMask) |
1267 ~(uint32_t)fpscrMask);
1273 const uint32_t ones = (uint32_t)(-1);
1274 FPSCR fpscrMask = 0;
1275 fpscrMask.ioc = ones;
1276 fpscrMask.dzc = ones;
1277 fpscrMask.ofc = ones;
1278 fpscrMask.ufc = ones;
1279 fpscrMask.ixc = ones;
1280 fpscrMask.idc = ones;
1281 fpscrMask.qc = ones;
1286 newVal = (newVal & (uint32_t)fpscrMask) |
1288 ~(uint32_t)fpscrMask);
1294 const uint32_t ones = (uint32_t)(-1);
1295 FPSCR fpscrMask = 0;
1296 fpscrMask.len = ones;
1297 fpscrMask.fz16 = ones;
1298 fpscrMask.stride = ones;
1299 fpscrMask.rMode = ones;
1300 fpscrMask.fz = ones;
1301 fpscrMask.dn = ones;
1302 fpscrMask.ahp = ones;
1303 newVal = (newVal & (uint32_t)fpscrMask) |
1305 ~(uint32_t)fpscrMask);
1334 const uint32_t fpexcMask = 0x60000000;
1335 newVal = (newVal & fpexcMask) |
1340 if (!
release->
has(ArmExtension::VIRTUALIZATION))
1347 if (!
release->
has(ArmExtension::VIRTUALIZATION))
1361 const uint32_t temp = (
val == 0xC5ACCE55)? 0x1 : 0x0;
1363 r.oslk =
bits(temp,0);
1482 r.udccdis =
v.udccdis;
1483 r.mdbgen =
v.mdbgen;
1604 const uint32_t ifsrMask =
1606 newVal = newVal & ~ifsrMask;
1612 const uint32_t dfsrMask =
mask(31, 14) |
mask(8, 8);
1613 newVal = newVal & ~dfsrMask;
1623 DPRINTF(MiscRegs,
"Writing AMAIR: %#x\n", newVal);
1631 DPRINTF(MiscRegs,
"Writing SCTLR: %#x\n", newVal);
1643 SCTLR new_sctlr = newVal;
1644 new_sctlr.nmfi = ((bool)sctlr.nmfi) &&
1687 warn(
"Not doing anything for write of miscreg ACTLR\n");
1702 newVal &= ~((uint32_t) hstrMask);
1709 secure_lookup =
release->
has(ArmExtension::SECURITY) &&
1711 if (!secure_lookup) {
1715 newVal = (newVal & ~
mask) | (oldValue &
mask);
1741 panic(
"Security Extensions required for ATS12NSOPR");
1746 panic(
"Security Extensions required for ATS12NSOPW");
1751 panic(
"Security Extensions required for ATS12NSOUR");
1757 panic(
"Security Extensions required for ATS12NSOUW");
1770 const uint32_t ones = (uint32_t)(-1);
1771 TTBCR ttbcrMask = 0;
1772 TTBCR ttbcrNew = newVal;
1777 ttbcrMask.pd0 = ones;
1778 ttbcrMask.pd1 = ones;
1780 ttbcrMask.epd0 = ones;
1781 ttbcrMask.irgn0 = ones;
1782 ttbcrMask.orgn0 = ones;
1783 ttbcrMask.sh0 = ones;
1784 ttbcrMask.ps = ones;
1785 ttbcrMask.a1 = ones;
1786 ttbcrMask.epd1 = ones;
1787 ttbcrMask.irgn1 = ones;
1788 ttbcrMask.orgn1 = ones;
1789 ttbcrMask.sh1 = ones;
1791 ttbcrMask.eae = ones;
1793 if (
release->
has(ArmExtension::LPAE) && ttbcrNew.eae) {
1794 newVal = newVal & ttbcrMask;
1796 newVal = (newVal & ttbcrMask) | (ttbcr & (~ttbcrMask));
1810 uint64_t ttbrMask =
mask(63,56) |
mask(47,40);
1811 newVal = (newVal & (~ttbrMask));
1860 cpsr.daif = (uint8_t) ((CPSR) newVal).
daif;
1877 cpsr.sp = (uint8_t) ((CPSR) newVal).
sp;
1885 cpsr.el = (uint8_t) ((CPSR) newVal).
el;
1896 cpsr.pan = (uint8_t) ((CPSR) newVal).
pan;
1907 cpsr.uao = (uint8_t) ((CPSR) newVal).
uao;
1953 warn(
"miscreg L2CTLR (%s) written with %#x. ignored...\n",
1988 return *
timer.get();
1992 if (!generic_timer) {
1993 panic(
"Trying to get a generic timer from a system that hasn't "
1994 "been configured to use a generic timer.\n");
2000 return *
timer.get();
2010 panic_if(!gicv3_ifc,
"The system does not have a GICv3 irq controller\n");
2068 "A ThreadContext is needed to determine the SVE vector length "
2069 "in full-system mode");
2086 static_cast<unsigned>(
2092 }
else if (
release->
has(ArmExtension::SECURITY)) {
2095 static_cast<unsigned>(
2101 return (
len + 1) * 128;
2107 DPRINTF(Checkpoint,
"Serializing Arm Misc Registers\n");
2114 DPRINTF(Checkpoint,
"Unserializing Arm Misc Registers\n");
2130 warn_once(
"Doing AT (address translation) in functional mode! Fix Me!\n");
2132 auto req = std::make_shared<Request>(
2137 req,
tc,
mode, tran_type);
2141 Addr paddr = req->getPaddr();
2143 uint64_t attr1 =
attr >> 56;
2144 if (!attr1 || attr1 ==0x44) {
2146 attr &= ~ uint64_t(0x80);
2148 par = (paddr &
mask(47, 12)) |
attr;
2150 "MISCREG: Translated addr %#x: PAR_EL1: %#xx\n",
2159 par.fst = fsr.status;
2160 par.ptw = (arm_fault->
iss() >> 7) & 0x1;
2161 par.s = arm_fault->
isStage2() ? 1 : 0;
2164 "MISCREG: Translated addr %#x fault fsr %#x: PAR: %#x\n",
2181 warn_once(
"Doing AT (address translation) in functional mode! Fix Me!\n");
2183 auto req = std::make_shared<Request>(
2188 req,
tc,
mode, tran_type);
2192 Addr paddr = req->getPaddr();
2196 uint8_t max_paddr_bit = 0;
2206 par = (paddr &
mask(max_paddr_bit, 12)) |
2210 "MISCREG: Translated addr 0x%08x: PAR: 0x%08x\n",
2219 par.lpae = fsr.lpae;
2220 par.ptw = (arm_fault->
iss() >> 7) & 0x1;
2221 par.s = arm_fault->
isStage2() ? 1 : 0;
2225 par.fst = fsr.status;
2228 par.fs4_0 = fsr.fsLow | (fsr.fsHigh << 5);
2232 "MISCREG: Translated addr 0x%08x fault fsr %#x: PAR: 0x%08x\n",
2242 Addr cacheBlockMask)
2247 DPRINTF(LLSC,
"%s: handling snoop for address: %#x locked: %d\n",
2255 Addr snoop_addr = pkt->
getAddr() & cacheBlockMask;
2257 DPRINTF(LLSC,
"%s: handling snoop for address: %#x locked addr: %#x\n",
2259 if (locked_addr == snoop_addr) {
2260 DPRINTF(LLSC,
"%s: address match, clearing lock and signaling sev\n",
2286 DPRINTF(LLSC,
"%s: Placing address %#x in monitor\n",
2295 DPRINTF(LLSC,
"%s: Placing address %#x in monitor\n",
2302 DPRINTF(LLSC,
"%s: handling snoop lock hit address: %#x\n",
2311 DPRINTF(LLSC,
"%s: handling snoop lock hit address: %#x\n",
2321 Addr cacheBlockMask)
2326 DPRINTF(LLSC,
"Handling locked write for address %#x in monitor.\n",
2332 if (!lock_flag || (req->getPaddr() & cacheBlockMask) != lock_addr) {
2335 req->setExtraData(0);
2337 DPRINTF(LLSC,
"clearing lock flag in handle locked write\n",
2343 int stCondFailures = xc->readStCondFailures();
2345 xc->setStCondFailures(stCondFailures);
2346 if (stCondFailures % 100000 == 0) {
2347 warn(
"context %d: %d consecutive "
2348 "store conditional failures\n",
2366 Addr cacheBlockMask)
2378 DPRINTF(LLSC,
"Clearing lock and signaling sev\n");
2392 DPRINTF(LLSC,
"Clearing lock and signaling sev\n");
ISA-specific types for hardware transactional memory.
virtual FSR getFsr(ThreadContext *tc) const
virtual uint32_t iss() const =0
void update(ThreadContext *tc)
virtual bool isStage2() const
Base class for devices that use the MiscReg interfaces.
virtual void setMiscReg(int misc_reg, RegVal val)=0
Write to a system register belonging to this device.
virtual void setISA(ISA *isa)
virtual void setThreadContext(ThreadContext *tc)
virtual RegVal readMiscReg(int misc_reg)=0
Read a system register belonging to this device.
bool inSecureState() const
Return true if the PE is in Secure state.
void clear32(const ArmISAParams &p, const SCTLR &sctlr_rst)
unsigned getCurSveVecLenInBits() const
std::pair< int, int > getMiscIndices(int misc_reg) const
ExceptionLevel currEL() const
Returns the current Exception Level (EL) of the ISA object.
void takeOverFrom(ThreadContext *new_tc, ThreadContext *old_tc) override
void serialize(CheckpointOut &cp) const override
Serialize an object.
void copyRegsFrom(ThreadContext *src) override
void initID64(const ArmISAParams &p)
DummyISADevice dummyDevice
Dummy device for to handle non-existing ISA devices.
void setupThreadContext()
void setMiscRegNoEffect(RegIndex idx, RegVal val) override
void addressTranslation64(MMU::ArmTranslationType tran_type, BaseMMU::Mode mode, Request::Flags flags, RegVal val)
void handleLockedSnoop(PacketPtr pkt, Addr cacheBlockMask) override
void initID32(const ArmISAParams &p)
RegVal miscRegs[NUM_MISCREGS]
void clear64(const ArmISAParams &p)
std::unique_ptr< BaseISADevice > timer
bool handleLockedWrite(const RequestPtr &req, Addr cacheBlockMask) override
void globalClearExclusive() override
void unserialize(CheckpointIn &cp) override
Unserialize an object.
void updateRegMap(CPSR cpsr)
void startup() override
startup() is the final initialization call before simulation.
int redirectRegVHE(int misc_reg)
Returns the enconcing equivalent when VHE is implemented and HCR_EL2.E2H is enabled and executing at ...
BaseISADevice & getGICv3CPUInterface()
BaseISADevice & getGenericTimer()
RegVal readMiscRegNoEffect(RegIndex idx) const override
void setMiscReg(RegIndex, RegVal val) override
unsigned sveVL
SVE vector length in quadwords.
void handleLockedRead(const RequestPtr &req) override
void addressTranslation(MMU::ArmTranslationType tran_type, BaseMMU::Mode mode, Request::Flags flags, RegVal val)
void initializeMiscRegMetadata()
const ArmRelease * release
This could be either a FS or a SE release.
RegVal readMiscReg(RegIndex idx) override
void handleLockedSnoopHit() override
std::unique_ptr< BaseISADevice > gicv3CpuInterface
TranslationGenPtr translateFunctional(Addr start, Addr size, ThreadContext *tc, Mode mode, Request::Flags flags) override
Returns a translation generator for a region of virtual addresses, instead of directly translating a ...
void setenableTDETGE(HCR hcr, HDCR mdcr)
void init(ThreadContext *tc)
void updateOSLock(RegVal val)
void setMDSCRvals(RegVal val)
void updateDBGBCR(int index, DBGBCR val)
void updateDBGWCR(int index, DBGWCR val)
void setMDBGen(RegVal val)
void setDebugMask(bool mask)
bool has(ArmExtension ext) const
bool highestELIs64() const
Returns true if the register width of the highest implemented exception level is 64 bits (ARMv8)
BaseGic * getGIC() const
Get a pointer to the system's GIC.
ArmISA::ExceptionLevel highestEL() const
Returns the highest implemented exception level.
uint8_t physAddrRange() const
Returns the supported physical address range in bits.
bool haveLargeAsid64() const
Returns true if ASID is 16 bits in AArch64 (ARMv8)
Addr resetAddr() const
Returns the reset address if the highest implemented exception level is 64 bits (ARMv8)
GenericTimer * getGenericTimer() const
Get a pointer to the system's generic timer model.
unsigned sveVL() const
Returns the SVE vector length at reset, in quadwords.
const ArmRelease * releaseFS() const
BaseInterrupts * getInterruptController(ThreadID tid)
The ExecContext is an abstract base class the provides the interface used by the ISA to manipulate th...
virtual RegVal readMiscReg(int misc_reg)=0
Reads a miscellaneous register, handling any architectural side effects due to reading that register.
virtual void setMiscReg(int misc_reg, RegVal val)=0
Sets a miscellaneous register, handling any architectural side effects due to writing that register.
virtual ThreadContext * tcBase() const =0
Returns a pointer to the ThreadContext.
Gicv3CPUInterface * getCPUInterface(int cpu_id) const
virtual std::string name() const
Addr instAddr() const
Returns the memory address of the instruction this PC points to.
A Packet is used to encapsulate a transfer between two objects in the memory system (e....
bool isInvalidate() const
@ funcRequestorId
This requestor id is used for functional requests that don't come from a particular device.
unsigned int cacheLineSize() const
Get the cache line size of the system.
ThreadContext is the external interface to all thread state for anything outside of the CPU.
virtual RegVal readMiscReg(RegIndex misc_reg)=0
virtual void setHtmCheckpointPtr(BaseHTMCheckpointPtr cpt)=0
virtual void pcStateNoRecord(const PCStateBase &val)=0
virtual void setMiscReg(RegIndex misc_reg, RegVal val)=0
virtual RegVal getReg(const RegId ®) const
virtual void setMiscRegNoEffect(RegIndex misc_reg, RegVal val)=0
virtual const PCStateBase & pcState() const =0
virtual System * getSystemPtr()=0
virtual CheckerCPU * getCheckerCpuPtr()=0
virtual void setReg(const RegId ®, RegVal val)
virtual InstDecoder * getDecoderPtr()=0
virtual BaseCPU * getCpuPtr()=0
virtual int threadId() const =0
virtual RegVal readMiscRegNoEffect(RegIndex misc_reg) const =0
virtual ContextID contextId() const =0
virtual BaseMMU * getMMUPtr()=0
Vector Register Abstraction This generic class is the model in a particularization of MVC,...
This module implements the global system counter and the local per-CPU architected timers as specifie...
constexpr T bits(T val, unsigned first, unsigned last)
Extract the bitfield from position 'first' to 'last' (inclusive) from 'val' and right justify it.
constexpr T insertBits(T val, unsigned first, unsigned last, B bit_val)
Returns val with bits first to last set to the LSBs of bit_val.
#define panic(...)
This implements a cprintf based panic() function.
#define panic_if(cond,...)
Conditional panic macro that checks the supplied condition and only panics if the condition is true a...
virtual void startup()
startup() is the final initialization call before simulation.
const Params & params() const
bool ELIs32(ThreadContext *tc, ExceptionLevel el)
constexpr RegClass flatIntRegClass
static const uint32_t FpscrQcMask
uint8_t encodePhysAddrRange64(int pa_size)
Returns the encoding corresponding to the specified n.
bool ELIsInHost(ThreadContext *tc, ExceptionLevel el)
Returns true if the current exception level el is executing a Host OS or an application of a Host OS ...
constexpr RegClass ccRegClass(CCRegClass, CCRegClassName, cc_reg::NumRegs, debug::CCRegs)
bool isSecure(ThreadContext *tc)
static const uint32_t FpscrExcMask
void sendEvent(ThreadContext *tc)
Send an event (SEV) to a specific PE if there isn't already a pending event.
constexpr RegClass vecElemClass
static const uint32_t CpsrMaskQ
void preUnflattenMiscReg()
constexpr RegClass vecPredRegClass
@ MISCREG_ID_AA64PFR0_EL1
@ MISCREG_ICC_IGRPEN1_EL3
@ MISCREG_ID_AA64ZFR0_EL1
@ MISCREG_ID_AA64DFR0_EL1
@ MISCREG_ID_AA64DFR1_EL1
@ MISCREG_ID_AA64ISAR1_EL1
@ MISCREG_ID_AA64MMFR1_EL1
@ MISCREG_CNTHPS_CVAL_EL2
@ MISCREG_CNTHPS_TVAL_EL2
@ MISCREG_ID_AA64MMFR0_EL1
@ MISCREG_CNTHVS_TVAL_EL2
@ MISCREG_CNTHVS_CVAL_EL2
@ MISCREG_ID_AA64MMFR2_EL1
@ MISCREG_ID_AA64AFR1_EL1
@ MISCREG_ID_AA64AFR0_EL1
@ MISCREG_ID_AA64ISAR0_EL1
@ MISCREG_CONTEXTIDR_EL12
@ MISCREG_PMXEVTYPER_PMCCFILTR
@ MISCREG_ID_AA64PFR1_EL1
int unflattenMiscReg(int reg)
static bool lockedWriteHandler(ThreadContext *tc, XC *xc, const RequestPtr &req, Addr cacheBlockMask)
static ExceptionLevel opModeToEL(OperatingMode mode)
constexpr RegClass miscRegClass
const char *const miscRegName[]
RegVal readMPIDR(ArmSystem *arm_sys, ThreadContext *tc)
This helper function is either returing the value of MPIDR_EL1 (by calling getMPIDR),...
static void lockedSnoopHandler(ThreadContext *tc, XC *xc, PacketPtr pkt, Addr cacheBlockMask)
std::vector< struct MiscRegLUTEntry > lookUpMiscReg(NUM_MISCREGS)
constexpr RegClass vecRegClass
constexpr RegClass floatRegClass
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
std::shared_ptr< FaultBase > Fault
std::shared_ptr< Request > RequestPtr
std::ostream CheckpointOut
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
bool FullSystem
The FullSystem variable can be used to determine the current mode of simulation.
constexpr decltype(nullptr) NoFault
@ FloatRegClass
Floating-point register.
constexpr char FloatRegClassName[]
#define UNSERIALIZE_MAPPING(member, names, size)
#define SERIALIZE_MAPPING(member, names, size)