gem5  v21.2.1.1
nativetrace.cc
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40 
41 #include "arch/arm/nativetrace.hh"
42 
43 #include "arch/arm/regs/cc.hh"
44 #include "arch/arm/regs/misc.hh"
45 #include "base/compiler.hh"
46 #include "cpu/thread_context.hh"
47 #include "debug/ExecRegDelta.hh"
48 #include "params/ArmNativeTrace.hh"
49 #include "sim/byteswap.hh"
50 
51 namespace gem5
52 {
53 
54 using namespace ArmISA;
55 
56 namespace Trace {
57 
58 [[maybe_unused]] static const char *regNames[] = {
59  "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
60  "r8", "r9", "r10", "fp", "r12", "sp", "lr", "pc",
61  "cpsr", "f0", "f1", "f2", "f3", "f4", "f5", "f6",
62  "f7", "f8", "f9", "f10", "f11", "f12", "f13", "f14",
63  "f15", "f16", "f17", "f18", "f19", "f20", "f21", "f22",
64  "f23", "f24", "f25", "f26", "f27", "f28", "f29", "f30",
65  "f31", "fpscr"
66 };
67 
68 void
70 {
71  oldState = state[current];
72  current = (current + 1) % 2;
73  newState = state[current];
74 
75  memcpy(newState, oldState, sizeof(state[0]));
76 
77  uint64_t diffVector;
78  parent->read(&diffVector, sizeof(diffVector));
79  diffVector = letoh(diffVector);
80 
81  int changes = 0;
82  for (int i = 0; i < STATE_NUMVALS; i++) {
83  if (diffVector & 0x1) {
84  changed[i] = true;
85  changes++;
86  } else {
87  changed[i] = false;
88  }
89  diffVector >>= 1;
90  }
91 
92  uint64_t values[changes];
93  parent->read(values, sizeof(values));
94  int pos = 0;
95  for (int i = 0; i < STATE_NUMVALS; i++) {
96  if (changed[i]) {
97  newState[i] = letoh(values[pos++]);
98  changed[i] = (newState[i] != oldState[i]);
99  }
100  }
101 }
102 
103 void
105 {
106  oldState = state[current];
107  current = (current + 1) % 2;
108  newState = state[current];
109 
110  // Regular int regs
111  for (int i = 0; i < 15; i++) {
112  newState[i] = tc->readIntReg(i);
113  changed[i] = (oldState[i] != newState[i]);
114  }
115 
116  //R15, aliased with the PC
117  newState[STATE_PC] = tc->pcState().as<ArmISA::PCState>().npc();
118  changed[STATE_PC] = (newState[STATE_PC] != oldState[STATE_PC]);
119 
120  //CPSR
121  CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
122  cpsr.nz = tc->readCCReg(CCREG_NZ);
123  cpsr.c = tc->readCCReg(CCREG_C);
124  cpsr.v = tc->readCCReg(CCREG_V);
125  cpsr.ge = tc->readCCReg(CCREG_GE);
126 
127  newState[STATE_CPSR] = cpsr;
128  changed[STATE_CPSR] = (newState[STATE_CPSR] != oldState[STATE_CPSR]);
129 
130  for (int i = 0; i < NumVecV7ArchRegs; i++) {
131  auto *vec = tc->readVecReg(RegId(VecRegClass,i)).as<uint64_t>();
132  newState[STATE_F0 + 2*i] = vec[0];
133  newState[STATE_F0 + 2*i + 1] = vec[1];
134  }
135  newState[STATE_FPSCR] = tc->readMiscRegNoEffect(MISCREG_FPSCR) |
136  tc->readCCReg(CCREG_FP);
137 }
138 
139 void
141 {
142  ThreadContext *tc = record->getThread();
143  // This area is read only on the target. It can't stop there to tell us
144  // what's going on, so we should skip over anything there also.
145  if (tc->pcState().as<ArmISA::PCState>().npc() > 0xffff0000)
146  return;
147  nState.update(this);
148  mState.update(tc);
149 
150  // If a syscall just happened native trace needs another tick
151  if ((mState.oldState[STATE_PC] == nState.oldState[STATE_PC]) &&
152  (mState.newState[STATE_PC] - 4 == nState.newState[STATE_PC])) {
153  DPRINTF(ExecRegDelta, "Advancing to match PCs after syscall\n");
154  nState.update(this);
155 
156  }
157 
158  bool errorFound = false;
159  // Regular int regs
160  for (int i = 0; i < STATE_NUMVALS; i++) {
161  if (nState.changed[i] || mState.changed[i]) {
162  bool oldMatch = (mState.oldState[i] == nState.oldState[i]);
163  bool newMatch = (mState.newState[i] == nState.newState[i]);
164  if (oldMatch && newMatch) {
165  // The more things change, the more they stay the same.
166  continue;
167  }
168 
169  errorFound = true;
170 
171 #ifndef NDEBUG
172  const char *vergence = " ";
173  if (oldMatch && !newMatch) {
174  vergence = "<>";
175  } else if (!oldMatch && newMatch) {
176  vergence = "><";
177  }
178 
179  if (!nState.changed[i]) {
180  DPRINTF(ExecRegDelta, "%s [%5s] "\
181  "Native: %#010x "\
182  "M5: %#010x => %#010x\n",
183  vergence, regNames[i],
184  nState.newState[i],
185  mState.oldState[i], mState.newState[i]);
186  } else if (!mState.changed[i]) {
187  DPRINTF(ExecRegDelta, "%s [%5s] "\
188  "Native: %#010x => %#010x "\
189  "M5: %#010x \n",
190  vergence, regNames[i],
191  nState.oldState[i], nState.newState[i],
192  mState.newState[i]);
193  } else {
194  DPRINTF(ExecRegDelta, "%s [%5s] "\
195  "Native: %#010x => %#010x "\
196  "M5: %#010x => %#010x\n",
197  vergence, regNames[i],
198  nState.oldState[i], nState.newState[i],
199  mState.oldState[i], mState.newState[i]);
200  }
201 #endif
202  }
203  }
204  if (errorFound) {
205  StaticInstPtr inst = record->getStaticInst();
206  assert(inst);
207  bool ran = true;
208  if (inst->isMicroop()) {
209  ran = false;
210  inst = record->getMacroStaticInst();
211  }
212  assert(inst);
213  record->traceInst(inst, ran);
214 
215  bool pcError = (mState.newState[STATE_PC] !=
216  nState.newState[STATE_PC]);
217  if (stopOnPCError && pcError)
218  panic("Native trace detected an error in control flow!");
219  }
220 }
221 
222 } // namespace Trace
223 } // namespace gem5
gem5::Trace::regNames
static const char * regNames[]
Definition: nativetrace.cc:58
gem5::ArmISA::MISCREG_CPSR
@ MISCREG_CPSR
Definition: misc.hh:61
gem5::ArmISA::CCREG_C
@ CCREG_C
Definition: cc.hh:50
gem5::ThreadContext::readMiscReg
virtual RegVal readMiscReg(RegIndex misc_reg)=0
gem5::StaticInst::isMicroop
bool isMicroop() const
Definition: static_inst.hh:207
nativetrace.hh
gem5::PCStateBase::as
Target & as()
Definition: pcstate.hh:72
gem5::Trace::NativeTrace::read
void read(void *ptr, size_t size)
Definition: nativetrace.hh:104
gem5::ThreadContext::pcState
virtual const PCStateBase & pcState() const =0
gem5::ArmISA::CCREG_NZ
@ CCREG_NZ
Definition: cc.hh:49
gem5::Trace::NativeTrace
Definition: nativetrace.hh:69
gem5::Trace::InstRecord::getStaticInst
StaticInstPtr getStaticInst() const
Definition: insttracer.hh:239
gem5::ArmISA::i
Bitfield< 7 > i
Definition: misc_types.hh:67
cc.hh
gem5::ThreadContext::readCCReg
virtual RegVal readCCReg(RegIndex reg_idx) const =0
gem5::RefCountingPtr< StaticInst >
gem5::letoh
T letoh(T value)
Definition: byteswap.hh:173
gem5::ArmISA::NumVecV7ArchRegs
const int NumVecV7ArchRegs
Definition: vec.hh:76
gem5::ThreadContext::readVecReg
virtual const TheISA::VecRegContainer & readVecReg(const RegId &reg) const =0
gem5::ThreadContext
ThreadContext is the external interface to all thread state for anything outside of the CPU.
Definition: thread_context.hh:94
gem5::GenericISA::PCStateWithNext::npc
Addr npc() const
Definition: pcstate.hh:266
DPRINTF
#define DPRINTF(x,...)
Definition: trace.hh:186
gem5::MipsISA::PCState
GenericISA::DelaySlotPCState< 4 > PCState
Definition: pcstate.hh:40
gem5::Trace::InstRecord::getMacroStaticInst
StaticInstPtr getMacroStaticInst() const
Definition: insttracer.hh:241
gem5::Trace::InstRecord::getThread
ThreadContext * getThread() const
Definition: insttracer.hh:238
compiler.hh
gem5::ThreadContext::readMiscRegNoEffect
virtual RegVal readMiscRegNoEffect(RegIndex misc_reg) const =0
gem5::ThreadContext::readIntReg
virtual RegVal readIntReg(RegIndex reg_idx) const =0
gem5::ArmISA::CCREG_GE
@ CCREG_GE
Definition: cc.hh:52
gem5::Trace::ArmNativeTrace::check
void check(NativeTraceRecord *record)
Definition: nativetrace.cc:140
gem5::ArmISA::CCREG_FP
@ CCREG_FP
Definition: cc.hh:53
gem5::ArmISA::MISCREG_FPSCR
@ MISCREG_FPSCR
Definition: misc.hh:72
gem5::PowerISA::vec
Bitfield< 25 > vec
Definition: misc.hh:108
misc.hh
gem5::Trace::ArmNativeTrace::ThreadState::update
void update(NativeTrace *parent)
Definition: nativetrace.cc:69
gem5::VecRegClass
@ VecRegClass
Vector Register.
Definition: reg_class.hh:61
gem5::Trace::ExeTracerRecord::traceInst
void traceInst(const StaticInstPtr &inst, bool ran)
Definition: exetrace.cc:61
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: tlb.cc:60
gem5::ArmISA::CCREG_V
@ CCREG_V
Definition: cc.hh:51
thread_context.hh
gem5::Trace::NativeTraceRecord
Definition: nativetrace.hh:51
byteswap.hh
gem5::RegId
Register ID: describe an architectural register with its class and index.
Definition: reg_class.hh:113
panic
#define panic(...)
This implements a cprintf based panic() function.
Definition: logging.hh:178

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