gem5  v22.0.0.2
nativetrace.cc
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40 
41 #include "arch/arm/nativetrace.hh"
42 
43 #include "arch/arm/regs/cc.hh"
44 #include "arch/arm/regs/misc.hh"
45 #include "base/compiler.hh"
46 #include "cpu/thread_context.hh"
47 #include "debug/ExecRegDelta.hh"
48 #include "params/ArmNativeTrace.hh"
49 #include "sim/byteswap.hh"
50 
51 namespace gem5
52 {
53 
54 using namespace ArmISA;
55 
56 namespace Trace {
57 
58 [[maybe_unused]] static const char *regNames[] = {
59  "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
60  "r8", "r9", "r10", "fp", "r12", "sp", "lr", "pc",
61  "cpsr", "f0", "f1", "f2", "f3", "f4", "f5", "f6",
62  "f7", "f8", "f9", "f10", "f11", "f12", "f13", "f14",
63  "f15", "f16", "f17", "f18", "f19", "f20", "f21", "f22",
64  "f23", "f24", "f25", "f26", "f27", "f28", "f29", "f30",
65  "f31", "fpscr"
66 };
67 
68 void
70 {
71  oldState = state[current];
72  current = (current + 1) % 2;
73  newState = state[current];
74 
75  memcpy(newState, oldState, sizeof(state[0]));
76 
77  uint64_t diffVector;
78  parent->read(&diffVector, sizeof(diffVector));
79  diffVector = letoh(diffVector);
80 
81  int changes = 0;
82  for (int i = 0; i < STATE_NUMVALS; i++) {
83  if (diffVector & 0x1) {
84  changed[i] = true;
85  changes++;
86  } else {
87  changed[i] = false;
88  }
89  diffVector >>= 1;
90  }
91 
92  uint64_t values[changes];
93  parent->read(values, sizeof(values));
94  int pos = 0;
95  for (int i = 0; i < STATE_NUMVALS; i++) {
96  if (changed[i]) {
97  newState[i] = letoh(values[pos++]);
98  changed[i] = (newState[i] != oldState[i]);
99  }
100  }
101 }
102 
103 void
105 {
106  oldState = state[current];
107  current = (current + 1) % 2;
108  newState = state[current];
109 
110  // Regular int regs
111  for (int i = 0; i < 15; i++) {
112  newState[i] = tc->getReg(RegId(IntRegClass, i));
113  changed[i] = (oldState[i] != newState[i]);
114  }
115 
116  //R15, aliased with the PC
117  newState[STATE_PC] = tc->pcState().as<ArmISA::PCState>().npc();
118  changed[STATE_PC] = (newState[STATE_PC] != oldState[STATE_PC]);
119 
120  //CPSR
121  CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
122  cpsr.nz = tc->getReg(cc_reg::Nz);
123  cpsr.c = tc->getReg(cc_reg::C);
124  cpsr.v = tc->getReg(cc_reg::V);
125  cpsr.ge = tc->getReg(cc_reg::Ge);
126 
127  newState[STATE_CPSR] = cpsr;
128  changed[STATE_CPSR] = (newState[STATE_CPSR] != oldState[STATE_CPSR]);
129 
130  for (int i = 0; i < NumVecV7ArchRegs; i++) {
131  ArmISA::VecRegContainer vec_container;
132  tc->getReg(RegId(VecRegClass, i), &vec_container);
133  auto *vec = vec_container.as<uint64_t>();
134  newState[STATE_F0 + 2*i] = vec[0];
135  newState[STATE_F0 + 2*i + 1] = vec[1];
136  }
137  newState[STATE_FPSCR] = tc->readMiscRegNoEffect(MISCREG_FPSCR) |
138  tc->getReg(cc_reg::Fp);
139 }
140 
141 void
143 {
144  ThreadContext *tc = record->getThread();
145  // This area is read only on the target. It can't stop there to tell us
146  // what's going on, so we should skip over anything there also.
147  if (tc->pcState().as<ArmISA::PCState>().npc() > 0xffff0000)
148  return;
149  nState.update(this);
150  mState.update(tc);
151 
152  // If a syscall just happened native trace needs another tick
153  if ((mState.oldState[STATE_PC] == nState.oldState[STATE_PC]) &&
154  (mState.newState[STATE_PC] - 4 == nState.newState[STATE_PC])) {
155  DPRINTF(ExecRegDelta, "Advancing to match PCs after syscall\n");
156  nState.update(this);
157 
158  }
159 
160  bool errorFound = false;
161  // Regular int regs
162  for (int i = 0; i < STATE_NUMVALS; i++) {
163  if (nState.changed[i] || mState.changed[i]) {
164  bool oldMatch = (mState.oldState[i] == nState.oldState[i]);
165  bool newMatch = (mState.newState[i] == nState.newState[i]);
166  if (oldMatch && newMatch) {
167  // The more things change, the more they stay the same.
168  continue;
169  }
170 
171  errorFound = true;
172 
173 #ifndef NDEBUG
174  const char *vergence = " ";
175  if (oldMatch && !newMatch) {
176  vergence = "<>";
177  } else if (!oldMatch && newMatch) {
178  vergence = "><";
179  }
180 
181  if (!nState.changed[i]) {
182  DPRINTF(ExecRegDelta, "%s [%5s] "\
183  "Native: %#010x "\
184  "M5: %#010x => %#010x\n",
185  vergence, regNames[i],
186  nState.newState[i],
187  mState.oldState[i], mState.newState[i]);
188  } else if (!mState.changed[i]) {
189  DPRINTF(ExecRegDelta, "%s [%5s] "\
190  "Native: %#010x => %#010x "\
191  "M5: %#010x \n",
192  vergence, regNames[i],
193  nState.oldState[i], nState.newState[i],
194  mState.newState[i]);
195  } else {
196  DPRINTF(ExecRegDelta, "%s [%5s] "\
197  "Native: %#010x => %#010x "\
198  "M5: %#010x => %#010x\n",
199  vergence, regNames[i],
200  nState.oldState[i], nState.newState[i],
201  mState.oldState[i], mState.newState[i]);
202  }
203 #endif
204  }
205  }
206  if (errorFound) {
207  StaticInstPtr inst = record->getStaticInst();
208  assert(inst);
209  bool ran = true;
210  if (inst->isMicroop()) {
211  ran = false;
212  inst = record->getMacroStaticInst();
213  }
214  assert(inst);
215  record->traceInst(inst, ran);
216 
217  bool pcError = (mState.newState[STATE_PC] !=
218  nState.newState[STATE_PC]);
219  if (stopOnPCError && pcError)
220  panic("Native trace detected an error in control flow!");
221  }
222 }
223 
224 } // namespace Trace
225 } // namespace gem5
gem5::Trace::regNames
static const char * regNames[]
Definition: nativetrace.cc:58
gem5::ArmISA::MISCREG_CPSR
@ MISCREG_CPSR
Definition: misc.hh:61
gem5::ThreadContext::readMiscReg
virtual RegVal readMiscReg(RegIndex misc_reg)=0
gem5::StaticInst::isMicroop
bool isMicroop() const
Definition: static_inst.hh:186
nativetrace.hh
gem5::ThreadContext::getReg
virtual RegVal getReg(const RegId &reg) const
Definition: thread_context.cc:171
gem5::PCStateBase::as
Target & as()
Definition: pcstate.hh:72
gem5::Trace::NativeTrace::read
void read(void *ptr, size_t size)
Definition: nativetrace.hh:104
gem5::ThreadContext::pcState
virtual const PCStateBase & pcState() const =0
gem5::Trace::NativeTrace
Definition: nativetrace.hh:69
gem5::ArmISA::cc_reg::Fp
constexpr RegId Fp(CCRegClass, _FpIdx)
gem5::Trace::InstRecord::getStaticInst
StaticInstPtr getStaticInst() const
Definition: insttracer.hh:273
gem5::ArmISA::i
Bitfield< 7 > i
Definition: misc_types.hh:67
cc.hh
gem5::RefCountingPtr< StaticInst >
gem5::letoh
T letoh(T value)
Definition: byteswap.hh:173
gem5::ArmISA::cc_reg::Nz
constexpr RegId Nz(CCRegClass, _NzIdx)
gem5::ArmISA::NumVecV7ArchRegs
const int NumVecV7ArchRegs
Definition: vec.hh:76
gem5::VecRegContainer
Vector Register Abstraction This generic class is the model in a particularization of MVC,...
Definition: vec_reg.hh:123
gem5::ThreadContext
ThreadContext is the external interface to all thread state for anything outside of the CPU.
Definition: thread_context.hh:94
gem5::GenericISA::PCStateWithNext::npc
Addr npc() const
Definition: pcstate.hh:266
gem5::VecRegContainer::as
VecElem * as()
View interposers.
Definition: vec_reg.hh:189
gem5::ArmISA::cc_reg::V
constexpr RegId V(CCRegClass, _VIdx)
DPRINTF
#define DPRINTF(x,...)
Definition: trace.hh:186
gem5::MipsISA::PCState
GenericISA::DelaySlotPCState< 4 > PCState
Definition: pcstate.hh:40
gem5::Trace::InstRecord::getMacroStaticInst
StaticInstPtr getMacroStaticInst() const
Definition: insttracer.hh:275
gem5::Trace::InstRecord::getThread
ThreadContext * getThread() const
Definition: insttracer.hh:272
compiler.hh
gem5::ThreadContext::readMiscRegNoEffect
virtual RegVal readMiscRegNoEffect(RegIndex misc_reg) const =0
gem5::ArmISA::cc_reg::C
constexpr RegId C(CCRegClass, _CIdx)
gem5::ArmISA::cc_reg::Ge
constexpr RegId Ge(CCRegClass, _GeIdx)
gem5::Trace::ArmNativeTrace::check
void check(NativeTraceRecord *record)
Definition: nativetrace.cc:142
gem5::IntRegClass
@ IntRegClass
Integer register.
Definition: reg_class.hh:58
state
atomic_var_t state
Definition: helpers.cc:188
gem5::ArmISA::MISCREG_FPSCR
@ MISCREG_FPSCR
Definition: misc.hh:72
gem5::PowerISA::vec
Bitfield< 25 > vec
Definition: misc.hh:108
misc.hh
gem5::Trace::ArmNativeTrace::ThreadState::update
void update(NativeTrace *parent)
Definition: nativetrace.cc:69
gem5::VecRegClass
@ VecRegClass
Vector Register.
Definition: reg_class.hh:61
gem5::Trace::ExeTracerRecord::traceInst
void traceInst(const StaticInstPtr &inst, bool ran)
Definition: exetrace.cc:61
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: gpu_translation_state.hh:37
thread_context.hh
gem5::Trace::NativeTraceRecord
Definition: nativetrace.hh:51
byteswap.hh
gem5::RegId
Register ID: describe an architectural register with its class and index.
Definition: reg_class.hh:126
panic
#define panic(...)
This implements a cprintf based panic() function.
Definition: logging.hh:178

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