nvm_interface.hh

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/*
 * Copyright (c) 2012-2020 ARM Limited
 * All rights reserved
 *
 * The license below extends only to copyright in the software and shall
 * not be construed as granting a license to any other intellectual
 * property including but not limited to intellectual property relating
 * to a hardware implementation of the functionality of the software
 * licensed hereunder.  You may use the software subject to the license
 * terms below provided that you ensure that this notice is replicated
 * unmodified and in its entirety in all distributions of the software,
 * modified or unmodified, in source code or in binary form.
 *
 * Copyright (c) 2013 Amin Farmahini-Farahani
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions are
 * met: redistributions of source code must retain the above copyright
 * notice, this list of conditions and the following disclaimer;
 * redistributions in binary form must reproduce the above copyright
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 * documentation and/or other materials provided with the distribution;
 * neither the name of the copyright holders nor the names of its
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 * this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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 */
 
#ifndef __NVM_INTERFACE_HH__
#define __NVM_INTERFACE_HH__
 
#include "mem/mem_interface.hh"
#include "params/NVMInterface.hh"
 
namespace gem5
{
 
namespace memory
{
 
class NVMInterface : public MemInterface
{
  private:
    class Rank : public EventManager
    {
      public:
 
        uint8_t rank;
 
        std::vector<Bank> banks;
 
        Rank(const NVMInterfaceParams &_p, int _rank,
             NVMInterface& _nvm);
    };
 
    const uint32_t maxPendingWrites;
    const uint32_t maxPendingReads;
    const bool twoCycleRdWr;
 
    const Tick tREAD;
    const Tick tWRITE;
    const Tick tSEND;
 
    struct NVMStats : public statistics::Group
    {
        NVMStats(NVMInterface &nvm);
 
        void regStats() override;
 
        NVMInterface &nvm;
 
        statistics::Scalar readBursts;
        statistics::Scalar writeBursts;
 
        statistics::Vector perBankRdBursts;
        statistics::Vector perBankWrBursts;
 
        // Latencies summed over all requests
        statistics::Scalar totQLat;
        statistics::Scalar totBusLat;
        statistics::Scalar totMemAccLat;
 
        // Average latencies per request
        statistics::Formula avgQLat;
        statistics::Formula avgBusLat;
        statistics::Formula avgMemAccLat;
 
        statistics::Scalar nvmBytesRead;
        statistics::Scalar nvmBytesWritten;
 
        // Average bandwidth
        statistics::Formula avgRdBW;
        statistics::Formula avgWrBW;
        statistics::Formula peakBW;
        statistics::Formula busUtil;
        statistics::Formula busUtilRead;
        statistics::Formula busUtilWrite;
 
        statistics::Histogram pendingReads;
        statistics::Histogram pendingWrites;
        statistics::Histogram bytesPerBank;
    };
    NVMStats stats;
 
    void processWriteRespondEvent();
    EventFunctionWrapper writeRespondEvent;
 
    void processReadReadyEvent();
    EventFunctionWrapper readReadyEvent;
 
    std::vector<Rank*> ranks;
 
    std::list<Tick> writeRespQueue;
 
    std::deque<Tick> readReadyQueue;
 
    bool writeRespQueueEmpty() const { return writeRespQueue.empty(); }
 
    Tick nextReadAt;
 
    // keep track of reads that have issued for which data is either
    // not yet ready or has not yet been transferred to the ctrl
    uint16_t numPendingReads;
    uint16_t numReadDataReady;
 
  public:
    // keep track of the number of reads that have yet to be issued
    uint16_t numReadsToIssue;
 
    void init() override;
 
    void setupRank(const uint8_t rank, const bool is_read) override;
 
    MemPacket* decodePacket(const PacketPtr pkt, Addr pkt_addr,
                           unsigned int size, bool is_read,
                           uint8_t pseudo_channel = 0) override;
 
    bool allRanksDrained() const override { return writeRespQueueEmpty(); }
 
    /*
     * @return time to offset next command
     */
    Tick commandOffset() const override { return tBURST; }
 
    bool burstReady(MemPacket* pkt) const override;
 
    bool isBusy(bool read_queue_empty, bool all_writes_nvm) override;
    std::pair<MemPacketQueue::iterator, Tick>
    chooseNextFRFCFS(MemPacketQueue& queue, Tick min_col_at) const override;
 
    void addRankToRankDelay(Tick cmd_at) override;
 
    void respondEvent(uint8_t rank) override { };
 
    void checkRefreshState(uint8_t rank) override { };
 
    void chooseRead(MemPacketQueue& queue) override;
 
    /*
     * Function to calulate unloaded access latency
     */
    Tick accessLatency() const override { return (tREAD + tSEND); }
 
    bool
    writeRespQueueFull() const override
    {
        return writeRespQueue.size() == maxPendingWrites;
    }
 
    bool
    readsWaitingToIssue() const override
    {
        return ((numReadsToIssue != 0) &&
                (numPendingReads < maxPendingReads));
    }
 
    std::pair<Tick, Tick>
    doBurstAccess(MemPacket* pkt, Tick next_burst_at,
                  const std::vector<MemPacketQueue>& queue) override;
 
    void drainRanks() override { }
    void suspend() override { }
    void startup() override { }
 
    NVMInterface(const NVMInterfaceParams &_p);
};
 
} // namespace memory
} // namespace gem5
 
#endif //__NVM_INTERFACE_HH__