gem5  v22.1.0.0
decoder.hh
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29 
30 #ifndef __ARCH_POWER_DECODER_HH__
31 #define __ARCH_POWER_DECODER_HH__
32 
34 #include "arch/generic/decoder.hh"
35 #include "arch/power/types.hh"
36 #include "cpu/static_inst.hh"
37 #include "debug/Decode.hh"
38 #include "params/PowerDecoder.hh"
39 
40 namespace gem5
41 {
42 
43 class BaseISA;
44 
45 namespace PowerISA
46 {
47 
48 class Decoder : public InstDecoder
49 {
50  protected:
51  // The extended machine instruction being generated
53 
54  public:
55  Decoder(const PowerDecoderParams &p) : InstDecoder(p, &emi) {}
56 
57  // Use this to give data to the predecoder. This should be used
58  // when there is control flow.
59  void
60  moreBytes(const PCStateBase &pc, Addr fetchPC) override
61  {
62  emi = gtoh(emi, pc.as<PCState>().byteOrder());
63  instDone = true;
64  }
65 
66  protected:
70 
72 
78  {
79  StaticInstPtr si = defaultCache.decode(this, mach_inst, addr);
80  DPRINTF(Decode, "Decode: Decoded %s instruction: %#x\n",
81  si->getName(), mach_inst);
82  return si;
83  }
84 
85  public:
87  decode(PCStateBase &next_pc) override
88  {
89  if (!instDone)
90  return NULL;
91  instDone = false;
92  return decode(emi, next_pc.instAddr());
93  }
94 };
95 
96 } // namespace PowerISA
97 } // namespace gem5
98 
99 #endif // __ARCH_POWER_DECODER_HH__
#define DPRINTF(x,...)
Definition: trace.hh:186
Addr instAddr() const
Returns the memory address of the instruction this PC points to.
Definition: pcstate.hh:107
Decoder(const PowerDecoderParams &p)
Definition: decoder.hh:55
StaticInstPtr decodeInst(ExtMachInst mach_inst)
StaticInstPtr decode(ExtMachInst mach_inst, Addr addr)
Decode a machine instruction.
Definition: decoder.hh:77
static GenericISA::BasicDecodeCache< Decoder, ExtMachInst > defaultCache
A cache of decoded instruction objects.
Definition: decoder.hh:68
void moreBytes(const PCStateBase &pc, Addr fetchPC) override
Feed data to the decoder.
Definition: decoder.hh:60
StaticInstPtr decode(PCStateBase &next_pc) override
Decode an instruction or fetch it from the code cache.
Definition: decoder.hh:87
ByteOrder byteOrder() const
Definition: pcstate.hh:67
Bitfield< 4 > pc
Bitfield< 15, 0 > si
Definition: types.hh:61
Bitfield< 54 > p
Definition: pagetable.hh:70
Bitfield< 3 > addr
Definition: types.hh:84
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
T gtoh(T value, ByteOrder guest_byte_order)
Definition: byteswap.hh:194

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