gem5  v21.1.0.2
decoder.hh
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29 
30 #ifndef __ARCH_POWER_DECODER_HH__
31 #define __ARCH_POWER_DECODER_HH__
32 
34 #include "arch/generic/decoder.hh"
35 #include "arch/power/types.hh"
36 #include "cpu/static_inst.hh"
37 #include "debug/Decode.hh"
38 
39 namespace gem5
40 {
41 
42 namespace PowerISA
43 {
44 
45 class ISA;
46 class Decoder : public InstDecoder
47 {
48  protected:
49  // The extended machine instruction being generated
51  bool instDone;
52 
53  public:
54  Decoder(ISA* isa=nullptr) : InstDecoder(&emi), instDone(false) {}
55 
56  void
58  {
59  }
60 
61  void
63  {
64  instDone = false;
65  }
66 
67  // Use this to give data to the predecoder. This should be used
68  // when there is control flow.
69  void
70  moreBytes(const PCState &pc, Addr fetchPC)
71  {
72  emi = gtoh(emi, pc.byteOrder());
73  instDone = true;
74  }
75 
76  bool
78  {
79  return true;
80  }
81 
82  bool
84  {
85  return instDone;
86  }
87 
88  void takeOverFrom(Decoder *old) {}
89 
90  protected:
94 
96 
102  {
103  StaticInstPtr si = defaultCache.decode(this, mach_inst, addr);
104  DPRINTF(Decode, "Decode: Decoded %s instruction: %#x\n",
105  si->getName(), mach_inst);
106  return si;
107  }
108 
109  public:
112  {
113  if (!instDone)
114  return NULL;
115  instDone = false;
116  return decode(emi, nextPC.instAddr());
117  }
118 };
119 
120 } // namespace PowerISA
121 } // namespace gem5
122 
123 #endif // __ARCH_POWER_DECODER_HH__
gem5::PowerISA::Decoder::instDone
bool instDone
Definition: decoder.hh:51
gem5::PowerISA::Decoder
Definition: decoder.hh:46
gem5::PowerISA::Decoder::process
void process()
Definition: decoder.hh:57
decode_cache.hh
gem5::PowerISA::Decoder::takeOverFrom
void takeOverFrom(Decoder *old)
Definition: decoder.hh:88
gem5::GenericISA::BasicDecodeCache
Definition: decode_cache.hh:43
gem5::PowerISA::Decoder::needMoreBytes
bool needMoreBytes()
Definition: decoder.hh:77
gem5::PowerISA::PCState
Definition: pcstate.hh:42
gem5::PowerISA::Decoder::reset
void reset()
Definition: decoder.hh:62
gem5::PowerISA::Decoder::decode
StaticInstPtr decode(ExtMachInst mach_inst, Addr addr)
Decode a machine instruction.
Definition: decoder.hh:101
gem5::PowerISA::Decoder::decode
StaticInstPtr decode(PowerISA::PCState &nextPC)
Definition: decoder.hh:111
gem5::RefCountingPtr< StaticInst >
gem5::PowerISA::Decoder::defaultCache
static GenericISA::BasicDecodeCache< Decoder, ExtMachInst > defaultCache
A cache of decoded instruction objects.
Definition: decoder.hh:92
decoder.hh
gem5::PowerISA::Decoder::Decoder
Decoder(ISA *isa=nullptr)
Definition: decoder.hh:54
gem5::InstDecoder
Definition: decoder.hh:39
DPRINTF
#define DPRINTF(x,...)
Definition: trace.hh:186
gem5::gtoh
T gtoh(T value, ByteOrder guest_byte_order)
Definition: byteswap.hh:194
gem5::PowerISA::Decoder::instReady
bool instReady()
Definition: decoder.hh:83
static_inst.hh
gem5::PowerISA::si
Bitfield< 15, 0 > si
Definition: types.hh:61
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::PowerISA::Decoder::emi
ExtMachInst emi
Definition: decoder.hh:50
gem5::X86ISA::ExtMachInst
Definition: types.hh:206
gem5::MipsISA::pc
Bitfield< 4 > pc
Definition: pra_constants.hh:243
gem5::PowerISA::ISA
Definition: isa.hh:52
gem5::GenericISA::PCStateBase::instAddr
Addr instAddr() const
Returns the memory address the bytes of this instruction came from.
Definition: types.hh:73
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40
gem5::PowerISA::Decoder::moreBytes
void moreBytes(const PCState &pc, Addr fetchPC)
Definition: decoder.hh:70
types.hh
gem5::X86ISA::addr
Bitfield< 3 > addr
Definition: types.hh:84
gem5::PowerISA::Decoder::decodeInst
StaticInstPtr decodeInst(ExtMachInst mach_inst)

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