gem5  v22.0.0.2
decoder.hh
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29 
30 #ifndef __ARCH_POWER_DECODER_HH__
31 #define __ARCH_POWER_DECODER_HH__
32 
34 #include "arch/generic/decoder.hh"
35 #include "arch/power/types.hh"
36 #include "cpu/static_inst.hh"
37 #include "debug/Decode.hh"
38 #include "params/PowerDecoder.hh"
39 
40 namespace gem5
41 {
42 
43 namespace PowerISA
44 {
45 
46 class ISA;
47 class Decoder : public InstDecoder
48 {
49  protected:
50  // The extended machine instruction being generated
52 
53  public:
54  Decoder(const PowerDecoderParams &p) : InstDecoder(p, &emi) {}
55 
56  // Use this to give data to the predecoder. This should be used
57  // when there is control flow.
58  void
59  moreBytes(const PCStateBase &pc, Addr fetchPC) override
60  {
61  emi = gtoh(emi, pc.as<PCState>().byteOrder());
62  instDone = true;
63  }
64 
65  protected:
69 
71 
77  {
78  StaticInstPtr si = defaultCache.decode(this, mach_inst, addr);
79  DPRINTF(Decode, "Decode: Decoded %s instruction: %#x\n",
80  si->getName(), mach_inst);
81  return si;
82  }
83 
84  public:
86  decode(PCStateBase &next_pc) override
87  {
88  if (!instDone)
89  return NULL;
90  instDone = false;
91  return decode(emi, next_pc.instAddr());
92  }
93 };
94 
95 } // namespace PowerISA
96 } // namespace gem5
97 
98 #endif // __ARCH_POWER_DECODER_HH__
gem5::PCStateBase::instAddr
Addr instAddr() const
Returns the memory address of the instruction this PC points to.
Definition: pcstate.hh:107
gem5::PowerISA::Decoder
Definition: decoder.hh:47
decode_cache.hh
gem5::GenericISA::BasicDecodeCache
Definition: decode_cache.hh:43
gem5::PowerISA::PCState
Definition: pcstate.hh:42
gem5::PowerISA::Decoder::decode
StaticInstPtr decode(ExtMachInst mach_inst, Addr addr)
Decode a machine instruction.
Definition: decoder.hh:76
gem5::RefCountingPtr< StaticInst >
gem5::PowerISA::Decoder::defaultCache
static GenericISA::BasicDecodeCache< Decoder, ExtMachInst > defaultCache
A cache of decoded instruction objects.
Definition: decoder.hh:67
decoder.hh
gem5::VegaISA::p
Bitfield< 54 > p
Definition: pagetable.hh:70
gem5::InstDecoder
Definition: decoder.hh:42
DPRINTF
#define DPRINTF(x,...)
Definition: trace.hh:186
gem5::gtoh
T gtoh(T value, ByteOrder guest_byte_order)
Definition: byteswap.hh:194
static_inst.hh
gem5::PowerISA::si
Bitfield< 15, 0 > si
Definition: types.hh:61
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::PowerISA::Decoder::emi
ExtMachInst emi
Definition: decoder.hh:51
gem5::X86ISA::ExtMachInst
Definition: types.hh:212
gem5::PowerISA::Decoder::moreBytes
void moreBytes(const PCStateBase &pc, Addr fetchPC) override
Feed data to the decoder.
Definition: decoder.hh:59
gem5::InstDecoder::instDone
bool instDone
Definition: decoder.hh:49
gem5::MipsISA::pc
Bitfield< 4 > pc
Definition: pra_constants.hh:243
gem5::PowerISA::PCState::byteOrder
ByteOrder byteOrder() const
Definition: pcstate.hh:67
gem5::PowerISA::Decoder::Decoder
Decoder(const PowerDecoderParams &p)
Definition: decoder.hh:54
gem5::PCStateBase
Definition: pcstate.hh:57
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: gpu_translation_state.hh:37
types.hh
gem5::PowerISA::Decoder::decode
StaticInstPtr decode(PCStateBase &next_pc) override
Decode an instruction or fetch it from the code cache.
Definition: decoder.hh:86
gem5::X86ISA::addr
Bitfield< 3 > addr
Definition: types.hh:84
gem5::PowerISA::Decoder::decodeInst
StaticInstPtr decodeInst(ExtMachInst mach_inst)

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