gem5 v24.0.0.0
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decoder.hh
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1/*
2 * Copyright (c) 2012 Google
3 * Copyright (c) 2021 IBM Corporation
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met: redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer;
10 * redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution;
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14 * contributors may be used to endorse or promote products derived from
15 * this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
20 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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22 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
23 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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27 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 */
29
30#ifndef __ARCH_POWER_DECODER_HH__
31#define __ARCH_POWER_DECODER_HH__
32
35#include "arch/power/types.hh"
36#include "cpu/static_inst.hh"
37#include "debug/Decode.hh"
38#include "params/PowerDecoder.hh"
39
40namespace gem5
41{
42
43class BaseISA;
44
45namespace PowerISA
46{
47
48class Decoder : public InstDecoder
49{
50 protected:
51 // The extended machine instruction being generated
53
54 public:
55 Decoder(const PowerDecoderParams &p) : InstDecoder(p, &emi) {}
56
57 // Use this to give data to the predecoder. This should be used
58 // when there is control flow.
59 void
60 moreBytes(const PCStateBase &pc, Addr fetchPC) override
61 {
62 emi = gtoh(emi, pc.as<PCState>().byteOrder());
63 instDone = true;
64 }
65
66 protected:
70
72
78 {
79 StaticInstPtr si = defaultCache.decode(this, mach_inst, addr);
80 DPRINTF(Decode, "Decode: Decoded %s instruction: %#x\n",
81 si->getName(), mach_inst);
82 return si;
83 }
84
85 public:
87 decode(PCStateBase &next_pc) override
88 {
89 if (!instDone)
90 return NULL;
91 instDone = false;
92 return decode(emi, next_pc.instAddr());
93 }
94};
95
96} // namespace PowerISA
97} // namespace gem5
98
99#endif // __ARCH_POWER_DECODER_HH__
#define DPRINTF(x,...)
Definition trace.hh:210
Addr instAddr() const
Returns the memory address of the instruction this PC points to.
Definition pcstate.hh:108
Decoder(const PowerDecoderParams &p)
Definition decoder.hh:55
StaticInstPtr decodeInst(ExtMachInst mach_inst)
StaticInstPtr decode(ExtMachInst mach_inst, Addr addr)
Decode a machine instruction.
Definition decoder.hh:77
static GenericISA::BasicDecodeCache< Decoder, ExtMachInst > defaultCache
A cache of decoded instruction objects.
Definition decoder.hh:68
void moreBytes(const PCStateBase &pc, Addr fetchPC) override
Feed data to the decoder.
Definition decoder.hh:60
StaticInstPtr decode(PCStateBase &next_pc) override
Decode an instruction or fetch it from the code cache.
Definition decoder.hh:87
ByteOrder byteOrder() const
Definition pcstate.hh:67
Bitfield< 4 > pc
Bitfield< 0 > p
Bitfield< 15, 0 > si
Definition types.hh:61
Bitfield< 3 > addr
Definition types.hh:84
Copyright (c) 2024 - Pranith Kumar Copyright (c) 2020 Inria All rights reserved.
Definition binary32.hh:36
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition types.hh:147
T gtoh(T value, ByteOrder guest_byte_order)
Definition byteswap.hh:194

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