gem5  v22.0.0.2
tlb.hh
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31 
32 #ifndef __ARCH_POWER_TLB_HH__
33 #define __ARCH_POWER_TLB_HH__
34 
35 #include <map>
36 
37 #include "arch/generic/tlb.hh"
38 #include "arch/power/pagetable.hh"
39 #include "base/statistics.hh"
40 #include "mem/request.hh"
41 #include "params/PowerTLB.hh"
42 
43 namespace gem5
44 {
45 
46 class ThreadContext;
47 
48 namespace PowerISA {
49 
50 // This is copied from the ARM ISA and has not been checked against the
51 // Power at all.
52 struct TlbEntry
53 {
55 
57  {
58  }
59 
60  TlbEntry(Addr asn, Addr vaddr, Addr paddr,
61  bool uncacheable, bool read_only)
62  : _pageStart(paddr)
63  {
64  if (uncacheable || read_only)
65  warn("Power TlbEntry does not support uncacheable"
66  " or read-only mappings\n");
67  }
68 
69  void
70  updateVaddr(Addr new_vaddr)
71  {
72  panic("unimplemented");
73  }
74 
75  Addr
77  {
78  return _pageStart;
79  }
80 
81  void
83  {
85  }
86 
87  void
89  {
91  }
92 };
93 
94 class TLB : public BaseTLB
95 {
96  protected:
97  typedef std::multimap<Addr, int> PageTable;
98  PageTable lookupTable; // Quick lookup into page table
99 
100  PowerISA::PTE *table; // the Page Table
101  int size; // TLB Size
102  int nlu; // not last used entry (for replacement)
103 
104  void
106  {
107  if (++nlu >= size) {
108  nlu = 0;
109  }
110  }
111 
112  PowerISA::PTE *lookup(Addr vpn, uint8_t asn) const;
113 
114  public:
115  typedef PowerTLBParams Params;
116  TLB(const Params &p);
117  virtual ~TLB();
118 
119  void takeOverFrom(BaseTLB *otlb) override {}
120 
121  int probeEntry(Addr vpn,uint8_t) const;
122  PowerISA::PTE *getEntry(unsigned) const;
123 
125 
126  int
127  getsize() const
128  {
129  return size;
130  }
131 
132  PowerISA::PTE &index(bool advance = true);
133  void insert(Addr vaddr, PowerISA::PTE &pte);
134  void insertAt(PowerISA::PTE &pte, unsigned Index, int _smallPages);
135  void flushAll() override;
136 
137  void
138  demapPage(Addr vaddr, uint64_t asn) override
139  {
140  panic("demapPage unimplemented.\n");
141  }
142 
143  // static helper functions... really
144  static bool validVirtualAddress(Addr vaddr);
145  static Fault checkCacheability(const RequestPtr &req);
146  Fault translateInst(const RequestPtr &req, ThreadContext *tc);
147  Fault translateData(const RequestPtr &req, ThreadContext *tc, bool write);
149  const RequestPtr &req, ThreadContext *tc, BaseMMU::Mode mode) override;
150  void translateTiming(
151  const RequestPtr &req, ThreadContext *tc,
152  BaseMMU::Translation *translation, BaseMMU::Mode mode) override;
154  const RequestPtr &req, ThreadContext *tc, BaseMMU::Mode mode) override;
156  const RequestPtr &req,
157  ThreadContext *tc, BaseMMU::Mode mode) const override;
158 
159  // Checkpointing
160  void serialize(CheckpointOut &cp) const override;
161  void unserialize(CheckpointIn &cp) override;
162 };
163 
164 } // namespace PowerISA
165 } // namespace gem5
166 
167 #endif // __ARCH_POWER_TLB_HH__
gem5::PowerISA::TLB::index
PowerISA::PTE & index(bool advance=true)
warn
#define warn(...)
Definition: logging.hh:246
UNSERIALIZE_SCALAR
#define UNSERIALIZE_SCALAR(scalar)
Definition: serialize.hh:575
gem5::PowerISA::TLB::probeEntry
int probeEntry(Addr vpn, uint8_t) const
gem5::BaseMMU::Mode
Mode
Definition: mmu.hh:56
gem5::PowerISA::TLB::lookupTable
PageTable lookupTable
Definition: tlb.hh:98
gem5::CheckpointIn
Definition: serialize.hh:68
gem5::PowerISA::TLB::insert
void insert(Addr vaddr, PowerISA::PTE &pte)
tlb.hh
gem5::PowerISA::TlbEntry::TlbEntry
TlbEntry()
Definition: tlb.hh:56
gem5::PowerISA::TlbEntry::unserialize
void unserialize(CheckpointIn &cp)
Definition: tlb.hh:88
gem5::PowerISA::TLB::takeOverFrom
void takeOverFrom(BaseTLB *otlb) override
Take over from an old tlb context.
Definition: tlb.hh:119
gem5::PowerISA::TLB::validVirtualAddress
static bool validVirtualAddress(Addr vaddr)
gem5::PowerISA::TlbEntry::pageStart
Addr pageStart()
Definition: tlb.hh:76
gem5::PowerISA::TLB::unserialize
void unserialize(CheckpointIn &cp) override
Unserialize an object.
gem5::PowerISA::TlbEntry::updateVaddr
void updateVaddr(Addr new_vaddr)
Definition: tlb.hh:70
request.hh
pagetable.hh
gem5::PowerISA::TLB::smallPages
int smallPages
Definition: tlb.hh:124
gem5::PowerISA::TlbEntry::serialize
void serialize(CheckpointOut &cp) const
Definition: tlb.hh:82
gem5::PowerISA::TLB::flushAll
void flushAll() override
Remove all entries from the TLB.
gem5::PowerISA::TLB::PageTable
std::multimap< Addr, int > PageTable
Definition: tlb.hh:97
gem5::PowerISA::TlbEntry::TlbEntry
TlbEntry(Addr asn, Addr vaddr, Addr paddr, bool uncacheable, bool read_only)
Definition: tlb.hh:60
gem5::ThreadContext
ThreadContext is the external interface to all thread state for anything outside of the CPU.
Definition: thread_context.hh:94
gem5::PowerISA::TLB::lookup
PowerISA::PTE * lookup(Addr vpn, uint8_t asn) const
Definition: tlb.cc:73
gem5::Fault
std::shared_ptr< FaultBase > Fault
Definition: types.hh:248
gem5::VegaISA::p
Bitfield< 54 > p
Definition: pagetable.hh:70
gem5::PowerISA::TLB::finalizePhysical
Fault finalizePhysical(const RequestPtr &req, ThreadContext *tc, BaseMMU::Mode mode) const override
Do post-translation physical address finalization.
statistics.hh
gem5::RequestPtr
std::shared_ptr< Request > RequestPtr
Definition: request.hh:92
gem5::PowerISA::TLB::serialize
void serialize(CheckpointOut &cp) const override
Serialize an object.
gem5::BaseTLB
Definition: tlb.hh:58
gem5::PowerISA::TlbEntry
Definition: tlb.hh:52
gem5::PowerISA::TLB::getsize
int getsize() const
Definition: tlb.hh:127
gem5::PowerISA::TLB
Definition: tlb.hh:94
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::PowerISA::TLB::getEntry
PowerISA::PTE * getEntry(unsigned) const
SERIALIZE_SCALAR
#define SERIALIZE_SCALAR(scalar)
Definition: serialize.hh:568
gem5::PowerISA::TLB::insertAt
void insertAt(PowerISA::PTE &pte, unsigned Index, int _smallPages)
Definition: tlb.cc:154
gem5::PowerISA::TLB::nextnlu
void nextnlu()
Definition: tlb.hh:105
gem5::PowerISA::TLB::size
int size
Definition: tlb.hh:101
gem5::PowerISA::TLB::TLB
TLB(const Params &p)
gem5::PowerISA::TLB::demapPage
void demapPage(Addr vaddr, uint64_t asn) override
Definition: tlb.hh:138
gem5::BaseMMU::Translation
Definition: mmu.hh:58
gem5::PowerISA::TLB::translateTiming
void translateTiming(const RequestPtr &req, ThreadContext *tc, BaseMMU::Translation *translation, BaseMMU::Mode mode) override
gem5::PowerISA::TLB::translateInst
Fault translateInst(const RequestPtr &req, ThreadContext *tc)
gem5::PowerISA::TLB::table
PowerISA::PTE * table
Definition: tlb.hh:100
gem5::PowerISA::TLB::checkCacheability
static Fault checkCacheability(const RequestPtr &req)
Definition: tlb.cc:139
gem5::PowerISA::TLB::translateData
Fault translateData(const RequestPtr &req, ThreadContext *tc, bool write)
gem5::PowerISA::TlbEntry::_pageStart
Addr _pageStart
Definition: tlb.hh:54
gem5::CheckpointOut
std::ostream CheckpointOut
Definition: serialize.hh:66
gem5::PowerISA::PTE
Definition: pagetable.hh:45
gem5::PowerISA::TLB::nlu
int nlu
Definition: tlb.hh:102
gem5::MipsISA::vaddr
vaddr
Definition: pra_constants.hh:278
gem5::PowerISA::TLB::translateAtomic
Fault translateAtomic(const RequestPtr &req, ThreadContext *tc, BaseMMU::Mode mode) override
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: gpu_translation_state.hh:37
gem5::PowerISA::TLB::translateFunctional
Fault translateFunctional(const RequestPtr &req, ThreadContext *tc, BaseMMU::Mode mode) override
gem5::PowerISA::TLB::Params
PowerTLBParams Params
Definition: tlb.hh:115
gem5::PowerISA::TLB::~TLB
virtual ~TLB()
panic
#define panic(...)
This implements a cprintf based panic() function.
Definition: logging.hh:178
gem5::ArmISA::mode
Bitfield< 4, 0 > mode
Definition: misc_types.hh:74

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