gem5  v21.1.0.2
tlb.cc
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1 /*
2  * Copyright (c) 2001-2005 The Regents of The University of Michigan
3  * Copyright (c) 2007 MIPS Technologies, Inc.
4  * All rights reserved.
5  *
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29 
30 #include "arch/mips/tlb.hh"
31 
32 #include <string>
33 #include <vector>
34 
35 #include "arch/mips/faults.hh"
36 #include "arch/mips/pagetable.hh"
38 #include "arch/mips/utility.hh"
39 #include "base/inifile.hh"
40 #include "base/str.hh"
41 #include "base/trace.hh"
42 #include "cpu/thread_context.hh"
43 #include "debug/MipsPRA.hh"
44 #include "debug/TLB.hh"
45 #include "mem/page_table.hh"
46 #include "params/MipsTLB.hh"
47 #include "sim/process.hh"
48 
49 namespace gem5
50 {
51 
52 using namespace MipsISA;
53 
55 //
56 // MIPS TLB
57 //
58 
59 TLB::TLB(const Params &p) : BaseTLB(p), size(p.size), nlu(0)
60 {
61  table = new PTE[size];
62  memset(table, 0, sizeof(PTE[size]));
63  smallPages = 0;
64 }
65 
66 TLB::~TLB()
67 {
68  delete [] table;
69 }
70 
71 // look up an entry in the TLB
72 MipsISA::PTE *
73 TLB::lookup(Addr vpn, uint8_t asn) const
74 {
75  // assume not found...
76  PTE *retval = NULL;
77  PageTable::const_iterator i = lookupTable.find(vpn);
78  if (i != lookupTable.end()) {
79  while (i->first == vpn) {
80  int index = i->second;
81  PTE *pte = &table[index];
82 
83  /* 1KB TLB Lookup code - from MIPS ARM Volume III - Rev. 2.50 */
84  Addr Mask = pte->Mask;
85  Addr InvMask = ~Mask;
86  Addr VPN = pte->VPN;
87  if (((vpn & InvMask) == (VPN & InvMask)) &&
88  (pte->G || (asn == pte->asid))) {
89  // We have a VPN + ASID Match
90  retval = pte;
91  break;
92  }
93  ++i;
94  }
95  }
96 
97  DPRINTF(TLB, "lookup %#x, asn %#x -> %s ppn %#x\n", vpn, (int)asn,
98  retval ? "hit" : "miss", retval ? retval->PFN1 : 0);
99  return retval;
100 }
101 
103 TLB::getEntry(unsigned Index) const
104 {
105  // Make sure that Index is valid
106  assert(Index<size);
107  return &table[Index];
108 }
109 
110 int
111 TLB::probeEntry(Addr vpn, uint8_t asn) const
112 {
113  // assume not found...
114  int Ind = -1;
115  PageTable::const_iterator i = lookupTable.find(vpn);
116  if (i != lookupTable.end()) {
117  while (i->first == vpn) {
118  int index = i->second;
119  PTE *pte = &table[index];
120 
121  /* 1KB TLB Lookup code - from MIPS ARM Volume III - Rev. 2.50 */
122  Addr Mask = pte->Mask;
123  Addr InvMask = ~Mask;
124  Addr VPN = pte->VPN;
125  if (((vpn & InvMask) == (VPN & InvMask)) &&
126  (pte->G || (asn == pte->asid))) {
127  // We have a VPN + ASID Match
128  Ind = index;
129  break;
130  }
131  ++i;
132  }
133  }
134  DPRINTF(MipsPRA,"VPN: %x, asid: %d, Result of TLBP: %d\n",vpn,asn,Ind);
135  return Ind;
136 }
137 
138 inline Fault
139 TLB::checkCacheability(const RequestPtr &req)
140 {
141  Addr VAddrUncacheable = 0xA0000000;
142  // In MIPS, cacheability is controlled by certain bits of the virtual
143  // address or by the TLB entry
144  if ((req->getVaddr() & VAddrUncacheable) == VAddrUncacheable) {
145  // mark request as uncacheable
147  }
148  return NoFault;
149 }
150 
151 void
152 TLB::insertAt(PTE &pte, unsigned Index, int _smallPages)
153 {
154  smallPages = _smallPages;
155  if (Index > size) {
156  warn("Attempted to write at index (%d) beyond TLB size (%d)",
157  Index, size);
158  } else {
159  // Update TLB
160  DPRINTF(TLB, "TLB[%d]: %x %x %x %x\n",
161  Index, pte.Mask << 11,
162  ((pte.VPN << 11) | pte.asid),
163  ((pte.PFN0 << 6) | (pte.C0 << 3) |
164  (pte.D0 << 2) | (pte.V0 <<1) | pte.G),
165  ((pte.PFN1 <<6) | (pte.C1 << 3) |
166  (pte.D1 << 2) | (pte.V1 <<1) | pte.G));
167  if (table[Index].V0 || table[Index].V1) {
168  // Previous entry is valid
169  PageTable::iterator i = lookupTable.find(table[Index].VPN);
170  lookupTable.erase(i);
171  }
172  table[Index]=pte;
173  // Update fast lookup table
174  lookupTable.insert(std::make_pair(table[Index].VPN, Index));
175  }
176 }
177 
178 // insert a new TLB entry
179 void
180 TLB::insert(Addr addr, PTE &pte)
181 {
182  fatal("TLB Insert not yet implemented\n");
183 }
184 
185 void
187 {
188  DPRINTF(TLB, "flushAll\n");
189  memset(table, 0, sizeof(PTE[size]));
190  lookupTable.clear();
191  nlu = 0;
192 }
193 
194 void
195 TLB::serialize(CheckpointOut &cp) const
196 {
198  SERIALIZE_SCALAR(nlu);
199 
200  for (int i = 0; i < size; i++) {
201  ScopedCheckpointSection sec(cp, csprintf("PTE%d", i));
202  table[i].serialize(cp);
203  }
204 }
205 
206 void
207 TLB::unserialize(CheckpointIn &cp)
208 {
210  UNSERIALIZE_SCALAR(nlu);
211 
212  for (int i = 0; i < size; i++) {
213  ScopedCheckpointSection sec(cp, csprintf("PTE%d", i));
214  table[i].unserialize(cp);
215  if (table[i].V0 || table[i].V1) {
216  lookupTable.insert(std::make_pair(table[i].VPN, i));
217  }
218  }
219 }
220 
221 Fault
222 TLB::translateAtomic(const RequestPtr &req, ThreadContext *tc,
224 {
225  panic_if(FullSystem, "translateAtomic not implemented in full system.");
226  return tc->getProcessPtr()->pTable->translate(req);
227 }
228 
229 void
230 TLB::translateTiming(const RequestPtr &req, ThreadContext *tc,
231  BaseMMU::Translation *translation, BaseMMU::Mode mode)
232 {
233  assert(translation);
234  translation->finish(translateAtomic(req, tc, mode), req, tc, mode);
235 }
236 
237 Fault
238 TLB::translateFunctional(const RequestPtr &req, ThreadContext *tc,
240 {
241  panic_if(FullSystem, "translateAtomic not implemented in full system.");
242  return tc->getProcessPtr()->pTable->translate(req);
243 }
244 
245 Fault
247  ThreadContext *tc, BaseMMU::Mode mode) const
248 {
249  return NoFault;
250 }
251 
252 
253 MipsISA::PTE &
254 TLB::index(bool advance)
255 {
256  PTE *pte = &table[nlu];
257 
258  if (advance)
259  nextnlu();
260 
261  return *pte;
262 }
263 
264 } // namespace gem5
gem5::PowerISA::PTE::V0
bool V0
Definition: pagetable.hh:64
fatal
#define fatal(...)
This implements a cprintf based fatal() function.
Definition: logging.hh:189
gem5::ArmISA::TLB::finalizePhysical
Fault finalizePhysical(const RequestPtr &req, ThreadContext *tc, BaseMMU::Mode mode) const override
Do post-translation physical address finalization.
Definition: tlb.cc:137
gem5::NoFault
constexpr decltype(nullptr) NoFault
Definition: types.hh:260
gem5::SimObject::unserialize
void unserialize(CheckpointIn &cp) override
Unserialize an object.
Definition: sim_object.hh:316
warn
#define warn(...)
Definition: logging.hh:245
gem5::PowerISA::PTE::VPN
Addr VPN
Definition: pagetable.hh:53
gem5::PowerISA::PTE::asid
uint8_t asid
Definition: pagetable.hh:56
gem5::Request::STRICT_ORDER
@ STRICT_ORDER
The request is required to be strictly ordered by CPU models and is non-speculative.
Definition: request.hh:135
UNSERIALIZE_SCALAR
#define UNSERIALIZE_SCALAR(scalar)
Definition: serialize.hh:575
gem5::PowerISA::PTE::C0
uint8_t C0
Definition: pagetable.hh:65
gem5::ArmISA::TLB::table
TlbEntry * table
Definition: tlb.hh:156
gem5::MipsISA::index
Bitfield< 30, 0 > index
Definition: pra_constants.hh:47
gem5::ArmISA::TLB::size
int size
Definition: tlb.hh:157
gem5::BaseMMU::Mode
Mode
Definition: mmu.hh:53
faults.hh
gem5::Request::UNCACHEABLE
@ UNCACHEABLE
The request is to an uncacheable address.
Definition: request.hh:125
pra_constants.hh
gem5::ArmISA::TLB::TLB
TLB(const Params &p)
Definition: tlb.cc:79
tlb.hh
gem5::ArmISA::TLB
Definition: tlb.hh:109
gem5::MipsISA::TLB::TLB
TLB(const Params &p)
gem5::PowerISA::PTE::PFN0
Addr PFN0
Definition: pagetable.hh:62
gem5::csprintf
std::string csprintf(const char *format, const Args &...args)
Definition: cprintf.hh:161
gem5::ArmISA::TLB::lookup
TlbEntry * lookup(Addr vpn, uint16_t asn, vmid_t vmid, bool hyp, bool secure, bool functional, bool ignore_asn, ExceptionLevel target_el, bool in_host, BaseMMU::Mode mode)
Lookup an entry in the TLB.
Definition: tlb.cc:166
gem5::ArmISA::TlbEntry::serialize
void serialize(CheckpointOut &cp) const override
Serialize an object.
Definition: pagetable.hh:306
gem5::ArmISA::i
Bitfield< 7 > i
Definition: misc_types.hh:66
str.hh
gem5::PowerISA::PTE::G
bool G
Definition: pagetable.hh:59
gem5::ArmISA::TLB::translateAtomic
Fault translateAtomic(const RequestPtr &req, ThreadContext *tc, BaseMMU::Mode mode, ArmTranslationType tranType)
Definition: tlb.cc:1256
gem5::SimObject::serialize
void serialize(CheckpointOut &cp) const override
Serialize an object.
Definition: sim_object.hh:315
gem5::PowerISA::PTE::D0
bool D0
Definition: pagetable.hh:63
gem5::ArmISA::TLB::translateFunctional
bool translateFunctional(ThreadContext *tc, Addr vaddr, Addr &paddr)
Do a functional lookup on the TLB (for debugging) and don't modify any internal state.
Definition: tlb.cc:119
gem5::Fault
std::shared_ptr< FaultBase > Fault
Definition: types.hh:255
DPRINTF
#define DPRINTF(x,...)
Definition: trace.hh:186
gem5::MipsISA::p
Bitfield< 0 > p
Definition: pra_constants.hh:326
gem5::RequestPtr
std::shared_ptr< Request > RequestPtr
Definition: request.hh:92
process.hh
utility.hh
gem5::ArmISA::TLB::translateTiming
void translateTiming(const RequestPtr &req, ThreadContext *tc, BaseMMU::Translation *translation, BaseMMU::Mode mode, ArmTranslationType tranType)
Definition: tlb.cc:1298
gem5::ArmISA::TlbEntry::unserialize
void unserialize(CheckpointIn &cp) override
Unserialize an object.
Definition: pagetable.hh:336
inifile.hh
gem5::PowerISA::TLB
Definition: tlb.hh:94
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::ArmISA::TLB::flushAll
void flushAll() override
Reset the entire TLB.
Definition: tlb.cc:274
SERIALIZE_SCALAR
#define SERIALIZE_SCALAR(scalar)
Definition: serialize.hh:568
gem5::PowerISA::PTE::D1
bool D1
Definition: pagetable.hh:69
gem5::PowerISA::PTE::Mask
Addr Mask
Definition: pagetable.hh:49
gem5::FullSystem
bool FullSystem
The FullSystem variable can be used to determine the current mode of simulation.
Definition: root.cc:223
panic_if
#define panic_if(cond,...)
Conditional panic macro that checks the supplied condition and only panics if the condition is true a...
Definition: logging.hh:203
gem5::PowerISA::PTE::V1
bool V1
Definition: pagetable.hh:70
gem5::MipsISA::PTE
Definition: pagetable.hh:43
gem5::ArmISA::TLB::insert
void insert(Addr vaddr, TlbEntry &pte)
Definition: tlb.cc:230
gem5::PowerISA::PTE::PFN1
Addr PFN1
Definition: pagetable.hh:68
gem5::CheckpointOut
std::ostream CheckpointOut
Definition: serialize.hh:66
gem5::PowerISA::PTE
Definition: pagetable.hh:45
trace.hh
gem5::ArmISA::TLB::~TLB
virtual ~TLB()
Definition: tlb.cc:106
page_table.hh
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40
gem5::ArmISA::PTE
Definition: pagetable.hh:61
thread_context.hh
pagetable.hh
gem5::ArmISA::mode
Bitfield< 4, 0 > mode
Definition: misc_types.hh:73
gem5::X86ISA::addr
Bitfield< 3 > addr
Definition: types.hh:84
gem5::PowerISA::PTE::C1
uint8_t C1
Definition: pagetable.hh:71

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