gem5 v24.0.0.0
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reg_class.cc
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1/*
2 * Copyright (c) 2016-2017 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2013 Advanced Micro Devices, Inc.
15 * All rights reserved
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 */
40
41#include "cpu/reg_class.hh"
42
43#include <sstream>
44
45#include "base/cprintf.hh"
46#include "sim/bufval.hh"
47#include "sim/byteswap.hh"
48
49namespace gem5
50{
51
52std::string
54{
55 return csprintf("%s[%d]", id.className(), id.index());
56}
57
58std::string
59RegClassOps::valString(const void *val, const size_t& size) const
60{
61 // If this is just a RegVal, or could be interpreted as one, print it
62 // that way.
63 auto [reg_val_str, reg_val_success] = printUintX(val, size, HostByteOrder);
64 if (reg_val_success)
65 return reg_val_str;
66
67 // Otherwise, print it as a sequence of bytes. Use big endian order so
68 // that the most significant bytes are printed first, like digits in a
69 // regular number.
70
71 return printByteBuf(val, size, ByteOrder::big);
72}
73
74} // namespace gem5
virtual std::string regName(const RegId &id) const
Print the name of the register specified in id.
Definition reg_class.cc:53
virtual std::string valString(const void *val, const size_t &size) const
Print the value of a register pointed to by val of size size.
Definition reg_class.cc:59
Register ID: describe an architectural register with its class and index.
Definition reg_class.hh:94
Bitfield< 30, 0 > index
Bitfield< 63 > val
Definition misc.hh:804
Copyright (c) 2024 - Pranith Kumar Copyright (c) 2020 Inria All rights reserved.
Definition binary32.hh:36
std::pair< std::string, bool > printUintX(const void *buf, std::size_t bytes, ByteOrder endian)
Definition bufval.cc:82
const ByteOrder HostByteOrder
Definition byteswap.hh:171
std::string csprintf(const char *format, const Args &...args)
Definition cprintf.hh:161
std::string printByteBuf(const void *buf, std::size_t bytes, ByteOrder endian, std::size_t chunk_size)
Definition bufval.cc:99

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