gem5  v21.1.0.2
pseudo.hh
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28 
29 #ifndef __ARCH_RISCV_INSTS_PSEUDO_HH__
30 #define __ARCH_RISCV_INSTS_PSEUDO_HH__
31 
32 #include <string>
33 
35 
36 namespace gem5
37 {
38 
39 namespace RiscvISA
40 {
41 
42 class PseudoOp : public RiscvStaticInst
43 {
44  protected:
46 
47  std::string generateDisassembly(
48  Addr pc, const loader::SymbolTable *symtab) const override
49  {
50  return mnemonic;
51  }
52 };
53 
54 } // namespace RiscvISA
55 } // namespace gem5
56 
57 #endif // __ARCH_RISCV_INSTS_PSEUDO_HH__
gem5::RiscvISA::RiscvStaticInst
Base class for all RISC-V static instructions.
Definition: static_inst.hh:49
gem5::RiscvISA::RiscvStaticInst::RiscvStaticInst
RiscvStaticInst(const char *_mnemonic, ExtMachInst _machInst, OpClass __opClass)
Definition: static_inst.hh:52
gem5::loader::SymbolTable
Definition: symtab.hh:65
gem5::RiscvISA::pc
Bitfield< 4 > pc
Definition: pra_constants.hh:243
static_inst.hh
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::RiscvISA::PseudoOp
Definition: pseudo.hh:42
gem5::RiscvISA::PseudoOp::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: pseudo.hh:47
gem5::StaticInst::mnemonic
const char * mnemonic
Base mnemonic (e.g., "add").
Definition: static_inst.hh:281
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40

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