gem5  v22.0.0.1
vio_mmio.hh
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38 
39 #ifndef __DEV_ARM_VIO_MMIO_HH__
40 #define __DEV_ARM_VIO_MMIO_HH__
41 
42 #include "dev/riscv/hifive.hh"
43 #include "dev/riscv/plic_device.hh"
44 #include "dev/virtio/base.hh"
45 
46 namespace gem5
47 {
48 
49 struct RiscvMmioVirtIOParams;
50 
51 namespace RiscvISA
52 {
53 
54 class MmioVirtIO : public PlicIntDevice
55 {
56  public:
57  MmioVirtIO(const RiscvMmioVirtIOParams &params);
58  virtual ~MmioVirtIO();
59 
60  protected: // BasicPioDevice
61  Tick read(PacketPtr pkt) override;
62  Tick write(PacketPtr pkt) override;
63 
64  protected:
68  enum : Addr
69  {
70  OFF_MAGIC = 0x00,
71  OFF_VERSION = 0x04,
72  OFF_DEVICE_ID = 0x08,
73  OFF_VENDOR_ID = 0x0C,
81  OFF_QUEUE_NUM = 0x38,
83  OFF_QUEUE_PFN = 0x40,
87  OFF_STATUS = 0x70,
88  OFF_CONFIG = 0x100,
89  };
90 
93  enum
94  {
95  INT_USED_RING = 1 << 0,
96  INT_CONFIG = 1 << 1,
97  };
98 
99  static const uint32_t MAGIC = 0x74726976;
100  static const uint32_t VERSION = 1;
101  static const uint32_t VENDOR_ID = 0x1AF4;
102 
103 
104  uint32_t read(Addr offset);
105  void write(Addr offset, uint32_t value);
106 
107  void kick();
108  void setInterrupts(uint32_t value);
109 
112  uint32_t pageSize;
113  uint32_t interruptStatus;
114 
115  protected: // Params
117 };
118 
119 } // namespace RiscvISA
120 
121 } // namespace gem5
122 
123 #endif // __DEV_ARM_VIO_MMIO_HH__
gem5::RiscvISA::MmioVirtIO::OFF_QUEUE_NUM
@ OFF_QUEUE_NUM
Definition: vio_mmio.hh:81
gem5::RiscvISA::MmioVirtIO::OFF_GUEST_FEATURES
@ OFF_GUEST_FEATURES
Definition: vio_mmio.hh:76
gem5::RiscvISA::MmioVirtIO::~MmioVirtIO
virtual ~MmioVirtIO()
Definition: vio_mmio.cc:60
gem5::RiscvISA::MmioVirtIO::OFF_INTERRUPT_STATUS
@ OFF_INTERRUPT_STATUS
Definition: vio_mmio.hh:85
gem5::RiscvISA::MmioVirtIO::OFF_QUEUE_PFN
@ OFF_QUEUE_PFN
Definition: vio_mmio.hh:83
gem5::RiscvISA::MmioVirtIO::OFF_QUEUE_NUM_MAX
@ OFF_QUEUE_NUM_MAX
Definition: vio_mmio.hh:80
gem5::RiscvISA::MmioVirtIO::hostFeaturesSelect
uint32_t hostFeaturesSelect
Definition: vio_mmio.hh:110
gem5::RiscvISA::MmioVirtIO::VERSION
static const uint32_t VERSION
Definition: vio_mmio.hh:100
gem5::PlicIntDevice
Definition: plic_device.hh:51
gem5::RiscvISA::MmioVirtIO::OFF_QUEUE_ALIGN
@ OFF_QUEUE_ALIGN
Definition: vio_mmio.hh:82
gem5::RiscvISA::MmioVirtIO::OFF_QUEUE_NOTIFY
@ OFF_QUEUE_NOTIFY
Definition: vio_mmio.hh:84
base.hh
gem5::RiscvISA::MmioVirtIO::guestFeaturesSelect
uint32_t guestFeaturesSelect
Definition: vio_mmio.hh:111
gem5::RiscvISA::MmioVirtIO::OFF_HOST_FEATURES
@ OFF_HOST_FEATURES
Definition: vio_mmio.hh:74
gem5::RiscvISA::MmioVirtIO::write
Tick write(PacketPtr pkt) override
Pure virtual function that the device must implement.
Definition: vio_mmio.cc:162
hifive.hh
gem5::Packet
A Packet is used to encapsulate a transfer between two objects in the memory system (e....
Definition: packet.hh:291
gem5::RiscvISA::MmioVirtIO::OFF_HOST_FEATURES_SELECT
@ OFF_HOST_FEATURES_SELECT
Definition: vio_mmio.hh:75
gem5::Tick
uint64_t Tick
Tick count type.
Definition: types.hh:58
gem5::RiscvISA::MmioVirtIO::OFF_STATUS
@ OFF_STATUS
Definition: vio_mmio.hh:87
gem5::RiscvISA::MmioVirtIO::OFF_VERSION
@ OFF_VERSION
Definition: vio_mmio.hh:71
gem5::RiscvISA::MmioVirtIO::MmioVirtIO
MmioVirtIO(const RiscvMmioVirtIOParams &params)
Definition: vio_mmio.cc:52
gem5::RiscvISA::MmioVirtIO::OFF_CONFIG
@ OFF_CONFIG
Definition: vio_mmio.hh:88
gem5::ArmISA::offset
Bitfield< 23, 0 > offset
Definition: types.hh:144
gem5::VirtIODeviceBase
Base class for all VirtIO-based devices.
Definition: base.hh:587
gem5::RiscvISA::MmioVirtIO::OFF_GUEST_FEATURES_SELECT
@ OFF_GUEST_FEATURES_SELECT
Definition: vio_mmio.hh:77
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::RiscvISA::MmioVirtIO::setInterrupts
void setInterrupts(uint32_t value)
Definition: vio_mmio.cc:268
gem5::RiscvISA::MmioVirtIO
Definition: vio_mmio.hh:54
gem5::RiscvISA::MmioVirtIO::OFF_QUEUE_SELECT
@ OFF_QUEUE_SELECT
Definition: vio_mmio.hh:79
gem5::RiscvISA::MmioVirtIO::pageSize
uint32_t pageSize
Definition: vio_mmio.hh:112
gem5::RiscvISA::MmioVirtIO::OFF_INTERRUPT_ACK
@ OFF_INTERRUPT_ACK
Definition: vio_mmio.hh:86
plic_device.hh
gem5::RiscvISA::MmioVirtIO::kick
void kick()
Definition: vio_mmio.cc:261
gem5::RiscvISA::MmioVirtIO::INT_CONFIG
@ INT_CONFIG
Definition: vio_mmio.hh:96
gem5::RiscvISA::MmioVirtIO::MAGIC
static const uint32_t MAGIC
Definition: vio_mmio.hh:99
gem5::RiscvISA::MmioVirtIO::VENDOR_ID
static const uint32_t VENDOR_ID
Definition: vio_mmio.hh:101
gem5::RiscvISA::MmioVirtIO::INT_USED_RING
@ INT_USED_RING
Definition: vio_mmio.hh:95
gem5::PlicIntDevice::params
const Params & params() const
Definition: plic_device.hh:62
gem5::RiscvISA::MmioVirtIO::vio
VirtIODeviceBase & vio
Definition: vio_mmio.hh:116
gem5::RiscvISA::MmioVirtIO::interruptStatus
uint32_t interruptStatus
Definition: vio_mmio.hh:113
gem5::RiscvISA::MmioVirtIO::OFF_DEVICE_ID
@ OFF_DEVICE_ID
Definition: vio_mmio.hh:72
gem5::RiscvISA::MmioVirtIO::OFF_MAGIC
@ OFF_MAGIC
Definition: vio_mmio.hh:70
gem5::RiscvISA::MmioVirtIO::OFF_GUEST_PAGE_SIZE
@ OFF_GUEST_PAGE_SIZE
Definition: vio_mmio.hh:78
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: gpu_translation_state.hh:37
gem5::RiscvISA::MmioVirtIO::read
Tick read(PacketPtr pkt) override
Pure virtual function that the device must implement.
Definition: vio_mmio.cc:65
gem5::RiscvISA::MmioVirtIO::OFF_VENDOR_ID
@ OFF_VENDOR_ID
Definition: vio_mmio.hh:73

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